1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28
29 #include "amdgpu.h"
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
32
33 #include "gc/gc_10_1_0_offset.h"
34 #include "gc/gc_10_1_0_sh_mask.h"
35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
37
38 #include "soc15_common.h"
39 #include "soc15.h"
40 #include "navi10_sdma_pkt_open.h"
41 #include "nbio_v2_3.h"
42 #include "sdma_common.h"
43 #include "sdma_v5_0.h"
44
45 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
46 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
47
48 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
49 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
50
51 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
52 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
53
54 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma.bin");
55 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma1.bin");
56
57 #define SDMA1_REG_OFFSET 0x600
58 #define SDMA0_HYP_DEC_REG_START 0x5880
59 #define SDMA0_HYP_DEC_REG_END 0x5893
60 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
61
62 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
63 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
64 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
65 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);
66
67 static const struct soc15_reg_golden golden_settings_sdma_5[] = {
68 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
69 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
70 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
71 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
72 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
73 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
74 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
75 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
76 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
77 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
78 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
79 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
80 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
81 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
82 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
83 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
84 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
85 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
86 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
87 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
88 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
89 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
90 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
91 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
92 };
93
94 static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = {
95 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
96 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
115 };
116
117 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
120 };
121
122 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
125 };
126
127 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
134 };
135
136 static const struct soc15_reg_golden golden_settings_sdma_cyan_skillfish[] = {
137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x007fffff, 0x004c5c00),
151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x007fffff, 0x004c5c00)
165 };
166
sdma_v5_0_get_reg_offset(struct amdgpu_device * adev,u32 instance,u32 internal_offset)167 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
168 {
169 u32 base;
170
171 if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
172 internal_offset <= SDMA0_HYP_DEC_REG_END) {
173 base = adev->reg_offset[GC_HWIP][0][1];
174 if (instance == 1)
175 internal_offset += SDMA1_HYP_DEC_REG_OFFSET;
176 } else {
177 base = adev->reg_offset[GC_HWIP][0][0];
178 if (instance == 1)
179 internal_offset += SDMA1_REG_OFFSET;
180 }
181
182 return base + internal_offset;
183 }
184
sdma_v5_0_init_golden_registers(struct amdgpu_device * adev)185 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
186 {
187 switch (adev->ip_versions[SDMA0_HWIP][0]) {
188 case IP_VERSION(5, 0, 0):
189 soc15_program_register_sequence(adev,
190 golden_settings_sdma_5,
191 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
192 soc15_program_register_sequence(adev,
193 golden_settings_sdma_nv10,
194 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
195 break;
196 case IP_VERSION(5, 0, 2):
197 soc15_program_register_sequence(adev,
198 golden_settings_sdma_5,
199 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
200 soc15_program_register_sequence(adev,
201 golden_settings_sdma_nv14,
202 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
203 break;
204 case IP_VERSION(5, 0, 5):
205 if (amdgpu_sriov_vf(adev))
206 soc15_program_register_sequence(adev,
207 golden_settings_sdma_5_sriov,
208 (const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov));
209 else
210 soc15_program_register_sequence(adev,
211 golden_settings_sdma_5,
212 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
213 soc15_program_register_sequence(adev,
214 golden_settings_sdma_nv12,
215 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
216 break;
217 case IP_VERSION(5, 0, 1):
218 soc15_program_register_sequence(adev,
219 golden_settings_sdma_cyan_skillfish,
220 (const u32)ARRAY_SIZE(golden_settings_sdma_cyan_skillfish));
221 break;
222 default:
223 break;
224 }
225 }
226
227 /**
228 * sdma_v5_0_init_microcode - load ucode images from disk
229 *
230 * @adev: amdgpu_device pointer
231 *
232 * Use the firmware interface to load the ucode images into
233 * the driver (not loaded into hw).
234 * Returns 0 on success, error on failure.
235 */
236
237 // emulation only, won't work on real chip
238 // navi10 real chip need to use PSP to load firmware
sdma_v5_0_init_microcode(struct amdgpu_device * adev)239 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
240 { int ret, i;
241
242 if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 0, 5)))
243 return 0;
244
245 for (i = 0; i < adev->sdma.num_instances; i++) {
246 ret = amdgpu_sdma_init_microcode(adev, i, false);
247 if (ret)
248 return ret;
249 }
250
251 return ret;
252 }
253
sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring * ring)254 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring)
255 {
256 unsigned ret;
257
258 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
259 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
260 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
261 amdgpu_ring_write(ring, 1);
262 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
263 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
264
265 return ret;
266 }
267
sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring * ring,unsigned offset)268 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
269 unsigned offset)
270 {
271 unsigned cur;
272
273 BUG_ON(offset > ring->buf_mask);
274 BUG_ON(ring->ring[offset] != 0x55aa55aa);
275
276 cur = (ring->wptr - 1) & ring->buf_mask;
277 if (cur > offset)
278 ring->ring[offset] = cur - offset;
279 else
280 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
281 }
282
283 /**
284 * sdma_v5_0_ring_get_rptr - get the current read pointer
285 *
286 * @ring: amdgpu ring pointer
287 *
288 * Get the current rptr from the hardware (NAVI10+).
289 */
sdma_v5_0_ring_get_rptr(struct amdgpu_ring * ring)290 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
291 {
292 u64 *rptr;
293
294 /* XXX check if swapping is necessary on BE */
295 rptr = (u64 *)ring->rptr_cpu_addr;
296
297 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
298 return ((*rptr) >> 2);
299 }
300
301 /**
302 * sdma_v5_0_ring_get_wptr - get the current write pointer
303 *
304 * @ring: amdgpu ring pointer
305 *
306 * Get the current wptr from the hardware (NAVI10+).
307 */
sdma_v5_0_ring_get_wptr(struct amdgpu_ring * ring)308 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
309 {
310 struct amdgpu_device *adev = ring->adev;
311 u64 wptr;
312
313 if (ring->use_doorbell) {
314 /* XXX check if swapping is necessary on BE */
315 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
316 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
317 } else {
318 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
319 wptr = wptr << 32;
320 wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
321 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
322 }
323
324 return wptr >> 2;
325 }
326
327 /**
328 * sdma_v5_0_ring_set_wptr - commit the write pointer
329 *
330 * @ring: amdgpu ring pointer
331 *
332 * Write the wptr back to the hardware (NAVI10+).
333 */
sdma_v5_0_ring_set_wptr(struct amdgpu_ring * ring)334 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
335 {
336 struct amdgpu_device *adev = ring->adev;
337 uint32_t *wptr_saved;
338 uint32_t *is_queue_unmap;
339 uint64_t aggregated_db_index;
340 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_DMA].mqd_size;
341
342 DRM_DEBUG("Setting write pointer\n");
343 if (ring->is_mes_queue) {
344 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
345 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
346 sizeof(uint32_t));
347 aggregated_db_index =
348 amdgpu_mes_get_aggregated_doorbell_index(adev,
349 AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
350
351 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
352 ring->wptr << 2);
353 *wptr_saved = ring->wptr << 2;
354 if (*is_queue_unmap) {
355 WDOORBELL64(aggregated_db_index, ring->wptr << 2);
356 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
357 ring->doorbell_index, ring->wptr << 2);
358 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
359 } else {
360 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
361 ring->doorbell_index, ring->wptr << 2);
362 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
363
364 if (*is_queue_unmap)
365 WDOORBELL64(aggregated_db_index,
366 ring->wptr << 2);
367 }
368 } else {
369 if (ring->use_doorbell) {
370 DRM_DEBUG("Using doorbell -- "
371 "wptr_offs == 0x%08x "
372 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
373 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
374 ring->wptr_offs,
375 lower_32_bits(ring->wptr << 2),
376 upper_32_bits(ring->wptr << 2));
377 /* XXX check if swapping is necessary on BE */
378 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
379 ring->wptr << 2);
380 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
381 ring->doorbell_index, ring->wptr << 2);
382 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
383 } else {
384 DRM_DEBUG("Not using doorbell -- "
385 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
386 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
387 ring->me,
388 lower_32_bits(ring->wptr << 2),
389 ring->me,
390 upper_32_bits(ring->wptr << 2));
391 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,
392 ring->me, mmSDMA0_GFX_RB_WPTR),
393 lower_32_bits(ring->wptr << 2));
394 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,
395 ring->me, mmSDMA0_GFX_RB_WPTR_HI),
396 upper_32_bits(ring->wptr << 2));
397 }
398 }
399 }
400
sdma_v5_0_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)401 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
402 {
403 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
404 int i;
405
406 for (i = 0; i < count; i++)
407 if (sdma && sdma->burst_nop && (i == 0))
408 amdgpu_ring_write(ring, ring->funcs->nop |
409 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
410 else
411 amdgpu_ring_write(ring, ring->funcs->nop);
412 }
413
414 /**
415 * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
416 *
417 * @ring: amdgpu ring pointer
418 * @job: job to retrieve vmid from
419 * @ib: IB object to schedule
420 * @flags: unused
421 *
422 * Schedule an IB in the DMA ring (NAVI10).
423 */
sdma_v5_0_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)424 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
425 struct amdgpu_job *job,
426 struct amdgpu_ib *ib,
427 uint32_t flags)
428 {
429 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
430 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
431
432 /* An IB packet must end on a 8 DW boundary--the next dword
433 * must be on a 8-dword boundary. Our IB packet below is 6
434 * dwords long, thus add x number of NOPs, such that, in
435 * modular arithmetic,
436 * wptr + 6 + x = 8k, k >= 0, which in C is,
437 * (wptr + 6 + x) % 8 = 0.
438 * The expression below, is a solution of x.
439 */
440 sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
441
442 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
443 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
444 /* base must be 32 byte aligned */
445 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
446 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
447 amdgpu_ring_write(ring, ib->length_dw);
448 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
449 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
450 }
451
452 /**
453 * sdma_v5_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
454 *
455 * @ring: amdgpu ring pointer
456 *
457 * flush the IB by graphics cache rinse.
458 */
sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring * ring)459 static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
460 {
461 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
462 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
463 SDMA_GCR_GLI_INV(1);
464
465 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
466 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
467 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
468 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
469 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
470 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
471 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
472 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
473 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
474 }
475
476 /**
477 * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
478 *
479 * @ring: amdgpu ring pointer
480 *
481 * Emit an hdp flush packet on the requested DMA ring.
482 */
sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring * ring)483 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
484 {
485 struct amdgpu_device *adev = ring->adev;
486 u32 ref_and_mask = 0;
487 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
488
489 if (ring->me == 0)
490 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
491 else
492 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
493
494 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
495 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
496 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
497 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
498 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
499 amdgpu_ring_write(ring, ref_and_mask); /* reference */
500 amdgpu_ring_write(ring, ref_and_mask); /* mask */
501 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
502 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
503 }
504
505 /**
506 * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
507 *
508 * @ring: amdgpu ring pointer
509 * @addr: address
510 * @seq: sequence number
511 * @flags: fence related flags
512 *
513 * Add a DMA fence packet to the ring to write
514 * the fence seq number and DMA trap packet to generate
515 * an interrupt if needed (NAVI10).
516 */
sdma_v5_0_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)517 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
518 unsigned flags)
519 {
520 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
521 /* write the fence */
522 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
523 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
524 /* zero in first two bits */
525 BUG_ON(addr & 0x3);
526 amdgpu_ring_write(ring, lower_32_bits(addr));
527 amdgpu_ring_write(ring, upper_32_bits(addr));
528 amdgpu_ring_write(ring, lower_32_bits(seq));
529
530 /* optionally write high bits as well */
531 if (write64bit) {
532 addr += 4;
533 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
534 SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
535 /* zero in first two bits */
536 BUG_ON(addr & 0x3);
537 amdgpu_ring_write(ring, lower_32_bits(addr));
538 amdgpu_ring_write(ring, upper_32_bits(addr));
539 amdgpu_ring_write(ring, upper_32_bits(seq));
540 }
541
542 if (flags & AMDGPU_FENCE_FLAG_INT) {
543 uint32_t ctx = ring->is_mes_queue ?
544 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
545 /* generate an interrupt */
546 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
547 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
548 }
549 }
550
551
552 /**
553 * sdma_v5_0_gfx_stop - stop the gfx async dma engines
554 *
555 * @adev: amdgpu_device pointer
556 *
557 * Stop the gfx async dma ring buffers (NAVI10).
558 */
sdma_v5_0_gfx_stop(struct amdgpu_device * adev)559 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
560 {
561 u32 rb_cntl, ib_cntl;
562 int i;
563
564 amdgpu_sdma_unset_buffer_funcs_helper(adev);
565
566 for (i = 0; i < adev->sdma.num_instances; i++) {
567 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
568 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
569 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
570 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
571 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
572 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
573 }
574 }
575
576 /**
577 * sdma_v5_0_rlc_stop - stop the compute async dma engines
578 *
579 * @adev: amdgpu_device pointer
580 *
581 * Stop the compute async dma queues (NAVI10).
582 */
sdma_v5_0_rlc_stop(struct amdgpu_device * adev)583 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
584 {
585 /* XXX todo */
586 }
587
588 /**
589 * sdma_v5_0_ctx_switch_enable - stop the async dma engines context switch
590 *
591 * @adev: amdgpu_device pointer
592 * @enable: enable/disable the DMA MEs context switch.
593 *
594 * Halt or unhalt the async dma engines context switch (NAVI10).
595 */
sdma_v5_0_ctx_switch_enable(struct amdgpu_device * adev,bool enable)596 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
597 {
598 u32 f32_cntl = 0, phase_quantum = 0;
599 int i;
600
601 if (amdgpu_sdma_phase_quantum) {
602 unsigned value = amdgpu_sdma_phase_quantum;
603 unsigned unit = 0;
604
605 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
606 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
607 value = (value + 1) >> 1;
608 unit++;
609 }
610 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
611 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
612 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
613 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
614 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
615 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
616 WARN_ONCE(1,
617 "clamping sdma_phase_quantum to %uK clock cycles\n",
618 value << unit);
619 }
620 phase_quantum =
621 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
622 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
623 }
624
625 for (i = 0; i < adev->sdma.num_instances; i++) {
626 if (!amdgpu_sriov_vf(adev)) {
627 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
628 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
629 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
630 }
631
632 if (enable && amdgpu_sdma_phase_quantum) {
633 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
634 phase_quantum);
635 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
636 phase_quantum);
637 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
638 phase_quantum);
639 }
640 if (!amdgpu_sriov_vf(adev))
641 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
642 }
643
644 }
645
646 /**
647 * sdma_v5_0_enable - stop the async dma engines
648 *
649 * @adev: amdgpu_device pointer
650 * @enable: enable/disable the DMA MEs.
651 *
652 * Halt or unhalt the async dma engines (NAVI10).
653 */
sdma_v5_0_enable(struct amdgpu_device * adev,bool enable)654 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
655 {
656 u32 f32_cntl;
657 int i;
658
659 if (!enable) {
660 sdma_v5_0_gfx_stop(adev);
661 sdma_v5_0_rlc_stop(adev);
662 }
663
664 if (amdgpu_sriov_vf(adev))
665 return;
666
667 for (i = 0; i < adev->sdma.num_instances; i++) {
668 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
669 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
670 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
671 }
672 }
673
674 /**
675 * sdma_v5_0_gfx_resume - setup and start the async dma engines
676 *
677 * @adev: amdgpu_device pointer
678 *
679 * Set up the gfx DMA ring buffers and enable them (NAVI10).
680 * Returns 0 for success, error for failure.
681 */
sdma_v5_0_gfx_resume(struct amdgpu_device * adev)682 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
683 {
684 struct amdgpu_ring *ring;
685 u32 rb_cntl, ib_cntl;
686 u32 rb_bufsz;
687 u32 doorbell;
688 u32 doorbell_offset;
689 u32 temp;
690 u32 wptr_poll_cntl;
691 u64 wptr_gpu_addr;
692 int i, r;
693
694 for (i = 0; i < adev->sdma.num_instances; i++) {
695 ring = &adev->sdma.instance[i].ring;
696
697 if (!amdgpu_sriov_vf(adev))
698 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
699
700 /* Set ring buffer size in dwords */
701 rb_bufsz = order_base_2(ring->ring_size / 4);
702 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
703 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
704 #ifdef __BIG_ENDIAN
705 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
706 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
707 RPTR_WRITEBACK_SWAP_ENABLE, 1);
708 #endif
709 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
710
711 /* Initialize the ring buffer's read and write pointers */
712 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
713 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
714 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
715 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
716
717 /* setup the wptr shadow polling */
718 wptr_gpu_addr = ring->wptr_gpu_addr;
719 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
720 lower_32_bits(wptr_gpu_addr));
721 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
722 upper_32_bits(wptr_gpu_addr));
723 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
724 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
725 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
726 SDMA0_GFX_RB_WPTR_POLL_CNTL,
727 F32_POLL_ENABLE, 1);
728 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
729 wptr_poll_cntl);
730
731 /* set the wb address whether it's enabled or not */
732 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
733 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
734 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
735 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
736
737 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
738
739 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE),
740 ring->gpu_addr >> 8);
741 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),
742 ring->gpu_addr >> 40);
743
744 ring->wptr = 0;
745
746 /* before programing wptr to a less value, need set minor_ptr_update first */
747 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
748
749 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
750 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),
751 lower_32_bits(ring->wptr << 2));
752 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI),
753 upper_32_bits(ring->wptr << 2));
754 }
755
756 doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
757 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
758 mmSDMA0_GFX_DOORBELL_OFFSET));
759
760 if (ring->use_doorbell) {
761 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
762 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
763 OFFSET, ring->doorbell_index);
764 } else {
765 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
766 }
767 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
768 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET),
769 doorbell_offset);
770
771 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
772 ring->doorbell_index, 20);
773
774 if (amdgpu_sriov_vf(adev))
775 sdma_v5_0_ring_set_wptr(ring);
776
777 /* set minor_ptr_update to 0 after wptr programed */
778 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
779
780 if (!amdgpu_sriov_vf(adev)) {
781 /* set utc l1 enable flag always to 1 */
782 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
783 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
784
785 /* enable MCBP */
786 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
787 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
788
789 /* Set up RESP_MODE to non-copy addresses */
790 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
791 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
792 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
793 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
794
795 /* program default cache read and write policy */
796 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
797 /* clean read policy and write policy bits */
798 temp &= 0xFF0FFF;
799 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
800 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
801 }
802
803 if (!amdgpu_sriov_vf(adev)) {
804 /* unhalt engine */
805 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
806 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
807 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
808 }
809
810 /* enable DMA RB */
811 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
812 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
813
814 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
815 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
816 #ifdef __BIG_ENDIAN
817 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
818 #endif
819 /* enable DMA IBs */
820 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
821
822 ring->sched.ready = true;
823
824 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
825 sdma_v5_0_ctx_switch_enable(adev, true);
826 sdma_v5_0_enable(adev, true);
827 }
828
829 r = amdgpu_ring_test_helper(ring);
830 if (r)
831 return r;
832
833 if (adev->mman.buffer_funcs_ring == ring)
834 amdgpu_ttm_set_buffer_funcs_status(adev, true);
835 }
836
837 return 0;
838 }
839
840 /**
841 * sdma_v5_0_rlc_resume - setup and start the async dma engines
842 *
843 * @adev: amdgpu_device pointer
844 *
845 * Set up the compute DMA queues and enable them (NAVI10).
846 * Returns 0 for success, error for failure.
847 */
sdma_v5_0_rlc_resume(struct amdgpu_device * adev)848 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev)
849 {
850 return 0;
851 }
852
853 /**
854 * sdma_v5_0_load_microcode - load the sDMA ME ucode
855 *
856 * @adev: amdgpu_device pointer
857 *
858 * Loads the sDMA0/1 ucode.
859 * Returns 0 for success, -EINVAL if the ucode is not available.
860 */
sdma_v5_0_load_microcode(struct amdgpu_device * adev)861 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev)
862 {
863 const struct sdma_firmware_header_v1_0 *hdr;
864 const __le32 *fw_data;
865 u32 fw_size;
866 int i, j;
867
868 /* halt the MEs */
869 sdma_v5_0_enable(adev, false);
870
871 for (i = 0; i < adev->sdma.num_instances; i++) {
872 if (!adev->sdma.instance[i].fw)
873 return -EINVAL;
874
875 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
876 amdgpu_ucode_print_sdma_hdr(&hdr->header);
877 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
878
879 fw_data = (const __le32 *)
880 (adev->sdma.instance[i].fw->data +
881 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
882
883 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
884
885 for (j = 0; j < fw_size; j++) {
886 if (amdgpu_emu_mode == 1 && j % 500 == 0)
887 msleep(1);
888 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
889 }
890
891 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
892 }
893
894 return 0;
895 }
896
897 /**
898 * sdma_v5_0_start - setup and start the async dma engines
899 *
900 * @adev: amdgpu_device pointer
901 *
902 * Set up the DMA engines and enable them (NAVI10).
903 * Returns 0 for success, error for failure.
904 */
sdma_v5_0_start(struct amdgpu_device * adev)905 static int sdma_v5_0_start(struct amdgpu_device *adev)
906 {
907 int r = 0;
908
909 if (amdgpu_sriov_vf(adev)) {
910 sdma_v5_0_ctx_switch_enable(adev, false);
911 sdma_v5_0_enable(adev, false);
912
913 /* set RB registers */
914 r = sdma_v5_0_gfx_resume(adev);
915 return r;
916 }
917
918 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
919 r = sdma_v5_0_load_microcode(adev);
920 if (r)
921 return r;
922 }
923
924 /* unhalt the MEs */
925 sdma_v5_0_enable(adev, true);
926 /* enable sdma ring preemption */
927 sdma_v5_0_ctx_switch_enable(adev, true);
928
929 /* start the gfx rings and rlc compute queues */
930 r = sdma_v5_0_gfx_resume(adev);
931 if (r)
932 return r;
933 r = sdma_v5_0_rlc_resume(adev);
934
935 return r;
936 }
937
sdma_v5_0_mqd_init(struct amdgpu_device * adev,void * mqd,struct amdgpu_mqd_prop * prop)938 static int sdma_v5_0_mqd_init(struct amdgpu_device *adev, void *mqd,
939 struct amdgpu_mqd_prop *prop)
940 {
941 struct v10_sdma_mqd *m = mqd;
942 uint64_t wb_gpu_addr;
943
944 m->sdmax_rlcx_rb_cntl =
945 order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
946 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
947 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
948 1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT;
949
950 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
951 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
952
953 m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,
954 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
955
956 wb_gpu_addr = prop->wptr_gpu_addr;
957 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
958 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
959
960 wb_gpu_addr = prop->rptr_gpu_addr;
961 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
962 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
963
964 m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,
965 mmSDMA0_GFX_IB_CNTL));
966
967 m->sdmax_rlcx_doorbell_offset =
968 prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
969
970 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1);
971
972 return 0;
973 }
974
sdma_v5_0_set_mqd_funcs(struct amdgpu_device * adev)975 static void sdma_v5_0_set_mqd_funcs(struct amdgpu_device *adev)
976 {
977 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd);
978 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_0_mqd_init;
979 }
980
981 /**
982 * sdma_v5_0_ring_test_ring - simple async dma engine test
983 *
984 * @ring: amdgpu_ring structure holding ring information
985 *
986 * Test the DMA engine by writing using it to write an
987 * value to memory. (NAVI10).
988 * Returns 0 for success, error for failure.
989 */
sdma_v5_0_ring_test_ring(struct amdgpu_ring * ring)990 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
991 {
992 struct amdgpu_device *adev = ring->adev;
993 unsigned i;
994 unsigned index;
995 int r;
996 u32 tmp;
997 u64 gpu_addr;
998 volatile uint32_t *cpu_ptr = NULL;
999
1000 tmp = 0xCAFEDEAD;
1001
1002 if (ring->is_mes_queue) {
1003 uint32_t offset = 0;
1004 offset = amdgpu_mes_ctx_get_offs(ring,
1005 AMDGPU_MES_CTX_PADDING_OFFS);
1006 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1007 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1008 *cpu_ptr = tmp;
1009 } else {
1010 r = amdgpu_device_wb_get(adev, &index);
1011 if (r) {
1012 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
1013 return r;
1014 }
1015
1016 gpu_addr = adev->wb.gpu_addr + (index * 4);
1017 adev->wb.wb[index] = cpu_to_le32(tmp);
1018 }
1019
1020 r = amdgpu_ring_alloc(ring, 20);
1021 if (r) {
1022 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
1023 amdgpu_device_wb_free(adev, index);
1024 return r;
1025 }
1026
1027 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1028 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1029 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1030 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1031 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1032 amdgpu_ring_write(ring, 0xDEADBEEF);
1033 amdgpu_ring_commit(ring);
1034
1035 for (i = 0; i < adev->usec_timeout; i++) {
1036 if (ring->is_mes_queue)
1037 tmp = le32_to_cpu(*cpu_ptr);
1038 else
1039 tmp = le32_to_cpu(adev->wb.wb[index]);
1040 if (tmp == 0xDEADBEEF)
1041 break;
1042 if (amdgpu_emu_mode == 1)
1043 msleep(1);
1044 else
1045 udelay(1);
1046 }
1047
1048 if (i >= adev->usec_timeout)
1049 r = -ETIMEDOUT;
1050
1051 if (!ring->is_mes_queue)
1052 amdgpu_device_wb_free(adev, index);
1053
1054 return r;
1055 }
1056
1057 /**
1058 * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
1059 *
1060 * @ring: amdgpu_ring structure holding ring information
1061 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1062 *
1063 * Test a simple IB in the DMA ring (NAVI10).
1064 * Returns 0 on success, error on failure.
1065 */
sdma_v5_0_ring_test_ib(struct amdgpu_ring * ring,long timeout)1066 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1067 {
1068 struct amdgpu_device *adev = ring->adev;
1069 struct amdgpu_ib ib;
1070 struct dma_fence *f = NULL;
1071 unsigned index;
1072 long r;
1073 u32 tmp = 0;
1074 u64 gpu_addr;
1075 volatile uint32_t *cpu_ptr = NULL;
1076
1077 tmp = 0xCAFEDEAD;
1078 memset(&ib, 0, sizeof(ib));
1079
1080 if (ring->is_mes_queue) {
1081 uint32_t offset = 0;
1082 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
1083 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1084 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1085
1086 offset = amdgpu_mes_ctx_get_offs(ring,
1087 AMDGPU_MES_CTX_PADDING_OFFS);
1088 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1089 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1090 *cpu_ptr = tmp;
1091 } else {
1092 r = amdgpu_device_wb_get(adev, &index);
1093 if (r) {
1094 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
1095 return r;
1096 }
1097
1098 gpu_addr = adev->wb.gpu_addr + (index * 4);
1099 adev->wb.wb[index] = cpu_to_le32(tmp);
1100
1101 r = amdgpu_ib_get(adev, NULL, 256,
1102 AMDGPU_IB_POOL_DIRECT, &ib);
1103 if (r) {
1104 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1105 goto err0;
1106 }
1107 }
1108
1109 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1110 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1111 ib.ptr[1] = lower_32_bits(gpu_addr);
1112 ib.ptr[2] = upper_32_bits(gpu_addr);
1113 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1114 ib.ptr[4] = 0xDEADBEEF;
1115 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1116 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1117 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1118 ib.length_dw = 8;
1119
1120 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1121 if (r)
1122 goto err1;
1123
1124 r = dma_fence_wait_timeout(f, false, timeout);
1125 if (r == 0) {
1126 DRM_ERROR("amdgpu: IB test timed out\n");
1127 r = -ETIMEDOUT;
1128 goto err1;
1129 } else if (r < 0) {
1130 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1131 goto err1;
1132 }
1133
1134 if (ring->is_mes_queue)
1135 tmp = le32_to_cpu(*cpu_ptr);
1136 else
1137 tmp = le32_to_cpu(adev->wb.wb[index]);
1138
1139 if (tmp == 0xDEADBEEF)
1140 r = 0;
1141 else
1142 r = -EINVAL;
1143
1144 err1:
1145 amdgpu_ib_free(adev, &ib, NULL);
1146 dma_fence_put(f);
1147 err0:
1148 if (!ring->is_mes_queue)
1149 amdgpu_device_wb_free(adev, index);
1150 return r;
1151 }
1152
1153
1154 /**
1155 * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
1156 *
1157 * @ib: indirect buffer to fill with commands
1158 * @pe: addr of the page entry
1159 * @src: src addr to copy from
1160 * @count: number of page entries to update
1161 *
1162 * Update PTEs by copying them from the GART using sDMA (NAVI10).
1163 */
sdma_v5_0_vm_copy_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t src,unsigned count)1164 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib,
1165 uint64_t pe, uint64_t src,
1166 unsigned count)
1167 {
1168 unsigned bytes = count * 8;
1169
1170 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1171 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1172 ib->ptr[ib->length_dw++] = bytes - 1;
1173 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1174 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1175 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1176 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1177 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1178
1179 }
1180
1181 /**
1182 * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
1183 *
1184 * @ib: indirect buffer to fill with commands
1185 * @pe: addr of the page entry
1186 * @value: dst addr to write into pe
1187 * @count: number of page entries to update
1188 * @incr: increase next addr by incr bytes
1189 *
1190 * Update PTEs by writing them manually using sDMA (NAVI10).
1191 */
sdma_v5_0_vm_write_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t value,unsigned count,uint32_t incr)1192 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1193 uint64_t value, unsigned count,
1194 uint32_t incr)
1195 {
1196 unsigned ndw = count * 2;
1197
1198 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1199 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1200 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1201 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1202 ib->ptr[ib->length_dw++] = ndw - 1;
1203 for (; ndw > 0; ndw -= 2) {
1204 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1205 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1206 value += incr;
1207 }
1208 }
1209
1210 /**
1211 * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1212 *
1213 * @ib: indirect buffer to fill with commands
1214 * @pe: addr of the page entry
1215 * @addr: dst addr to write into pe
1216 * @count: number of page entries to update
1217 * @incr: increase next addr by incr bytes
1218 * @flags: access flags
1219 *
1220 * Update the page tables using sDMA (NAVI10).
1221 */
sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib * ib,uint64_t pe,uint64_t addr,unsigned count,uint32_t incr,uint64_t flags)1222 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1223 uint64_t pe,
1224 uint64_t addr, unsigned count,
1225 uint32_t incr, uint64_t flags)
1226 {
1227 /* for physically contiguous pages (vram) */
1228 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1229 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1230 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1231 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1232 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1233 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1234 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1235 ib->ptr[ib->length_dw++] = incr; /* increment size */
1236 ib->ptr[ib->length_dw++] = 0;
1237 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1238 }
1239
1240 /**
1241 * sdma_v5_0_ring_pad_ib - pad the IB
1242 * @ring: amdgpu_ring structure holding ring information
1243 * @ib: indirect buffer to fill with padding
1244 *
1245 * Pad the IB with NOPs to a boundary multiple of 8.
1246 */
sdma_v5_0_ring_pad_ib(struct amdgpu_ring * ring,struct amdgpu_ib * ib)1247 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1248 {
1249 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1250 u32 pad_count;
1251 int i;
1252
1253 pad_count = (-ib->length_dw) & 0x7;
1254 for (i = 0; i < pad_count; i++)
1255 if (sdma && sdma->burst_nop && (i == 0))
1256 ib->ptr[ib->length_dw++] =
1257 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1258 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1259 else
1260 ib->ptr[ib->length_dw++] =
1261 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1262 }
1263
1264
1265 /**
1266 * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
1267 *
1268 * @ring: amdgpu_ring pointer
1269 *
1270 * Make sure all previous operations are completed (CIK).
1271 */
sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring * ring)1272 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1273 {
1274 uint32_t seq = ring->fence_drv.sync_seq;
1275 uint64_t addr = ring->fence_drv.gpu_addr;
1276
1277 /* wait for idle */
1278 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1279 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1280 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1281 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1282 amdgpu_ring_write(ring, addr & 0xfffffffc);
1283 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1284 amdgpu_ring_write(ring, seq); /* reference */
1285 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1286 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1287 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1288 }
1289
1290
1291 /**
1292 * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1293 *
1294 * @ring: amdgpu_ring pointer
1295 * @vmid: vmid number to use
1296 * @pd_addr: address
1297 *
1298 * Update the page table base and flush the VM TLB
1299 * using sDMA (NAVI10).
1300 */
sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1301 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1302 unsigned vmid, uint64_t pd_addr)
1303 {
1304 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1305 }
1306
sdma_v5_0_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1307 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring,
1308 uint32_t reg, uint32_t val)
1309 {
1310 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1311 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1312 amdgpu_ring_write(ring, reg);
1313 amdgpu_ring_write(ring, val);
1314 }
1315
sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1316 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1317 uint32_t val, uint32_t mask)
1318 {
1319 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1320 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1321 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1322 amdgpu_ring_write(ring, reg << 2);
1323 amdgpu_ring_write(ring, 0);
1324 amdgpu_ring_write(ring, val); /* reference */
1325 amdgpu_ring_write(ring, mask); /* mask */
1326 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1327 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1328 }
1329
sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring * ring,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)1330 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1331 uint32_t reg0, uint32_t reg1,
1332 uint32_t ref, uint32_t mask)
1333 {
1334 amdgpu_ring_emit_wreg(ring, reg0, ref);
1335 /* wait for a cycle to reset vm_inv_eng*_ack */
1336 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1337 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1338 }
1339
sdma_v5_0_early_init(void * handle)1340 static int sdma_v5_0_early_init(void *handle)
1341 {
1342 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1343
1344 sdma_v5_0_set_ring_funcs(adev);
1345 sdma_v5_0_set_buffer_funcs(adev);
1346 sdma_v5_0_set_vm_pte_funcs(adev);
1347 sdma_v5_0_set_irq_funcs(adev);
1348 sdma_v5_0_set_mqd_funcs(adev);
1349
1350 return 0;
1351 }
1352
1353
sdma_v5_0_sw_init(void * handle)1354 static int sdma_v5_0_sw_init(void *handle)
1355 {
1356 struct amdgpu_ring *ring;
1357 int r, i;
1358 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1359
1360 /* SDMA trap event */
1361 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
1362 SDMA0_5_0__SRCID__SDMA_TRAP,
1363 &adev->sdma.trap_irq);
1364 if (r)
1365 return r;
1366
1367 /* SDMA trap event */
1368 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1,
1369 SDMA1_5_0__SRCID__SDMA_TRAP,
1370 &adev->sdma.trap_irq);
1371 if (r)
1372 return r;
1373
1374 r = sdma_v5_0_init_microcode(adev);
1375 if (r) {
1376 DRM_ERROR("Failed to load sdma firmware!\n");
1377 return r;
1378 }
1379
1380 for (i = 0; i < adev->sdma.num_instances; i++) {
1381 ring = &adev->sdma.instance[i].ring;
1382 ring->ring_obj = NULL;
1383 ring->use_doorbell = true;
1384
1385 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1386 ring->use_doorbell?"true":"false");
1387
1388 ring->doorbell_index = (i == 0) ?
1389 (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset
1390 : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset
1391
1392 sprintf(ring->name, "sdma%d", i);
1393 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1394 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
1395 AMDGPU_SDMA_IRQ_INSTANCE1,
1396 AMDGPU_RING_PRIO_DEFAULT, NULL);
1397 if (r)
1398 return r;
1399 }
1400
1401 return r;
1402 }
1403
sdma_v5_0_sw_fini(void * handle)1404 static int sdma_v5_0_sw_fini(void *handle)
1405 {
1406 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1407 int i;
1408
1409 for (i = 0; i < adev->sdma.num_instances; i++)
1410 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1411
1412 amdgpu_sdma_destroy_inst_ctx(adev, false);
1413
1414 return 0;
1415 }
1416
sdma_v5_0_hw_init(void * handle)1417 static int sdma_v5_0_hw_init(void *handle)
1418 {
1419 int r;
1420 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1421
1422 sdma_v5_0_init_golden_registers(adev);
1423
1424 r = sdma_v5_0_start(adev);
1425
1426 return r;
1427 }
1428
sdma_v5_0_hw_fini(void * handle)1429 static int sdma_v5_0_hw_fini(void *handle)
1430 {
1431 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1432
1433 if (amdgpu_sriov_vf(adev)) {
1434 /* disable the scheduler for SDMA */
1435 amdgpu_sdma_unset_buffer_funcs_helper(adev);
1436 return 0;
1437 }
1438
1439 sdma_v5_0_ctx_switch_enable(adev, false);
1440 sdma_v5_0_enable(adev, false);
1441
1442 return 0;
1443 }
1444
sdma_v5_0_suspend(void * handle)1445 static int sdma_v5_0_suspend(void *handle)
1446 {
1447 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1448
1449 return sdma_v5_0_hw_fini(adev);
1450 }
1451
sdma_v5_0_resume(void * handle)1452 static int sdma_v5_0_resume(void *handle)
1453 {
1454 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1455
1456 return sdma_v5_0_hw_init(adev);
1457 }
1458
sdma_v5_0_is_idle(void * handle)1459 static bool sdma_v5_0_is_idle(void *handle)
1460 {
1461 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1462 u32 i;
1463
1464 for (i = 0; i < adev->sdma.num_instances; i++) {
1465 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1466
1467 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1468 return false;
1469 }
1470
1471 return true;
1472 }
1473
sdma_v5_0_wait_for_idle(void * handle)1474 static int sdma_v5_0_wait_for_idle(void *handle)
1475 {
1476 unsigned i;
1477 u32 sdma0, sdma1;
1478 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1479
1480 for (i = 0; i < adev->usec_timeout; i++) {
1481 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1482 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1483
1484 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1485 return 0;
1486 udelay(1);
1487 }
1488 return -ETIMEDOUT;
1489 }
1490
sdma_v5_0_soft_reset(void * handle)1491 static int sdma_v5_0_soft_reset(void *handle)
1492 {
1493 /* todo */
1494
1495 return 0;
1496 }
1497
sdma_v5_0_ring_preempt_ib(struct amdgpu_ring * ring)1498 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
1499 {
1500 int i, r = 0;
1501 struct amdgpu_device *adev = ring->adev;
1502 u32 index = 0;
1503 u64 sdma_gfx_preempt;
1504
1505 amdgpu_sdma_get_index_from_ring(ring, &index);
1506 if (index == 0)
1507 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT;
1508 else
1509 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT;
1510
1511 /* assert preemption condition */
1512 amdgpu_ring_set_preempt_cond_exec(ring, false);
1513
1514 /* emit the trailing fence */
1515 ring->trail_seq += 1;
1516 amdgpu_ring_alloc(ring, 10);
1517 sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1518 ring->trail_seq, 0);
1519 amdgpu_ring_commit(ring);
1520
1521 /* assert IB preemption */
1522 WREG32(sdma_gfx_preempt, 1);
1523
1524 /* poll the trailing fence */
1525 for (i = 0; i < adev->usec_timeout; i++) {
1526 if (ring->trail_seq ==
1527 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1528 break;
1529 udelay(1);
1530 }
1531
1532 if (i >= adev->usec_timeout) {
1533 r = -EINVAL;
1534 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1535 }
1536
1537 /* deassert IB preemption */
1538 WREG32(sdma_gfx_preempt, 0);
1539
1540 /* deassert the preemption condition */
1541 amdgpu_ring_set_preempt_cond_exec(ring, true);
1542 return r;
1543 }
1544
sdma_v5_0_set_trap_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1545 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
1546 struct amdgpu_irq_src *source,
1547 unsigned type,
1548 enum amdgpu_interrupt_state state)
1549 {
1550 u32 sdma_cntl;
1551
1552 if (!amdgpu_sriov_vf(adev)) {
1553 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
1554 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1555 sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
1556
1557 sdma_cntl = RREG32(reg_offset);
1558 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1559 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1560 WREG32(reg_offset, sdma_cntl);
1561 }
1562
1563 return 0;
1564 }
1565
sdma_v5_0_process_trap_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1566 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
1567 struct amdgpu_irq_src *source,
1568 struct amdgpu_iv_entry *entry)
1569 {
1570 uint32_t mes_queue_id = entry->src_data[0];
1571
1572 DRM_DEBUG("IH: SDMA trap\n");
1573
1574 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1575 struct amdgpu_mes_queue *queue;
1576
1577 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1578
1579 spin_lock(&adev->mes.queue_id_lock);
1580 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1581 if (queue) {
1582 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1583 amdgpu_fence_process(queue->ring);
1584 }
1585 spin_unlock(&adev->mes.queue_id_lock);
1586 return 0;
1587 }
1588
1589 switch (entry->client_id) {
1590 case SOC15_IH_CLIENTID_SDMA0:
1591 switch (entry->ring_id) {
1592 case 0:
1593 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1594 break;
1595 case 1:
1596 /* XXX compute */
1597 break;
1598 case 2:
1599 /* XXX compute */
1600 break;
1601 case 3:
1602 /* XXX page queue*/
1603 break;
1604 }
1605 break;
1606 case SOC15_IH_CLIENTID_SDMA1:
1607 switch (entry->ring_id) {
1608 case 0:
1609 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1610 break;
1611 case 1:
1612 /* XXX compute */
1613 break;
1614 case 2:
1615 /* XXX compute */
1616 break;
1617 case 3:
1618 /* XXX page queue*/
1619 break;
1620 }
1621 break;
1622 }
1623 return 0;
1624 }
1625
sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1626 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1627 struct amdgpu_irq_src *source,
1628 struct amdgpu_iv_entry *entry)
1629 {
1630 return 0;
1631 }
1632
sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)1633 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1634 bool enable)
1635 {
1636 uint32_t data, def;
1637 int i;
1638
1639 for (i = 0; i < adev->sdma.num_instances; i++) {
1640 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1641 /* Enable sdma clock gating */
1642 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1643 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1644 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1645 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1646 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1647 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1648 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1649 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1650 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1651 if (def != data)
1652 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1653 } else {
1654 /* Disable sdma clock gating */
1655 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1656 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1657 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1658 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1659 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1660 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1661 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1662 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1663 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1664 if (def != data)
1665 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1666 }
1667 }
1668 }
1669
sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)1670 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1671 bool enable)
1672 {
1673 uint32_t data, def;
1674 int i;
1675
1676 for (i = 0; i < adev->sdma.num_instances; i++) {
1677 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1678 /* Enable sdma mem light sleep */
1679 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1680 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1681 if (def != data)
1682 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1683
1684 } else {
1685 /* Disable sdma mem light sleep */
1686 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1687 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1688 if (def != data)
1689 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1690
1691 }
1692 }
1693 }
1694
sdma_v5_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)1695 static int sdma_v5_0_set_clockgating_state(void *handle,
1696 enum amd_clockgating_state state)
1697 {
1698 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1699
1700 if (amdgpu_sriov_vf(adev))
1701 return 0;
1702
1703 switch (adev->ip_versions[SDMA0_HWIP][0]) {
1704 case IP_VERSION(5, 0, 0):
1705 case IP_VERSION(5, 0, 2):
1706 case IP_VERSION(5, 0, 5):
1707 sdma_v5_0_update_medium_grain_clock_gating(adev,
1708 state == AMD_CG_STATE_GATE);
1709 sdma_v5_0_update_medium_grain_light_sleep(adev,
1710 state == AMD_CG_STATE_GATE);
1711 break;
1712 default:
1713 break;
1714 }
1715
1716 return 0;
1717 }
1718
sdma_v5_0_set_powergating_state(void * handle,enum amd_powergating_state state)1719 static int sdma_v5_0_set_powergating_state(void *handle,
1720 enum amd_powergating_state state)
1721 {
1722 return 0;
1723 }
1724
sdma_v5_0_get_clockgating_state(void * handle,u64 * flags)1725 static void sdma_v5_0_get_clockgating_state(void *handle, u64 *flags)
1726 {
1727 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1728 int data;
1729
1730 if (amdgpu_sriov_vf(adev))
1731 *flags = 0;
1732
1733 /* AMD_CG_SUPPORT_SDMA_MGCG */
1734 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1735 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1736 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1737
1738 /* AMD_CG_SUPPORT_SDMA_LS */
1739 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1740 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1741 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1742 }
1743
1744 const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
1745 .name = "sdma_v5_0",
1746 .early_init = sdma_v5_0_early_init,
1747 .late_init = NULL,
1748 .sw_init = sdma_v5_0_sw_init,
1749 .sw_fini = sdma_v5_0_sw_fini,
1750 .hw_init = sdma_v5_0_hw_init,
1751 .hw_fini = sdma_v5_0_hw_fini,
1752 .suspend = sdma_v5_0_suspend,
1753 .resume = sdma_v5_0_resume,
1754 .is_idle = sdma_v5_0_is_idle,
1755 .wait_for_idle = sdma_v5_0_wait_for_idle,
1756 .soft_reset = sdma_v5_0_soft_reset,
1757 .set_clockgating_state = sdma_v5_0_set_clockgating_state,
1758 .set_powergating_state = sdma_v5_0_set_powergating_state,
1759 .get_clockgating_state = sdma_v5_0_get_clockgating_state,
1760 };
1761
1762 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
1763 .type = AMDGPU_RING_TYPE_SDMA,
1764 .align_mask = 0xf,
1765 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1766 .support_64bit_ptrs = true,
1767 .secure_submission_supported = true,
1768 .vmhub = AMDGPU_GFXHUB_0,
1769 .get_rptr = sdma_v5_0_ring_get_rptr,
1770 .get_wptr = sdma_v5_0_ring_get_wptr,
1771 .set_wptr = sdma_v5_0_ring_set_wptr,
1772 .emit_frame_size =
1773 5 + /* sdma_v5_0_ring_init_cond_exec */
1774 6 + /* sdma_v5_0_ring_emit_hdp_flush */
1775 3 + /* hdp_invalidate */
1776 6 + /* sdma_v5_0_ring_emit_pipeline_sync */
1777 /* sdma_v5_0_ring_emit_vm_flush */
1778 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1779 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
1780 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1781 .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
1782 .emit_ib = sdma_v5_0_ring_emit_ib,
1783 .emit_mem_sync = sdma_v5_0_ring_emit_mem_sync,
1784 .emit_fence = sdma_v5_0_ring_emit_fence,
1785 .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
1786 .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
1787 .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush,
1788 .test_ring = sdma_v5_0_ring_test_ring,
1789 .test_ib = sdma_v5_0_ring_test_ib,
1790 .insert_nop = sdma_v5_0_ring_insert_nop,
1791 .pad_ib = sdma_v5_0_ring_pad_ib,
1792 .emit_wreg = sdma_v5_0_ring_emit_wreg,
1793 .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
1794 .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
1795 .init_cond_exec = sdma_v5_0_ring_init_cond_exec,
1796 .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec,
1797 .preempt_ib = sdma_v5_0_ring_preempt_ib,
1798 };
1799
sdma_v5_0_set_ring_funcs(struct amdgpu_device * adev)1800 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)
1801 {
1802 int i;
1803
1804 for (i = 0; i < adev->sdma.num_instances; i++) {
1805 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;
1806 adev->sdma.instance[i].ring.me = i;
1807 }
1808 }
1809
1810 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = {
1811 .set = sdma_v5_0_set_trap_irq_state,
1812 .process = sdma_v5_0_process_trap_irq,
1813 };
1814
1815 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
1816 .process = sdma_v5_0_process_illegal_inst_irq,
1817 };
1818
sdma_v5_0_set_irq_funcs(struct amdgpu_device * adev)1819 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
1820 {
1821 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1822 adev->sdma.num_instances;
1823 adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
1824 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
1825 }
1826
1827 /**
1828 * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1829 *
1830 * @ib: indirect buffer to copy to
1831 * @src_offset: src GPU address
1832 * @dst_offset: dst GPU address
1833 * @byte_count: number of bytes to xfer
1834 * @tmz: if a secure copy should be used
1835 *
1836 * Copy GPU buffers using the DMA engine (NAVI10).
1837 * Used by the amdgpu ttm implementation to move pages if
1838 * registered as the asic copy callback.
1839 */
sdma_v5_0_emit_copy_buffer(struct amdgpu_ib * ib,uint64_t src_offset,uint64_t dst_offset,uint32_t byte_count,bool tmz)1840 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
1841 uint64_t src_offset,
1842 uint64_t dst_offset,
1843 uint32_t byte_count,
1844 bool tmz)
1845 {
1846 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1847 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1848 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1849 ib->ptr[ib->length_dw++] = byte_count - 1;
1850 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1851 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1852 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1853 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1854 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1855 }
1856
1857 /**
1858 * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1859 *
1860 * @ib: indirect buffer to fill
1861 * @src_data: value to write to buffer
1862 * @dst_offset: dst GPU address
1863 * @byte_count: number of bytes to xfer
1864 *
1865 * Fill GPU buffers using the DMA engine (NAVI10).
1866 */
sdma_v5_0_emit_fill_buffer(struct amdgpu_ib * ib,uint32_t src_data,uint64_t dst_offset,uint32_t byte_count)1867 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib,
1868 uint32_t src_data,
1869 uint64_t dst_offset,
1870 uint32_t byte_count)
1871 {
1872 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1873 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1874 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1875 ib->ptr[ib->length_dw++] = src_data;
1876 ib->ptr[ib->length_dw++] = byte_count - 1;
1877 }
1878
1879 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = {
1880 .copy_max_bytes = 0x400000,
1881 .copy_num_dw = 7,
1882 .emit_copy_buffer = sdma_v5_0_emit_copy_buffer,
1883
1884 .fill_max_bytes = 0x400000,
1885 .fill_num_dw = 5,
1886 .emit_fill_buffer = sdma_v5_0_emit_fill_buffer,
1887 };
1888
sdma_v5_0_set_buffer_funcs(struct amdgpu_device * adev)1889 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
1890 {
1891 if (adev->mman.buffer_funcs == NULL) {
1892 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
1893 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1894 }
1895 }
1896
1897 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
1898 .copy_pte_num_dw = 7,
1899 .copy_pte = sdma_v5_0_vm_copy_pte,
1900 .write_pte = sdma_v5_0_vm_write_pte,
1901 .set_pte_pde = sdma_v5_0_vm_set_pte_pde,
1902 };
1903
sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device * adev)1904 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1905 {
1906 unsigned i;
1907
1908 if (adev->vm_manager.vm_pte_funcs == NULL) {
1909 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
1910 for (i = 0; i < adev->sdma.num_instances; i++) {
1911 adev->vm_manager.vm_pte_scheds[i] =
1912 &adev->sdma.instance[i].ring.sched;
1913 }
1914 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1915 }
1916 }
1917
1918 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = {
1919 .type = AMD_IP_BLOCK_TYPE_SDMA,
1920 .major = 5,
1921 .minor = 0,
1922 .rev = 0,
1923 .funcs = &sdma_v5_0_ip_funcs,
1924 };
1925