1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "umc_v8_10.h"
24 #include "amdgpu_ras.h"
25 #include "amdgpu_umc.h"
26 #include "amdgpu.h"
27 #include "umc/umc_8_10_0_offset.h"
28 #include "umc/umc_8_10_0_sh_mask.h"
29
30 #define UMC_8_NODE_DIST 0x800000
31 #define UMC_8_INST_DIST 0x4000
32
33 struct channelnum_map_colbit {
34 uint32_t channel_num;
35 uint32_t col_bit;
36 };
37
38 const struct channelnum_map_colbit umc_v8_10_channelnum_map_colbit_table[] = {
39 {24, 13},
40 {20, 13},
41 {16, 12},
42 {14, 12},
43 {12, 12},
44 {10, 12},
45 {6, 11},
46 };
47
48 const uint32_t
49 umc_v8_10_channel_idx_tbl_ext0[]
50 [UMC_V8_10_UMC_INSTANCE_NUM]
51 [UMC_V8_10_CHANNEL_INSTANCE_NUM] = {
52 {{1, 5}, {7, 3}},
53 {{14, 15}, {13, 12}},
54 {{10, 11}, {9, 8}},
55 {{6, 2}, {0, 4}}
56 };
57
58 const uint32_t
59 umc_v8_10_channel_idx_tbl[]
60 [UMC_V8_10_UMC_INSTANCE_NUM]
61 [UMC_V8_10_CHANNEL_INSTANCE_NUM] = {
62 {{16, 18}, {17, 19}},
63 {{15, 11}, {3, 7}},
64 {{1, 5}, {13, 9}},
65 {{23, 21}, {22, 20}},
66 {{0, 4}, {12, 8}},
67 {{14, 10}, {2, 6}}
68 };
69
get_umc_v8_10_reg_offset(struct amdgpu_device * adev,uint32_t node_inst,uint32_t umc_inst,uint32_t ch_inst)70 static inline uint32_t get_umc_v8_10_reg_offset(struct amdgpu_device *adev,
71 uint32_t node_inst,
72 uint32_t umc_inst,
73 uint32_t ch_inst)
74 {
75 return adev->umc.channel_offs * ch_inst + UMC_8_INST_DIST * umc_inst +
76 UMC_8_NODE_DIST * node_inst;
77 }
78
umc_v8_10_clear_error_count_per_channel(struct amdgpu_device * adev,uint32_t umc_reg_offset)79 static void umc_v8_10_clear_error_count_per_channel(struct amdgpu_device *adev,
80 uint32_t umc_reg_offset)
81 {
82 uint32_t ecc_err_cnt_addr;
83
84 ecc_err_cnt_addr =
85 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCnt);
86
87 /* clear error count */
88 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4,
89 UMC_V8_10_CE_CNT_INIT);
90 }
91
umc_v8_10_clear_error_count(struct amdgpu_device * adev)92 static void umc_v8_10_clear_error_count(struct amdgpu_device *adev)
93 {
94 uint32_t node_inst = 0;
95 uint32_t umc_inst = 0;
96 uint32_t ch_inst = 0;
97 uint32_t umc_reg_offset = 0;
98
99 LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) {
100 umc_reg_offset = get_umc_v8_10_reg_offset(adev,
101 node_inst,
102 umc_inst,
103 ch_inst);
104
105 umc_v8_10_clear_error_count_per_channel(adev,
106 umc_reg_offset);
107 }
108 }
109
umc_v8_10_query_correctable_error_count(struct amdgpu_device * adev,uint32_t umc_reg_offset,unsigned long * error_count)110 static void umc_v8_10_query_correctable_error_count(struct amdgpu_device *adev,
111 uint32_t umc_reg_offset,
112 unsigned long *error_count)
113 {
114 uint64_t mc_umc_status;
115 uint32_t mc_umc_status_addr;
116
117 /* UMC 8_10 registers */
118 mc_umc_status_addr =
119 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
120
121 /* Rely on MCUMC_STATUS for correctable error counter
122 * MCUMC_STATUS is a 64 bit register
123 */
124 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4);
125 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
126 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
127 *error_count += 1;
128 }
129
umc_v8_10_query_uncorrectable_error_count(struct amdgpu_device * adev,uint32_t umc_reg_offset,unsigned long * error_count)130 static void umc_v8_10_query_uncorrectable_error_count(struct amdgpu_device *adev,
131 uint32_t umc_reg_offset,
132 unsigned long *error_count)
133 {
134 uint64_t mc_umc_status;
135 uint32_t mc_umc_status_addr;
136
137 mc_umc_status_addr = SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
138
139 /* Check the MCUMC_STATUS. */
140 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4);
141 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
142 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
143 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
144 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
145 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
146 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
147 *error_count += 1;
148 }
149
umc_v8_10_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)150 static void umc_v8_10_query_ras_error_count(struct amdgpu_device *adev,
151 void *ras_error_status)
152 {
153 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
154
155 uint32_t node_inst = 0;
156 uint32_t umc_inst = 0;
157 uint32_t ch_inst = 0;
158 uint32_t umc_reg_offset = 0;
159
160 LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) {
161 umc_reg_offset = get_umc_v8_10_reg_offset(adev,
162 node_inst,
163 umc_inst,
164 ch_inst);
165
166 umc_v8_10_query_correctable_error_count(adev,
167 umc_reg_offset,
168 &(err_data->ce_count));
169 umc_v8_10_query_uncorrectable_error_count(adev,
170 umc_reg_offset,
171 &(err_data->ue_count));
172 }
173
174 umc_v8_10_clear_error_count(adev);
175 }
176
umc_v8_10_get_col_bit(uint32_t channel_num)177 static uint32_t umc_v8_10_get_col_bit(uint32_t channel_num)
178 {
179 uint32_t t = 0;
180
181 for (t = 0; t < ARRAY_SIZE(umc_v8_10_channelnum_map_colbit_table); t++)
182 if (channel_num == umc_v8_10_channelnum_map_colbit_table[t].channel_num)
183 return umc_v8_10_channelnum_map_colbit_table[t].col_bit;
184
185 /* Failed to get col_bit. */
186 return U32_MAX;
187 }
188
189 /*
190 * Mapping normal address to soc physical address in swizzle mode.
191 */
umc_v8_10_swizzle_mode_na_to_pa(struct amdgpu_device * adev,uint32_t channel_idx,uint64_t na,uint64_t * soc_pa)192 static int umc_v8_10_swizzle_mode_na_to_pa(struct amdgpu_device *adev,
193 uint32_t channel_idx,
194 uint64_t na, uint64_t *soc_pa)
195 {
196 uint32_t channel_num = UMC_V8_10_TOTAL_CHANNEL_NUM(adev);
197 uint32_t col_bit = umc_v8_10_get_col_bit(channel_num);
198 uint64_t tmp_addr;
199
200 if (col_bit == U32_MAX)
201 return -1;
202
203 tmp_addr = SWIZZLE_MODE_TMP_ADDR(na, channel_num, channel_idx);
204 *soc_pa = SWIZZLE_MODE_ADDR_HI(tmp_addr, col_bit) |
205 SWIZZLE_MODE_ADDR_MID(na, col_bit) |
206 SWIZZLE_MODE_ADDR_LOW(tmp_addr, col_bit) |
207 SWIZZLE_MODE_ADDR_LSB(na);
208
209 return 0;
210 }
211
umc_v8_10_convert_error_address(struct amdgpu_device * adev,struct ras_err_data * err_data,uint64_t err_addr,uint32_t ch_inst,uint32_t umc_inst,uint32_t node_inst,uint64_t mc_umc_status)212 static void umc_v8_10_convert_error_address(struct amdgpu_device *adev,
213 struct ras_err_data *err_data, uint64_t err_addr,
214 uint32_t ch_inst, uint32_t umc_inst,
215 uint32_t node_inst, uint64_t mc_umc_status)
216 {
217 uint64_t na_err_addr_base;
218 uint64_t na_err_addr, retired_page_addr;
219 uint32_t channel_index, addr_lsb, col = 0;
220 int ret = 0;
221
222 channel_index =
223 adev->umc.channel_idx_tbl[node_inst * adev->umc.umc_inst_num *
224 adev->umc.channel_inst_num +
225 umc_inst * adev->umc.channel_inst_num +
226 ch_inst];
227
228 /* the lowest lsb bits should be ignored */
229 addr_lsb = REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrLsb);
230 err_addr &= ~((0x1ULL << addr_lsb) - 1);
231 na_err_addr_base = err_addr & ~(0x3ULL << UMC_V8_10_NA_C5_BIT);
232
233 /* loop for all possibilities of [C6 C5] in normal address. */
234 for (col = 0; col < UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM; col++) {
235 na_err_addr = na_err_addr_base | (col << UMC_V8_10_NA_C5_BIT);
236
237 /* Mapping normal error address to retired soc physical address. */
238 ret = umc_v8_10_swizzle_mode_na_to_pa(adev, channel_index,
239 na_err_addr, &retired_page_addr);
240 if (ret) {
241 dev_err(adev->dev, "Failed to map pa from umc na.\n");
242 break;
243 }
244 dev_info(adev->dev, "Error Address(PA): 0x%llx\n",
245 retired_page_addr);
246 amdgpu_umc_fill_error_record(err_data, na_err_addr,
247 retired_page_addr, channel_index, umc_inst);
248 }
249 }
250
umc_v8_10_query_error_address(struct amdgpu_device * adev,struct ras_err_data * err_data,uint32_t umc_reg_offset,uint32_t node_inst,uint32_t ch_inst,uint32_t umc_inst)251 static void umc_v8_10_query_error_address(struct amdgpu_device *adev,
252 struct ras_err_data *err_data,
253 uint32_t umc_reg_offset,
254 uint32_t node_inst,
255 uint32_t ch_inst,
256 uint32_t umc_inst)
257 {
258 uint64_t mc_umc_status_addr;
259 uint64_t mc_umc_status, err_addr;
260 uint64_t mc_umc_addrt0;
261
262 mc_umc_status_addr =
263 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
264 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4);
265
266 if (mc_umc_status == 0)
267 return;
268
269 if (!err_data->err_addr) {
270 /* clear umc status */
271 WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL);
272 return;
273 }
274
275 /* calculate error address if ue error is detected */
276 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
277 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrV) == 1 &&
278 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {
279
280 mc_umc_addrt0 = SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0);
281 err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4);
282 err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
283
284 umc_v8_10_convert_error_address(adev, err_data, err_addr,
285 ch_inst, umc_inst, node_inst, mc_umc_status);
286 }
287
288 /* clear umc status */
289 WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL);
290 }
291
umc_v8_10_query_ras_error_address(struct amdgpu_device * adev,void * ras_error_status)292 static void umc_v8_10_query_ras_error_address(struct amdgpu_device *adev,
293 void *ras_error_status)
294 {
295 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
296 uint32_t node_inst = 0;
297 uint32_t umc_inst = 0;
298 uint32_t ch_inst = 0;
299 uint32_t umc_reg_offset = 0;
300
301 LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) {
302 umc_reg_offset = get_umc_v8_10_reg_offset(adev,
303 node_inst,
304 umc_inst,
305 ch_inst);
306
307 umc_v8_10_query_error_address(adev,
308 err_data,
309 umc_reg_offset,
310 node_inst,
311 ch_inst,
312 umc_inst);
313 }
314 }
315
umc_v8_10_err_cnt_init_per_channel(struct amdgpu_device * adev,uint32_t umc_reg_offset)316 static void umc_v8_10_err_cnt_init_per_channel(struct amdgpu_device *adev,
317 uint32_t umc_reg_offset)
318 {
319 uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;
320 uint32_t ecc_err_cnt_addr;
321
322 ecc_err_cnt_sel_addr =
323 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCntSel);
324 ecc_err_cnt_addr =
325 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCnt);
326
327 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4);
328
329 /* set ce error interrupt type to APIC based interrupt */
330 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_GeccErrCntSel,
331 GeccErrInt, 0x1);
332 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel);
333 /* set error count to initial value */
334 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V8_10_CE_CNT_INIT);
335 }
336
umc_v8_10_err_cnt_init(struct amdgpu_device * adev)337 static void umc_v8_10_err_cnt_init(struct amdgpu_device *adev)
338 {
339 uint32_t node_inst = 0;
340 uint32_t umc_inst = 0;
341 uint32_t ch_inst = 0;
342 uint32_t umc_reg_offset = 0;
343
344 LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) {
345 umc_reg_offset = get_umc_v8_10_reg_offset(adev,
346 node_inst,
347 umc_inst,
348 ch_inst);
349
350 umc_v8_10_err_cnt_init_per_channel(adev, umc_reg_offset);
351 }
352 }
353
umc_v8_10_query_ras_poison_mode(struct amdgpu_device * adev)354 static bool umc_v8_10_query_ras_poison_mode(struct amdgpu_device *adev)
355 {
356 /*
357 * Force return true, because UMCCH0_0_GeccCtrl
358 * is not accessible from host side
359 */
360 return true;
361 }
362
umc_v8_10_ecc_info_query_correctable_error_count(struct amdgpu_device * adev,uint32_t node_inst,uint32_t umc_inst,uint32_t ch_inst,unsigned long * error_count)363 static void umc_v8_10_ecc_info_query_correctable_error_count(struct amdgpu_device *adev,
364 uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst,
365 unsigned long *error_count)
366 {
367 uint64_t mc_umc_status;
368 uint32_t eccinfo_table_idx;
369 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
370
371 eccinfo_table_idx = node_inst * adev->umc.umc_inst_num *
372 adev->umc.channel_inst_num +
373 umc_inst * adev->umc.channel_inst_num +
374 ch_inst;
375
376 /* check the MCUMC_STATUS */
377 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
378 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
379 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) {
380 *error_count += 1;
381 }
382 }
383
umc_v8_10_ecc_info_query_uncorrectable_error_count(struct amdgpu_device * adev,uint32_t node_inst,uint32_t umc_inst,uint32_t ch_inst,unsigned long * error_count)384 static void umc_v8_10_ecc_info_query_uncorrectable_error_count(struct amdgpu_device *adev,
385 uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst,
386 unsigned long *error_count)
387 {
388 uint64_t mc_umc_status;
389 uint32_t eccinfo_table_idx;
390 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
391
392 eccinfo_table_idx = node_inst * adev->umc.umc_inst_num *
393 adev->umc.channel_inst_num +
394 umc_inst * adev->umc.channel_inst_num +
395 ch_inst;
396
397 /* check the MCUMC_STATUS */
398 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
399 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
400 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
401 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
402 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
403 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
404 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) {
405 *error_count += 1;
406 }
407 }
408
umc_v8_10_ecc_info_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)409 static void umc_v8_10_ecc_info_query_ras_error_count(struct amdgpu_device *adev,
410 void *ras_error_status)
411 {
412 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
413
414 uint32_t node_inst = 0;
415 uint32_t umc_inst = 0;
416 uint32_t ch_inst = 0;
417
418 /* TODO: driver needs to toggle DF Cstate to ensure
419 * safe access of UMC registers. Will add the protection
420 */
421 LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) {
422 umc_v8_10_ecc_info_query_correctable_error_count(adev,
423 node_inst, umc_inst, ch_inst,
424 &(err_data->ce_count));
425 umc_v8_10_ecc_info_query_uncorrectable_error_count(adev,
426 node_inst, umc_inst, ch_inst,
427 &(err_data->ue_count));
428 }
429 }
430
umc_v8_10_ecc_info_query_error_address(struct amdgpu_device * adev,struct ras_err_data * err_data,uint32_t ch_inst,uint32_t umc_inst,uint32_t node_inst)431 static void umc_v8_10_ecc_info_query_error_address(struct amdgpu_device *adev,
432 struct ras_err_data *err_data,
433 uint32_t ch_inst,
434 uint32_t umc_inst,
435 uint32_t node_inst)
436 {
437 uint32_t eccinfo_table_idx;
438 uint64_t mc_umc_status, err_addr;
439
440 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
441
442 eccinfo_table_idx = node_inst * adev->umc.umc_inst_num *
443 adev->umc.channel_inst_num +
444 umc_inst * adev->umc.channel_inst_num +
445 ch_inst;
446
447 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
448
449 if (mc_umc_status == 0)
450 return;
451
452 if (!err_data->err_addr)
453 return;
454
455 /* calculate error address if ue error is detected */
456 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
457 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrV) == 1 &&
458 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1)) {
459
460 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr;
461 err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
462
463 umc_v8_10_convert_error_address(adev, err_data, err_addr,
464 ch_inst, umc_inst, node_inst, mc_umc_status);
465 }
466 }
467
umc_v8_10_ecc_info_query_ras_error_address(struct amdgpu_device * adev,void * ras_error_status)468 static void umc_v8_10_ecc_info_query_ras_error_address(struct amdgpu_device *adev,
469 void *ras_error_status)
470 {
471 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
472
473 uint32_t node_inst = 0;
474 uint32_t umc_inst = 0;
475 uint32_t ch_inst = 0;
476
477 /* TODO: driver needs to toggle DF Cstate to ensure
478 * safe access of UMC resgisters. Will add the protection
479 * when firmware interface is ready
480 */
481 LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) {
482 umc_v8_10_ecc_info_query_error_address(adev,
483 err_data,
484 ch_inst,
485 umc_inst,
486 node_inst);
487 }
488 }
489
490 const struct amdgpu_ras_block_hw_ops umc_v8_10_ras_hw_ops = {
491 .query_ras_error_count = umc_v8_10_query_ras_error_count,
492 .query_ras_error_address = umc_v8_10_query_ras_error_address,
493 };
494
495 struct amdgpu_umc_ras umc_v8_10_ras = {
496 .ras_block = {
497 .hw_ops = &umc_v8_10_ras_hw_ops,
498 },
499 .err_cnt_init = umc_v8_10_err_cnt_init,
500 .query_ras_poison_mode = umc_v8_10_query_ras_poison_mode,
501 .ecc_info_query_ras_error_count = umc_v8_10_ecc_info_query_ras_error_count,
502 .ecc_info_query_ras_error_address = umc_v8_10_ecc_info_query_ras_error_address,
503 };
504