1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dm_services.h"
28 #include "dm_helpers.h"
29 #include "core_types.h"
30 #include "resource.h"
31 #include "dccg.h"
32 #include "dce/dce_hwseq.h"
33 #include "dcn30/dcn30_cm_common.h"
34 #include "reg_helper.h"
35 #include "abm.h"
36 #include "hubp.h"
37 #include "dchubbub.h"
38 #include "timing_generator.h"
39 #include "opp.h"
40 #include "ipp.h"
41 #include "mpc.h"
42 #include "mcif_wb.h"
43 #include "dc_dmub_srv.h"
44 #include "link_hwss.h"
45 #include "dpcd_defs.h"
46 #include "dcn32_hwseq.h"
47 #include "clk_mgr.h"
48 #include "dsc.h"
49 #include "dcn20/dcn20_optc.h"
50 #include "dmub_subvp_state.h"
51 #include "dce/dmub_hw_lock_mgr.h"
52 #include "dcn32_resource.h"
53 #include "link.h"
54 #include "dmub/inc/dmub_subvp_state.h"
55
56 #define DC_LOGGER_INIT(logger)
57
58 #define CTX \
59 hws->ctx
60 #define REG(reg)\
61 hws->regs->reg
62 #define DC_LOGGER \
63 dc->ctx->logger
64
65
66 #undef FN
67 #define FN(reg_name, field_name) \
68 hws->shifts->field_name, hws->masks->field_name
69
dcn32_dsc_pg_control(struct dce_hwseq * hws,unsigned int dsc_inst,bool power_on)70 void dcn32_dsc_pg_control(
71 struct dce_hwseq *hws,
72 unsigned int dsc_inst,
73 bool power_on)
74 {
75 uint32_t power_gate = power_on ? 0 : 1;
76 uint32_t pwr_status = power_on ? 0 : 2;
77 uint32_t org_ip_request_cntl = 0;
78
79 if (hws->ctx->dc->debug.disable_dsc_power_gate)
80 return;
81
82 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
83 if (org_ip_request_cntl == 0)
84 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
85
86 switch (dsc_inst) {
87 case 0: /* DSC0 */
88 REG_UPDATE(DOMAIN16_PG_CONFIG,
89 DOMAIN_POWER_GATE, power_gate);
90
91 REG_WAIT(DOMAIN16_PG_STATUS,
92 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
93 1, 1000);
94 break;
95 case 1: /* DSC1 */
96 REG_UPDATE(DOMAIN17_PG_CONFIG,
97 DOMAIN_POWER_GATE, power_gate);
98
99 REG_WAIT(DOMAIN17_PG_STATUS,
100 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
101 1, 1000);
102 break;
103 case 2: /* DSC2 */
104 REG_UPDATE(DOMAIN18_PG_CONFIG,
105 DOMAIN_POWER_GATE, power_gate);
106
107 REG_WAIT(DOMAIN18_PG_STATUS,
108 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
109 1, 1000);
110 break;
111 case 3: /* DSC3 */
112 REG_UPDATE(DOMAIN19_PG_CONFIG,
113 DOMAIN_POWER_GATE, power_gate);
114
115 REG_WAIT(DOMAIN19_PG_STATUS,
116 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
117 1, 1000);
118 break;
119 default:
120 BREAK_TO_DEBUGGER();
121 break;
122 }
123
124 if (org_ip_request_cntl == 0)
125 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
126 }
127
128
dcn32_enable_power_gating_plane(struct dce_hwseq * hws,bool enable)129 void dcn32_enable_power_gating_plane(
130 struct dce_hwseq *hws,
131 bool enable)
132 {
133 bool force_on = true; /* disable power gating */
134
135 if (enable)
136 force_on = false;
137
138 /* DCHUBP0/1/2/3 */
139 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
140 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
141 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
142 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
143
144 /* DCS0/1/2/3 */
145 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
146 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
147 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
148 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
149 }
150
dcn32_hubp_pg_control(struct dce_hwseq * hws,unsigned int hubp_inst,bool power_on)151 void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
152 {
153 uint32_t power_gate = power_on ? 0 : 1;
154 uint32_t pwr_status = power_on ? 0 : 2;
155
156 if (hws->ctx->dc->debug.disable_hubp_power_gate)
157 return;
158
159 if (REG(DOMAIN0_PG_CONFIG) == 0)
160 return;
161
162 switch (hubp_inst) {
163 case 0:
164 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
165 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
166 break;
167 case 1:
168 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
169 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
170 break;
171 case 2:
172 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
173 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
174 break;
175 case 3:
176 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
177 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
178 break;
179 default:
180 BREAK_TO_DEBUGGER();
181 break;
182 }
183 }
184
dcn32_check_no_memory_request_for_cab(struct dc * dc)185 static bool dcn32_check_no_memory_request_for_cab(struct dc *dc)
186 {
187 int i;
188
189 /* First, check no-memory-request case */
190 for (i = 0; i < dc->current_state->stream_count; i++) {
191 if ((dc->current_state->stream_status[i].plane_count) &&
192 (dc->current_state->streams[i]->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED))
193 /* Fail eligibility on a visible stream */
194 break;
195 }
196
197 if (i == dc->current_state->stream_count)
198 return true;
199
200 return false;
201 }
202
203
204 /* This function loops through every surface that needs to be cached in CAB for SS,
205 * and calculates the total number of ways required to store all surfaces (primary,
206 * meta, cursor).
207 */
dcn32_calculate_cab_allocation(struct dc * dc,struct dc_state * ctx)208 static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)
209 {
210 int i;
211 uint8_t num_ways = 0;
212 uint32_t mall_ss_size_bytes = 0;
213
214 mall_ss_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_size_bytes;
215 // TODO add additional logic for PSR active stream exclusion optimization
216 // mall_ss_psr_active_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes;
217
218 // Include cursor size for CAB allocation
219 for (i = 0; i < dc->res_pool->pipe_count; i++) {
220 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i];
221
222 if (!pipe->stream || !pipe->plane_state)
223 continue;
224
225 mall_ss_size_bytes += dcn32_helper_calculate_mall_bytes_for_cursor(dc, pipe, false);
226 }
227
228 // Convert number of cache lines required to number of ways
229 if (dc->debug.force_mall_ss_num_ways > 0) {
230 num_ways = dc->debug.force_mall_ss_num_ways;
231 } else {
232 num_ways = dcn32_helper_mall_bytes_to_ways(dc, mall_ss_size_bytes);
233 }
234
235 return num_ways;
236 }
237
dcn32_apply_idle_power_optimizations(struct dc * dc,bool enable)238 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable)
239 {
240 union dmub_rb_cmd cmd;
241 uint8_t ways, i;
242 int j;
243 bool mall_ss_unsupported = false;
244 struct dc_plane_state *plane = NULL;
245
246 if (!dc->ctx->dmub_srv)
247 return false;
248
249 for (i = 0; i < dc->current_state->stream_count; i++) {
250 /* MALL SS messaging is not supported with PSR at this time */
251 if (dc->current_state->streams[i] != NULL &&
252 dc->current_state->streams[i]->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED)
253 return false;
254 }
255
256 if (enable) {
257 if (dc->current_state) {
258
259 /* 1. Check no memory request case for CAB.
260 * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message
261 */
262 if (dcn32_check_no_memory_request_for_cab(dc)) {
263 /* Enable no-memory-requests case */
264 memset(&cmd, 0, sizeof(cmd));
265 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
266 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ;
267 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
268
269 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
270 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
271
272 return true;
273 }
274
275 /* 2. Check if all surfaces can fit in CAB.
276 * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message
277 * and configure HUBP's to fetch from MALL
278 */
279 ways = dcn32_calculate_cab_allocation(dc, dc->current_state);
280
281 /* MALL not supported with Stereo3D or TMZ surface. If any plane is using stereo,
282 * or TMZ surface, don't try to enter MALL.
283 */
284 for (i = 0; i < dc->current_state->stream_count; i++) {
285 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) {
286 plane = dc->current_state->stream_status[i].plane_states[j];
287
288 if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO ||
289 plane->address.tmz_surface) {
290 mall_ss_unsupported = true;
291 break;
292 }
293 }
294 if (mall_ss_unsupported)
295 break;
296 }
297 if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) {
298 memset(&cmd, 0, sizeof(cmd));
299 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
300 cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB;
301 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
302 cmd.cab.cab_alloc_ways = ways;
303
304 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
305 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
306
307 return true;
308 }
309
310 }
311 return false;
312 }
313
314 /* Disable CAB */
315 memset(&cmd, 0, sizeof(cmd));
316 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
317 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION;
318 cmd.cab.header.payload_bytes =
319 sizeof(cmd.cab) - sizeof(cmd.cab.header);
320
321 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
322 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
323 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
324
325 return true;
326 }
327
328 /* Send DMCUB message with SubVP pipe info
329 * - For each pipe in context, populate payload with required SubVP information
330 * if the pipe is using SubVP for MCLK switch
331 * - This function must be called while the DMUB HW lock is acquired by driver
332 */
dcn32_commit_subvp_config(struct dc * dc,struct dc_state * context)333 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context)
334 {
335 int i;
336 bool enable_subvp = false;
337
338 if (!dc->ctx || !dc->ctx->dmub_srv)
339 return;
340
341 for (i = 0; i < dc->res_pool->pipe_count; i++) {
342 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
343
344 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.paired_stream &&
345 pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN) {
346 // There is at least 1 SubVP pipe, so enable SubVP
347 enable_subvp = true;
348 break;
349 }
350 }
351 dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp);
352 }
353
354 /* Sub-Viewport DMUB lock needs to be acquired by driver whenever SubVP is active and:
355 * 1. Any full update for any SubVP main pipe
356 * 2. Any immediate flip for any SubVP pipe
357 * 3. Any flip for DRR pipe
358 * 4. If SubVP was previously in use (i.e. in old context)
359 */
dcn32_subvp_pipe_control_lock(struct dc * dc,struct dc_state * context,bool lock,bool should_lock_all_pipes,struct pipe_ctx * top_pipe_to_program,bool subvp_prev_use)360 void dcn32_subvp_pipe_control_lock(struct dc *dc,
361 struct dc_state *context,
362 bool lock,
363 bool should_lock_all_pipes,
364 struct pipe_ctx *top_pipe_to_program,
365 bool subvp_prev_use)
366 {
367 unsigned int i = 0;
368 bool subvp_immediate_flip = false;
369 bool subvp_in_use = false;
370 struct pipe_ctx *pipe;
371
372 for (i = 0; i < dc->res_pool->pipe_count; i++) {
373 pipe = &context->res_ctx.pipe_ctx[i];
374
375 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
376 subvp_in_use = true;
377 break;
378 }
379 }
380
381 if (top_pipe_to_program && top_pipe_to_program->stream && top_pipe_to_program->plane_state) {
382 if (top_pipe_to_program->stream->mall_stream_config.type == SUBVP_MAIN &&
383 top_pipe_to_program->plane_state->flip_immediate)
384 subvp_immediate_flip = true;
385 }
386
387 // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared.
388 if ((subvp_in_use && (should_lock_all_pipes || subvp_immediate_flip)) || (!subvp_in_use && subvp_prev_use)) {
389 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };
390
391 if (!lock) {
392 for (i = 0; i < dc->res_pool->pipe_count; i++) {
393 pipe = &context->res_ctx.pipe_ctx[i];
394 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN &&
395 should_lock_all_pipes)
396 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK);
397 }
398 }
399
400 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;
401 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;
402 hw_lock_cmd.bits.lock = lock;
403 hw_lock_cmd.bits.should_release = !lock;
404 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);
405 }
406 }
407
408
dcn32_set_mpc_shaper_3dlut(struct pipe_ctx * pipe_ctx,const struct dc_stream_state * stream)409 static bool dcn32_set_mpc_shaper_3dlut(
410 struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream)
411 {
412 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
413 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
414 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
415 bool result = false;
416
417 const struct pwl_params *shaper_lut = NULL;
418 //get the shaper lut params
419 if (stream->func_shaper) {
420 if (stream->func_shaper->type == TF_TYPE_HWPWL)
421 shaper_lut = &stream->func_shaper->pwl;
422 else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {
423 cm_helper_translate_curve_to_hw_format(
424 stream->func_shaper,
425 &dpp_base->shaper_params, true);
426 shaper_lut = &dpp_base->shaper_params;
427 }
428 }
429
430 if (stream->lut3d_func &&
431 stream->lut3d_func->state.bits.initialized == 1) {
432
433 result = mpc->funcs->program_3dlut(mpc,
434 &stream->lut3d_func->lut_3d,
435 mpcc_id);
436
437 result = mpc->funcs->program_shaper(mpc,
438 shaper_lut,
439 mpcc_id);
440 }
441
442 return result;
443 }
444
dcn32_set_mcm_luts(struct pipe_ctx * pipe_ctx,const struct dc_plane_state * plane_state)445 bool dcn32_set_mcm_luts(
446 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
447 {
448 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
449 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
450 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
451 bool result = true;
452 struct pwl_params *lut_params = NULL;
453
454 // 1D LUT
455 if (plane_state->blend_tf) {
456 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
457 lut_params = &plane_state->blend_tf->pwl;
458 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
459 cm_helper_translate_curve_to_hw_format(
460 plane_state->blend_tf,
461 &dpp_base->regamma_params, false);
462 lut_params = &dpp_base->regamma_params;
463 }
464 }
465 result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id);
466
467 // Shaper
468 if (plane_state->in_shaper_func) {
469 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
470 lut_params = &plane_state->in_shaper_func->pwl;
471 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
472 // TODO: dpp_base replace
473 ASSERT(false);
474 cm_helper_translate_curve_to_hw_format(
475 plane_state->in_shaper_func,
476 &dpp_base->shaper_params, true);
477 lut_params = &dpp_base->shaper_params;
478 }
479 }
480
481 result = mpc->funcs->program_shaper(mpc, lut_params, mpcc_id);
482
483 // 3D
484 if (plane_state->lut3d_func && plane_state->lut3d_func->state.bits.initialized == 1)
485 result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func->lut_3d, mpcc_id);
486 else
487 result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id);
488
489 return result;
490 }
491
dcn32_set_input_transfer_func(struct dc * dc,struct pipe_ctx * pipe_ctx,const struct dc_plane_state * plane_state)492 bool dcn32_set_input_transfer_func(struct dc *dc,
493 struct pipe_ctx *pipe_ctx,
494 const struct dc_plane_state *plane_state)
495 {
496 struct dce_hwseq *hws = dc->hwseq;
497 struct mpc *mpc = dc->res_pool->mpc;
498 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
499
500 enum dc_transfer_func_predefined tf;
501 bool result = true;
502 struct pwl_params *params = NULL;
503
504 if (mpc == NULL || plane_state == NULL)
505 return false;
506
507 tf = TRANSFER_FUNCTION_UNITY;
508
509 if (plane_state->in_transfer_func &&
510 plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED)
511 tf = plane_state->in_transfer_func->tf;
512
513 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf);
514
515 if (plane_state->in_transfer_func) {
516 if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL)
517 params = &plane_state->in_transfer_func->pwl;
518 else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS &&
519 cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func,
520 &dpp_base->degamma_params, false))
521 params = &dpp_base->degamma_params;
522 }
523
524 dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);
525
526 if (pipe_ctx->stream_res.opp &&
527 pipe_ctx->stream_res.opp->ctx &&
528 hws->funcs.set_mcm_luts)
529 result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state);
530
531 return result;
532 }
533
dcn32_set_output_transfer_func(struct dc * dc,struct pipe_ctx * pipe_ctx,const struct dc_stream_state * stream)534 bool dcn32_set_output_transfer_func(struct dc *dc,
535 struct pipe_ctx *pipe_ctx,
536 const struct dc_stream_state *stream)
537 {
538 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
539 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
540 struct pwl_params *params = NULL;
541 bool ret = false;
542
543 /* program OGAM or 3DLUT only for the top pipe*/
544 if (pipe_ctx->top_pipe == NULL) {
545 /*program shaper and 3dlut in MPC*/
546 ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream);
547 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
548 if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
549 params = &stream->out_transfer_func->pwl;
550 else if (pipe_ctx->stream->out_transfer_func->type ==
551 TF_TYPE_DISTRIBUTED_POINTS &&
552 cm3_helper_translate_curve_to_hw_format(
553 stream->out_transfer_func,
554 &mpc->blender_params, false))
555 params = &mpc->blender_params;
556 /* there are no ROM LUTs in OUTGAM */
557 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
558 BREAK_TO_DEBUGGER();
559 }
560 }
561
562 mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
563 return ret;
564 }
565
566 /* Program P-State force value according to if pipe is using SubVP or not:
567 * 1. Reset P-State force on all pipes first
568 * 2. For each main pipe, force P-State disallow (P-State allow moderated by DMUB)
569 */
dcn32_subvp_update_force_pstate(struct dc * dc,struct dc_state * context)570 void dcn32_subvp_update_force_pstate(struct dc *dc, struct dc_state *context)
571 {
572 int i;
573 int num_subvp = 0;
574 /* Unforce p-state for each pipe
575 */
576 for (i = 0; i < dc->res_pool->pipe_count; i++) {
577 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
578 struct hubp *hubp = pipe->plane_res.hubp;
579
580 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)
581 hubp->funcs->hubp_update_force_pstate_disallow(hubp, false);
582 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN)
583 num_subvp++;
584 }
585
586 if (num_subvp == 0)
587 return;
588
589 /* Loop through each pipe -- for each subvp main pipe force p-state allow equal to false.
590 */
591 for (i = 0; i < dc->res_pool->pipe_count; i++) {
592 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
593
594 if (pipe->stream && pipe->plane_state && (pipe->stream->mall_stream_config.type == SUBVP_MAIN)) {
595 struct hubp *hubp = pipe->plane_res.hubp;
596
597 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)
598 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true);
599 }
600 }
601 }
602
603 /* Update MALL_SEL register based on if pipe / plane
604 * is a phantom pipe, main pipe, and if using MALL
605 * for SS.
606 */
dcn32_update_mall_sel(struct dc * dc,struct dc_state * context)607 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context)
608 {
609 int i;
610 unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context);
611 bool cache_cursor = false;
612
613 for (i = 0; i < dc->res_pool->pipe_count; i++) {
614 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
615 struct hubp *hubp = pipe->plane_res.hubp;
616
617 if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) {
618 int cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height;
619
620 switch (hubp->curs_attr.color_format) {
621 case CURSOR_MODE_MONO:
622 cursor_size /= 2;
623 break;
624 case CURSOR_MODE_COLOR_1BIT_AND:
625 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
626 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
627 cursor_size *= 4;
628 break;
629
630 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
631 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
632 default:
633 cursor_size *= 8;
634 break;
635 }
636
637 if (cursor_size > 16384)
638 cache_cursor = true;
639
640 if (pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
641 hubp->funcs->hubp_update_mall_sel(hubp, 1, false);
642 } else {
643 // MALL not supported with Stereo3D
644 hubp->funcs->hubp_update_mall_sel(hubp,
645 num_ways <= dc->caps.cache_num_ways &&
646 pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&
647 pipe->plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO &&
648 !pipe->plane_state->address.tmz_surface ? 2 : 0,
649 cache_cursor);
650 }
651 }
652 }
653 }
654
655 /* Program the sub-viewport pipe configuration after the main / phantom pipes
656 * have been programmed in hardware.
657 * 1. Update force P-State for all the main pipes (disallow P-state)
658 * 2. Update MALL_SEL register
659 * 3. Program FORCE_ONE_ROW_FOR_FRAME for main subvp pipes
660 */
dcn32_program_mall_pipe_config(struct dc * dc,struct dc_state * context)661 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context)
662 {
663 int i;
664 struct dce_hwseq *hws = dc->hwseq;
665
666 // Don't force p-state disallow -- can't block dummy p-state
667
668 // Update MALL_SEL register for each pipe
669 if (hws && hws->funcs.update_mall_sel)
670 hws->funcs.update_mall_sel(dc, context);
671
672 //update subvp force pstate
673 if (hws && hws->funcs.subvp_update_force_pstate)
674 dc->hwseq->funcs.subvp_update_force_pstate(dc, context);
675
676 // Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes
677 for (i = 0; i < dc->res_pool->pipe_count; i++) {
678 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
679 struct hubp *hubp = pipe->plane_res.hubp;
680
681 if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) {
682 /* TODO - remove setting CURSOR_REQ_MODE to 0 for legacy cases
683 * - need to investigate single pipe MPO + SubVP case to
684 * see if CURSOR_REQ_MODE will be back to 1 for SubVP
685 * when it should be 0 for MPO
686 */
687 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
688 hubp->funcs->hubp_prepare_subvp_buffering(hubp, true);
689 }
690 }
691 }
692 }
693
dcn32_initialize_min_clocks(struct dc * dc)694 static void dcn32_initialize_min_clocks(struct dc *dc)
695 {
696 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk;
697
698 clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ;
699 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000;
700 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000;
701 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000;
702 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000;
703 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000;
704 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
705 clocks->fclk_p_state_change_support = true;
706 clocks->p_state_change_support = true;
707
708 dc->clk_mgr->funcs->update_clocks(
709 dc->clk_mgr,
710 dc->current_state,
711 true);
712 }
713
dcn32_init_hw(struct dc * dc)714 void dcn32_init_hw(struct dc *dc)
715 {
716 struct abm **abms = dc->res_pool->multiple_abms;
717 struct dce_hwseq *hws = dc->hwseq;
718 struct dc_bios *dcb = dc->ctx->dc_bios;
719 struct resource_pool *res_pool = dc->res_pool;
720 int i;
721 int edp_num;
722 uint32_t backlight = MAX_BACKLIGHT_LEVEL;
723
724 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
725 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
726
727 // Initialize the dccg
728 if (res_pool->dccg->funcs->dccg_init)
729 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
730
731 if (!dcb->funcs->is_accelerated_mode(dcb)) {
732 hws->funcs.bios_golden_init(dc);
733 hws->funcs.disable_vga(dc->hwseq);
734 }
735
736 // Set default OPTC memory power states
737 if (dc->debug.enable_mem_low_power.bits.optc) {
738 // Shutdown when unassigned and light sleep in VBLANK
739 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
740 }
741
742 if (dc->debug.enable_mem_low_power.bits.vga) {
743 // Power down VGA memory
744 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
745 }
746
747 if (dc->ctx->dc_bios->fw_info_valid) {
748 res_pool->ref_clocks.xtalin_clock_inKhz =
749 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
750
751 if (res_pool->dccg && res_pool->hubbub) {
752 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
753 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
754 &res_pool->ref_clocks.dccg_ref_clock_inKhz);
755
756 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
757 res_pool->ref_clocks.dccg_ref_clock_inKhz,
758 &res_pool->ref_clocks.dchub_ref_clock_inKhz);
759 } else {
760 // Not all ASICs have DCCG sw component
761 res_pool->ref_clocks.dccg_ref_clock_inKhz =
762 res_pool->ref_clocks.xtalin_clock_inKhz;
763 res_pool->ref_clocks.dchub_ref_clock_inKhz =
764 res_pool->ref_clocks.xtalin_clock_inKhz;
765 }
766 } else
767 ASSERT_CRITICAL(false);
768
769 for (i = 0; i < dc->link_count; i++) {
770 /* Power up AND update implementation according to the
771 * required signal (which may be different from the
772 * default signal on connector).
773 */
774 struct dc_link *link = dc->links[i];
775
776 link->link_enc->funcs->hw_init(link->link_enc);
777
778 /* Check for enabled DIG to identify enabled display */
779 if (link->link_enc->funcs->is_dig_enabled &&
780 link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
781 link->link_status.link_active = true;
782 link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
783 if (link->link_enc->funcs->fec_is_active &&
784 link->link_enc->funcs->fec_is_active(link->link_enc))
785 link->fec_state = dc_link_fec_enabled;
786 }
787 }
788
789 /* Power gate DSCs */
790 for (i = 0; i < res_pool->res_cap->num_dsc; i++)
791 if (hws->funcs.dsc_pg_control != NULL)
792 hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
793
794 /* we want to turn off all dp displays before doing detection */
795 link_blank_all_dp_displays(dc);
796
797 /* If taking control over from VBIOS, we may want to optimize our first
798 * mode set, so we need to skip powering down pipes until we know which
799 * pipes we want to use.
800 * Otherwise, if taking control is not possible, we need to power
801 * everything down.
802 */
803 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
804 hws->funcs.init_pipes(dc, dc->current_state);
805 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
806 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
807 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
808
809 dcn32_initialize_min_clocks(dc);
810
811 /* On HW init, allow idle optimizations after pipes have been turned off.
812 *
813 * In certain D3 cases (i.e. BOCO / BOMACO) it's possible that hardware state
814 * is reset (i.e. not in idle at the time hw init is called), but software state
815 * still has idle_optimizations = true, so we must disable idle optimizations first
816 * (i.e. set false), then re-enable (set true).
817 */
818 dc_allow_idle_optimizations(dc, false);
819 dc_allow_idle_optimizations(dc, true);
820 }
821
822 /* In headless boot cases, DIG may be turned
823 * on which causes HW/SW discrepancies.
824 * To avoid this, power down hardware on boot
825 * if DIG is turned on and seamless boot not enabled
826 */
827 if (!dc->config.seamless_boot_edp_requested) {
828 struct dc_link *edp_links[MAX_NUM_EDP];
829 struct dc_link *edp_link;
830
831 get_edp_links(dc, edp_links, &edp_num);
832 if (edp_num) {
833 for (i = 0; i < edp_num; i++) {
834 edp_link = edp_links[i];
835 if (edp_link->link_enc->funcs->is_dig_enabled &&
836 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
837 dc->hwss.edp_backlight_control &&
838 dc->hwss.power_down &&
839 dc->hwss.edp_power_control) {
840 dc->hwss.edp_backlight_control(edp_link, false);
841 dc->hwss.power_down(dc);
842 dc->hwss.edp_power_control(edp_link, false);
843 }
844 }
845 } else {
846 for (i = 0; i < dc->link_count; i++) {
847 struct dc_link *link = dc->links[i];
848
849 if (link->link_enc->funcs->is_dig_enabled &&
850 link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
851 dc->hwss.power_down) {
852 dc->hwss.power_down(dc);
853 break;
854 }
855
856 }
857 }
858 }
859
860 for (i = 0; i < res_pool->audio_count; i++) {
861 struct audio *audio = res_pool->audios[i];
862
863 audio->funcs->hw_init(audio);
864 }
865
866 for (i = 0; i < dc->link_count; i++) {
867 struct dc_link *link = dc->links[i];
868
869 if (link->panel_cntl)
870 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
871 }
872
873 for (i = 0; i < dc->res_pool->pipe_count; i++) {
874 if (abms[i] != NULL && abms[i]->funcs != NULL)
875 abms[i]->funcs->abm_init(abms[i], backlight);
876 }
877
878 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
879 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
880
881 if (!dc->debug.disable_clock_gate) {
882 /* enable all DCN clock gating */
883 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
884
885 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
886
887 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
888 }
889 if (hws->funcs.enable_power_gating_plane)
890 hws->funcs.enable_power_gating_plane(dc->hwseq, true);
891
892 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
893 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
894
895 if (dc->clk_mgr->funcs->notify_wm_ranges)
896 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
897
898 if (dc->clk_mgr->funcs->set_hard_max_memclk)
899 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
900
901 if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
902 dc->res_pool->hubbub->funcs->force_pstate_change_control(
903 dc->res_pool->hubbub, false, false);
904
905 if (dc->res_pool->hubbub->funcs->init_crb)
906 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
907
908 if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0)
909 dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc);
910
911 // Get DMCUB capabilities
912 if (dc->ctx->dmub_srv) {
913 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub);
914 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
915 }
916 }
917
calc_mpc_flow_ctrl_cnt(const struct dc_stream_state * stream,int opp_cnt)918 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
919 int opp_cnt)
920 {
921 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing);
922 int flow_ctrl_cnt;
923
924 if (opp_cnt >= 2)
925 hblank_halved = true;
926
927 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable -
928 stream->timing.h_border_left -
929 stream->timing.h_border_right;
930
931 if (hblank_halved)
932 flow_ctrl_cnt /= 2;
933
934 /* ODM combine 4:1 case */
935 if (opp_cnt == 4)
936 flow_ctrl_cnt /= 2;
937
938 return flow_ctrl_cnt;
939 }
940
update_dsc_on_stream(struct pipe_ctx * pipe_ctx,bool enable)941 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
942 {
943 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
944 struct dc_stream_state *stream = pipe_ctx->stream;
945 struct pipe_ctx *odm_pipe;
946 int opp_cnt = 1;
947
948 ASSERT(dsc);
949 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
950 opp_cnt++;
951
952 if (enable) {
953 struct dsc_config dsc_cfg;
954 struct dsc_optc_config dsc_optc_cfg;
955 enum optc_dsc_mode optc_dsc_mode;
956
957 /* Enable DSC hw block */
958 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
959 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
960 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
961 dsc_cfg.color_depth = stream->timing.display_color_depth;
962 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
963 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
964 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
965 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
966
967 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
968 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
969 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
970 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;
971
972 ASSERT(odm_dsc);
973 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);
974 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
975 }
976 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;
977 dsc_cfg.pic_width *= opp_cnt;
978
979 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
980
981 /* Enable DSC in OPTC */
982 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
983 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,
984 optc_dsc_mode,
985 dsc_optc_cfg.bytes_per_pixel,
986 dsc_optc_cfg.slice_width);
987 } else {
988 /* disable DSC in OPTC */
989 pipe_ctx->stream_res.tg->funcs->set_dsc_config(
990 pipe_ctx->stream_res.tg,
991 OPTC_DSC_DISABLED, 0, 0);
992
993 /* disable DSC block */
994 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
995 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
996 ASSERT(odm_pipe->stream_res.dsc);
997 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);
998 }
999 }
1000 }
1001
1002 /*
1003 * Given any pipe_ctx, return the total ODM combine factor, and optionally return
1004 * the OPPids which are used
1005 * */
get_odm_config(struct pipe_ctx * pipe_ctx,unsigned int * opp_instances)1006 static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)
1007 {
1008 unsigned int opp_count = 1;
1009 struct pipe_ctx *odm_pipe;
1010
1011 /* First get to the top pipe */
1012 for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe)
1013 ;
1014
1015 /* First pipe is always used */
1016 if (opp_instances)
1017 opp_instances[0] = odm_pipe->stream_res.opp->inst;
1018
1019 /* Find and count odm pipes, if any */
1020 for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1021 if (opp_instances)
1022 opp_instances[opp_count] = odm_pipe->stream_res.opp->inst;
1023 opp_count++;
1024 }
1025
1026 return opp_count;
1027 }
1028
dcn32_update_odm(struct dc * dc,struct dc_state * context,struct pipe_ctx * pipe_ctx)1029 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
1030 {
1031 struct pipe_ctx *odm_pipe;
1032 int opp_cnt = 0;
1033 int opp_inst[MAX_PIPES] = {0};
1034 bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing));
1035 struct mpc_dwb_flow_control flow_control;
1036 struct mpc *mpc = dc->res_pool->mpc;
1037 int i;
1038
1039 opp_cnt = get_odm_config(pipe_ctx, opp_inst);
1040
1041 if (opp_cnt > 1)
1042 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
1043 pipe_ctx->stream_res.tg,
1044 opp_inst, opp_cnt,
1045 &pipe_ctx->stream->timing);
1046 else
1047 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
1048 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1049
1050 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1;
1051 flow_control.flow_ctrl_mode = 0;
1052 flow_control.flow_ctrl_cnt0 = 0x80;
1053 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt);
1054 if (mpc->funcs->set_out_rate_control) {
1055 for (i = 0; i < opp_cnt; ++i) {
1056 mpc->funcs->set_out_rate_control(
1057 mpc, opp_inst[i],
1058 true,
1059 rate_control_2x_pclk,
1060 &flow_control);
1061 }
1062 }
1063
1064 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1065 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
1066 odm_pipe->stream_res.opp,
1067 true);
1068 }
1069
1070 if (pipe_ctx->stream_res.dsc) {
1071 struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
1072
1073 update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);
1074
1075 /* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */
1076 if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&
1077 current_pipe_ctx->next_odm_pipe->stream_res.dsc) {
1078 struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc;
1079 /* disconnect DSC block from stream */
1080 dsc->funcs->dsc_disconnect(dsc);
1081 }
1082 }
1083 }
1084
dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx * pipe_ctx,unsigned int * k1_div,unsigned int * k2_div)1085 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
1086 {
1087 struct dc_stream_state *stream = pipe_ctx->stream;
1088 unsigned int odm_combine_factor = 0;
1089 bool two_pix_per_container = false;
1090
1091 // For phantom pipes, use the same programming as the main pipes
1092 if (pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) {
1093 stream = pipe_ctx->stream->mall_stream_config.paired_stream;
1094 }
1095 two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing);
1096 odm_combine_factor = get_odm_config(pipe_ctx, NULL);
1097
1098 if (link_is_dp_128b_132b_signal(pipe_ctx)) {
1099 *k1_div = PIXEL_RATE_DIV_BY_1;
1100 *k2_div = PIXEL_RATE_DIV_BY_1;
1101 } else if (dc_is_hdmi_tmds_signal(stream->signal) || dc_is_dvi_signal(stream->signal)) {
1102 *k1_div = PIXEL_RATE_DIV_BY_1;
1103 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1104 *k2_div = PIXEL_RATE_DIV_BY_2;
1105 else
1106 *k2_div = PIXEL_RATE_DIV_BY_4;
1107 } else if (dc_is_dp_signal(stream->signal) || dc_is_virtual_signal(stream->signal)) {
1108 if (two_pix_per_container) {
1109 *k1_div = PIXEL_RATE_DIV_BY_1;
1110 *k2_div = PIXEL_RATE_DIV_BY_2;
1111 } else {
1112 *k1_div = PIXEL_RATE_DIV_BY_1;
1113 *k2_div = PIXEL_RATE_DIV_BY_4;
1114 if ((odm_combine_factor == 2) || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))
1115 *k2_div = PIXEL_RATE_DIV_BY_2;
1116 }
1117 }
1118
1119 if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))
1120 ASSERT(false);
1121
1122 return odm_combine_factor;
1123 }
1124
dcn32_set_pixels_per_cycle(struct pipe_ctx * pipe_ctx)1125 void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
1126 {
1127 uint32_t pix_per_cycle = 1;
1128 uint32_t odm_combine_factor = 1;
1129
1130 if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc)
1131 return;
1132
1133 odm_combine_factor = get_odm_config(pipe_ctx, NULL);
1134 if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1
1135 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))
1136 pix_per_cycle = 2;
1137
1138 if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode)
1139 pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc,
1140 pix_per_cycle);
1141 }
1142
dcn32_unblank_stream(struct pipe_ctx * pipe_ctx,struct dc_link_settings * link_settings)1143 void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,
1144 struct dc_link_settings *link_settings)
1145 {
1146 struct encoder_unblank_param params = {0};
1147 struct dc_stream_state *stream = pipe_ctx->stream;
1148 struct dc_link *link = stream->link;
1149 struct dce_hwseq *hws = link->dc->hwseq;
1150 struct pipe_ctx *odm_pipe;
1151 uint32_t pix_per_cycle = 1;
1152
1153 params.opp_cnt = 1;
1154 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1155 params.opp_cnt++;
1156
1157 /* only 3 items below are used by unblank */
1158 params.timing = pipe_ctx->stream->timing;
1159
1160 params.link_settings.link_rate = link_settings->link_rate;
1161
1162 if (link_is_dp_128b_132b_signal(pipe_ctx)) {
1163 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
1164 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(
1165 pipe_ctx->stream_res.hpo_dp_stream_enc,
1166 pipe_ctx->stream_res.tg->inst);
1167 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1168 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1
1169 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) {
1170 params.timing.pix_clk_100hz /= 2;
1171 pix_per_cycle = 2;
1172 }
1173 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
1174 pipe_ctx->stream_res.stream_enc, pix_per_cycle > 1);
1175 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms);
1176 }
1177
1178 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP)
1179 hws->funcs.edp_backlight_control(link, true);
1180 }
1181
dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx * pipe_ctx)1182 bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx)
1183 {
1184 struct dc *dc = pipe_ctx->stream->ctx->dc;
1185
1186 if (!is_h_timing_divisible_by_2(pipe_ctx->stream))
1187 return false;
1188
1189 if (dc_is_dp_signal(pipe_ctx->stream->signal) && !link_is_dp_128b_132b_signal(pipe_ctx) &&
1190 dc->debug.enable_dp_dig_pixel_rate_div_policy)
1191 return true;
1192 return false;
1193 }
1194
apply_symclk_on_tx_off_wa(struct dc_link * link)1195 static void apply_symclk_on_tx_off_wa(struct dc_link *link)
1196 {
1197 /* There are use cases where SYMCLK is referenced by OTG. For instance
1198 * for TMDS signal, OTG relies SYMCLK even if TX video output is off.
1199 * However current link interface will power off PHY when disabling link
1200 * output. This will turn off SYMCLK generated by PHY. The workaround is
1201 * to identify such case where SYMCLK is still in use by OTG when we
1202 * power off PHY. When this is detected, we will temporarily power PHY
1203 * back on and move PHY's SYMCLK state to SYMCLK_ON_TX_OFF by calling
1204 * program_pix_clk interface. When OTG is disabled, we will then power
1205 * off PHY by calling disable link output again.
1206 *
1207 * In future dcn generations, we plan to rework transmitter control
1208 * interface so that we could have an option to set SYMCLK ON TX OFF
1209 * state in one step without this workaround
1210 */
1211
1212 struct dc *dc = link->ctx->dc;
1213 struct pipe_ctx *pipe_ctx = NULL;
1214 uint8_t i;
1215
1216 if (link->phy_state.symclk_ref_cnts.otg > 0) {
1217 for (i = 0; i < MAX_PIPES; i++) {
1218 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1219 if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) {
1220 pipe_ctx->clock_source->funcs->program_pix_clk(
1221 pipe_ctx->clock_source,
1222 &pipe_ctx->stream_res.pix_clk_params,
1223 link_dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),
1224 &pipe_ctx->pll_settings);
1225 link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
1226 break;
1227 }
1228 }
1229 }
1230 }
1231
dcn32_disable_link_output(struct dc_link * link,const struct link_resource * link_res,enum signal_type signal)1232 void dcn32_disable_link_output(struct dc_link *link,
1233 const struct link_resource *link_res,
1234 enum signal_type signal)
1235 {
1236 struct dc *dc = link->ctx->dc;
1237 const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
1238 struct dmcu *dmcu = dc->res_pool->dmcu;
1239
1240 if (signal == SIGNAL_TYPE_EDP &&
1241 link->dc->hwss.edp_backlight_control)
1242 link->dc->hwss.edp_backlight_control(link, false);
1243 else if (dmcu != NULL && dmcu->funcs->lock_phy)
1244 dmcu->funcs->lock_phy(dmcu);
1245
1246 link_hwss->disable_link_output(link, link_res, signal);
1247 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
1248
1249 if (signal == SIGNAL_TYPE_EDP &&
1250 link->dc->hwss.edp_backlight_control)
1251 link->dc->hwss.edp_power_control(link, false);
1252 else if (dmcu != NULL && dmcu->funcs->lock_phy)
1253 dmcu->funcs->unlock_phy(dmcu);
1254
1255 link_dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
1256
1257 apply_symclk_on_tx_off_wa(link);
1258 }
1259
1260 /* For SubVP the main pipe can have a viewport position change
1261 * without a full update. In this case we must also update the
1262 * viewport positions for the phantom pipe accordingly.
1263 */
dcn32_update_phantom_vp_position(struct dc * dc,struct dc_state * context,struct pipe_ctx * phantom_pipe)1264 void dcn32_update_phantom_vp_position(struct dc *dc,
1265 struct dc_state *context,
1266 struct pipe_ctx *phantom_pipe)
1267 {
1268 uint32_t i;
1269 struct dc_plane_state *phantom_plane = phantom_pipe->plane_state;
1270
1271 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1272 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1273
1274 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN &&
1275 pipe->stream->mall_stream_config.paired_stream == phantom_pipe->stream) {
1276 if (pipe->plane_state && pipe->plane_state->update_flags.bits.position_change) {
1277
1278 phantom_plane->src_rect.x = pipe->plane_state->src_rect.x;
1279 phantom_plane->src_rect.y = pipe->plane_state->src_rect.y;
1280 phantom_plane->clip_rect.x = pipe->plane_state->clip_rect.x;
1281 phantom_plane->dst_rect.x = pipe->plane_state->dst_rect.x;
1282 phantom_plane->dst_rect.y = pipe->plane_state->dst_rect.y;
1283
1284 phantom_pipe->plane_state->update_flags.bits.position_change = 1;
1285 resource_build_scaling_params(phantom_pipe);
1286 return;
1287 }
1288 }
1289 }
1290 }
1291
1292 /* Treat the phantom pipe as if it needs to be fully enabled.
1293 * If the pipe was previously in use but not phantom, it would
1294 * have been disabled earlier in the sequence so we need to run
1295 * the full enable sequence.
1296 */
dcn32_apply_update_flags_for_phantom(struct pipe_ctx * phantom_pipe)1297 void dcn32_apply_update_flags_for_phantom(struct pipe_ctx *phantom_pipe)
1298 {
1299 phantom_pipe->update_flags.raw = 0;
1300 if (phantom_pipe->stream && phantom_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
1301 if (phantom_pipe->stream && phantom_pipe->plane_state) {
1302 phantom_pipe->update_flags.bits.enable = 1;
1303 phantom_pipe->update_flags.bits.mpcc = 1;
1304 phantom_pipe->update_flags.bits.dppclk = 1;
1305 phantom_pipe->update_flags.bits.hubp_interdependent = 1;
1306 phantom_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1307 phantom_pipe->update_flags.bits.gamut_remap = 1;
1308 phantom_pipe->update_flags.bits.scaler = 1;
1309 phantom_pipe->update_flags.bits.viewport = 1;
1310 phantom_pipe->update_flags.bits.det_size = 1;
1311 if (!phantom_pipe->top_pipe && !phantom_pipe->prev_odm_pipe) {
1312 phantom_pipe->update_flags.bits.odm = 1;
1313 phantom_pipe->update_flags.bits.global_sync = 1;
1314 }
1315 }
1316 }
1317 }
1318
dcn32_dsc_pg_status(struct dce_hwseq * hws,unsigned int dsc_inst)1319 bool dcn32_dsc_pg_status(
1320 struct dce_hwseq *hws,
1321 unsigned int dsc_inst)
1322 {
1323 uint32_t pwr_status = 0;
1324
1325 switch (dsc_inst) {
1326 case 0: /* DSC0 */
1327 REG_GET(DOMAIN16_PG_STATUS,
1328 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1329 break;
1330 case 1: /* DSC1 */
1331
1332 REG_GET(DOMAIN17_PG_STATUS,
1333 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1334 break;
1335 case 2: /* DSC2 */
1336 REG_GET(DOMAIN18_PG_STATUS,
1337 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1338 break;
1339 case 3: /* DSC3 */
1340 REG_GET(DOMAIN19_PG_STATUS,
1341 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1342 break;
1343 default:
1344 BREAK_TO_DEBUGGER();
1345 break;
1346 }
1347
1348 return pwr_status == 0;
1349 }
1350
dcn32_update_dsc_pg(struct dc * dc,struct dc_state * context,bool safe_to_disable)1351 void dcn32_update_dsc_pg(struct dc *dc,
1352 struct dc_state *context,
1353 bool safe_to_disable)
1354 {
1355 struct dce_hwseq *hws = dc->hwseq;
1356 int i;
1357
1358 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {
1359 struct display_stream_compressor *dsc = dc->res_pool->dscs[i];
1360 bool is_dsc_ungated = hws->funcs.dsc_pg_status(hws, dsc->inst);
1361
1362 if (context->res_ctx.is_dsc_acquired[i]) {
1363 if (!is_dsc_ungated) {
1364 hws->funcs.dsc_pg_control(hws, dsc->inst, true);
1365 }
1366 } else if (safe_to_disable) {
1367 if (is_dsc_ungated) {
1368 hws->funcs.dsc_pg_control(hws, dsc->inst, false);
1369 }
1370 }
1371 }
1372 }
1373
dcn32_enable_phantom_streams(struct dc * dc,struct dc_state * context)1374 void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context)
1375 {
1376 unsigned int i;
1377
1378 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1379 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1380 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1381
1382 /* If an active, non-phantom pipe is being transitioned into a phantom
1383 * pipe, wait for the double buffer update to complete first before we do
1384 * ANY phantom pipe programming.
1385 */
1386 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM &&
1387 old_pipe->stream && old_pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) {
1388 old_pipe->stream_res.tg->funcs->wait_for_state(
1389 old_pipe->stream_res.tg,
1390 CRTC_STATE_VBLANK);
1391 old_pipe->stream_res.tg->funcs->wait_for_state(
1392 old_pipe->stream_res.tg,
1393 CRTC_STATE_VACTIVE);
1394 }
1395 }
1396 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1397 struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
1398
1399 if (new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
1400 // If old context or new context has phantom pipes, apply
1401 // the phantom timings now. We can't change the phantom
1402 // pipe configuration safely without driver acquiring
1403 // the DMCUB lock first.
1404 dc->hwss.apply_ctx_to_hw(dc, context);
1405 break;
1406 }
1407 }
1408 }
1409