1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/module.h>
33 #include <linux/oom.h>
34 #include <linux/pci.h>
35 #include <linux/pm.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/slab.h>
38 #include <linux/string_helpers.h>
39 #include <linux/vga_switcheroo.h>
40 #include <linux/vt.h>
41
42 #include <drm/drm_aperture.h>
43 #include <drm/drm_atomic_helper.h>
44 #include <drm/drm_ioctl.h>
45 #include <drm/drm_managed.h>
46 #include <drm/drm_probe_helper.h>
47
48 #include "display/intel_acpi.h"
49 #include "display/intel_bw.h"
50 #include "display/intel_cdclk.h"
51 #include "display/intel_display_types.h"
52 #include "display/intel_dmc.h"
53 #include "display/intel_dp.h"
54 #include "display/intel_dpt.h"
55 #include "display/intel_fbdev.h"
56 #include "display/intel_hotplug.h"
57 #include "display/intel_overlay.h"
58 #include "display/intel_pch_refclk.h"
59 #include "display/intel_pipe_crc.h"
60 #include "display/intel_pps.h"
61 #include "display/intel_sprite.h"
62 #include "display/intel_vga.h"
63 #include "display/skl_watermark.h"
64
65 #include "gem/i915_gem_context.h"
66 #include "gem/i915_gem_create.h"
67 #include "gem/i915_gem_dmabuf.h"
68 #include "gem/i915_gem_ioctls.h"
69 #include "gem/i915_gem_mman.h"
70 #include "gem/i915_gem_pm.h"
71 #include "gt/intel_gt.h"
72 #include "gt/intel_gt_pm.h"
73 #include "gt/intel_rc6.h"
74
75 #include "pxp/intel_pxp.h"
76 #include "pxp/intel_pxp_debugfs.h"
77 #include "pxp/intel_pxp_pm.h"
78
79 #include "soc/intel_dram.h"
80 #include "soc/intel_gmch.h"
81
82 #include "i915_file_private.h"
83 #include "i915_debugfs.h"
84 #include "i915_driver.h"
85 #include "i915_drm_client.h"
86 #include "i915_drv.h"
87 #include "i915_getparam.h"
88 #include "i915_hwmon.h"
89 #include "i915_ioc32.h"
90 #include "i915_ioctl.h"
91 #include "i915_irq.h"
92 #include "i915_memcpy.h"
93 #include "i915_perf.h"
94 #include "i915_query.h"
95 #include "i915_suspend.h"
96 #include "i915_switcheroo.h"
97 #include "i915_sysfs.h"
98 #include "i915_utils.h"
99 #include "i915_vgpu.h"
100 #include "intel_gvt.h"
101 #include "intel_memory_region.h"
102 #include "intel_pci_config.h"
103 #include "intel_pcode.h"
104 #include "intel_pm.h"
105 #include "intel_region_ttm.h"
106 #include "vlv_suspend.h"
107
108 static const struct drm_driver i915_drm_driver;
109
i915_workqueues_init(struct drm_i915_private * dev_priv)110 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
111 {
112 /*
113 * The i915 workqueue is primarily used for batched retirement of
114 * requests (and thus managing bo) once the task has been completed
115 * by the GPU. i915_retire_requests() is called directly when we
116 * need high-priority retirement, such as waiting for an explicit
117 * bo.
118 *
119 * It is also used for periodic low-priority events, such as
120 * idle-timers and recording error state.
121 *
122 * All tasks on the workqueue are expected to acquire the dev mutex
123 * so there is no point in running more than one instance of the
124 * workqueue at any time. Use an ordered one.
125 */
126 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
127 if (dev_priv->wq == NULL)
128 goto out_err;
129
130 dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
131 if (dev_priv->display.hotplug.dp_wq == NULL)
132 goto out_free_wq;
133
134 return 0;
135
136 out_free_wq:
137 destroy_workqueue(dev_priv->wq);
138 out_err:
139 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
140
141 return -ENOMEM;
142 }
143
i915_workqueues_cleanup(struct drm_i915_private * dev_priv)144 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
145 {
146 destroy_workqueue(dev_priv->display.hotplug.dp_wq);
147 destroy_workqueue(dev_priv->wq);
148 }
149
150 /*
151 * We don't keep the workarounds for pre-production hardware, so we expect our
152 * driver to fail on these machines in one way or another. A little warning on
153 * dmesg may help both the user and the bug triagers.
154 *
155 * Our policy for removing pre-production workarounds is to keep the
156 * current gen workarounds as a guide to the bring-up of the next gen
157 * (workarounds have a habit of persisting!). Anything older than that
158 * should be removed along with the complications they introduce.
159 */
intel_detect_preproduction_hw(struct drm_i915_private * dev_priv)160 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
161 {
162 bool pre = false;
163
164 pre |= IS_HSW_EARLY_SDV(dev_priv);
165 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
166 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
167 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
168 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
169 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
170
171 if (pre) {
172 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
173 "It may not be fully functional.\n");
174 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
175 }
176 }
177
sanitize_gpu(struct drm_i915_private * i915)178 static void sanitize_gpu(struct drm_i915_private *i915)
179 {
180 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) {
181 struct intel_gt *gt;
182 unsigned int i;
183
184 for_each_gt(gt, i915, i)
185 __intel_gt_reset(gt, ALL_ENGINES);
186 }
187 }
188
189 /**
190 * i915_driver_early_probe - setup state not requiring device access
191 * @dev_priv: device private
192 *
193 * Initialize everything that is a "SW-only" state, that is state not
194 * requiring accessing the device or exposing the driver via kernel internal
195 * or userspace interfaces. Example steps belonging here: lock initialization,
196 * system memory allocation, setting up device specific attributes and
197 * function hooks not requiring accessing the device.
198 */
i915_driver_early_probe(struct drm_i915_private * dev_priv)199 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
200 {
201 int ret = 0;
202
203 if (i915_inject_probe_failure(dev_priv))
204 return -ENODEV;
205
206 intel_device_info_runtime_init_early(dev_priv);
207
208 intel_step_init(dev_priv);
209
210 intel_uncore_mmio_debug_init_early(dev_priv);
211
212 spin_lock_init(&dev_priv->irq_lock);
213 spin_lock_init(&dev_priv->gpu_error.lock);
214 mutex_init(&dev_priv->display.backlight.lock);
215
216 mutex_init(&dev_priv->sb_lock);
217 cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
218
219 mutex_init(&dev_priv->display.audio.mutex);
220 mutex_init(&dev_priv->display.wm.wm_mutex);
221 mutex_init(&dev_priv->display.pps.mutex);
222 mutex_init(&dev_priv->display.hdcp.comp_mutex);
223 spin_lock_init(&dev_priv->display.dkl.phy_lock);
224
225 i915_memcpy_init_early(dev_priv);
226 intel_runtime_pm_init_early(&dev_priv->runtime_pm);
227
228 ret = i915_workqueues_init(dev_priv);
229 if (ret < 0)
230 return ret;
231
232 ret = vlv_suspend_init(dev_priv);
233 if (ret < 0)
234 goto err_workqueues;
235
236 ret = intel_region_ttm_device_init(dev_priv);
237 if (ret)
238 goto err_ttm;
239
240 ret = intel_root_gt_init_early(dev_priv);
241 if (ret < 0)
242 goto err_rootgt;
243
244 i915_drm_clients_init(&dev_priv->clients, dev_priv);
245
246 i915_gem_init_early(dev_priv);
247
248 /* This must be called before any calls to HAS_PCH_* */
249 intel_detect_pch(dev_priv);
250
251 intel_pm_setup(dev_priv);
252 ret = intel_power_domains_init(dev_priv);
253 if (ret < 0)
254 goto err_gem;
255 intel_irq_init(dev_priv);
256 intel_init_display_hooks(dev_priv);
257 intel_init_clock_gating_hooks(dev_priv);
258
259 intel_detect_preproduction_hw(dev_priv);
260
261 return 0;
262
263 err_gem:
264 i915_gem_cleanup_early(dev_priv);
265 intel_gt_driver_late_release_all(dev_priv);
266 i915_drm_clients_fini(&dev_priv->clients);
267 err_rootgt:
268 intel_region_ttm_device_fini(dev_priv);
269 err_ttm:
270 vlv_suspend_cleanup(dev_priv);
271 err_workqueues:
272 i915_workqueues_cleanup(dev_priv);
273 return ret;
274 }
275
276 /**
277 * i915_driver_late_release - cleanup the setup done in
278 * i915_driver_early_probe()
279 * @dev_priv: device private
280 */
i915_driver_late_release(struct drm_i915_private * dev_priv)281 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
282 {
283 intel_irq_fini(dev_priv);
284 intel_power_domains_cleanup(dev_priv);
285 i915_gem_cleanup_early(dev_priv);
286 intel_gt_driver_late_release_all(dev_priv);
287 i915_drm_clients_fini(&dev_priv->clients);
288 intel_region_ttm_device_fini(dev_priv);
289 vlv_suspend_cleanup(dev_priv);
290 i915_workqueues_cleanup(dev_priv);
291
292 cpu_latency_qos_remove_request(&dev_priv->sb_qos);
293 mutex_destroy(&dev_priv->sb_lock);
294
295 i915_params_free(&dev_priv->params);
296 }
297
298 /**
299 * i915_driver_mmio_probe - setup device MMIO
300 * @dev_priv: device private
301 *
302 * Setup minimal device state necessary for MMIO accesses later in the
303 * initialization sequence. The setup here should avoid any other device-wide
304 * side effects or exposing the driver via kernel internal or user space
305 * interfaces.
306 */
i915_driver_mmio_probe(struct drm_i915_private * dev_priv)307 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
308 {
309 struct intel_gt *gt;
310 int ret, i;
311
312 if (i915_inject_probe_failure(dev_priv))
313 return -ENODEV;
314
315 ret = intel_gmch_bridge_setup(dev_priv);
316 if (ret < 0)
317 return ret;
318
319 for_each_gt(gt, dev_priv, i) {
320 ret = intel_uncore_init_mmio(gt->uncore);
321 if (ret)
322 return ret;
323
324 ret = drmm_add_action_or_reset(&dev_priv->drm,
325 intel_uncore_fini_mmio,
326 gt->uncore);
327 if (ret)
328 return ret;
329 }
330
331 /* Try to make sure MCHBAR is enabled before poking at it */
332 intel_gmch_bar_setup(dev_priv);
333 intel_device_info_runtime_init(dev_priv);
334
335 for_each_gt(gt, dev_priv, i) {
336 ret = intel_gt_init_mmio(gt);
337 if (ret)
338 goto err_uncore;
339 }
340
341 /* As early as possible, scrub existing GPU state before clobbering */
342 sanitize_gpu(dev_priv);
343
344 return 0;
345
346 err_uncore:
347 intel_gmch_bar_teardown(dev_priv);
348
349 return ret;
350 }
351
352 /**
353 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
354 * @dev_priv: device private
355 */
i915_driver_mmio_release(struct drm_i915_private * dev_priv)356 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
357 {
358 intel_gmch_bar_teardown(dev_priv);
359 }
360
361 /**
362 * i915_set_dma_info - set all relevant PCI dma info as configured for the
363 * platform
364 * @i915: valid i915 instance
365 *
366 * Set the dma max segment size, device and coherent masks. The dma mask set
367 * needs to occur before i915_ggtt_probe_hw.
368 *
369 * A couple of platforms have special needs. Address them as well.
370 *
371 */
i915_set_dma_info(struct drm_i915_private * i915)372 static int i915_set_dma_info(struct drm_i915_private *i915)
373 {
374 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
375 int ret;
376
377 GEM_BUG_ON(!mask_size);
378
379 /*
380 * We don't have a max segment size, so set it to the max so sg's
381 * debugging layer doesn't complain
382 */
383 dma_set_max_seg_size(i915->drm.dev, UINT_MAX);
384
385 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
386 if (ret)
387 goto mask_err;
388
389 /* overlay on gen2 is broken and can't address above 1G */
390 if (GRAPHICS_VER(i915) == 2)
391 mask_size = 30;
392
393 /*
394 * 965GM sometimes incorrectly writes to hardware status page (HWS)
395 * using 32bit addressing, overwriting memory if HWS is located
396 * above 4GB.
397 *
398 * The documentation also mentions an issue with undefined
399 * behaviour if any general state is accessed within a page above 4GB,
400 * which also needs to be handled carefully.
401 */
402 if (IS_I965G(i915) || IS_I965GM(i915))
403 mask_size = 32;
404
405 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
406 if (ret)
407 goto mask_err;
408
409 return 0;
410
411 mask_err:
412 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
413 return ret;
414 }
415
i915_pcode_init(struct drm_i915_private * i915)416 static int i915_pcode_init(struct drm_i915_private *i915)
417 {
418 struct intel_gt *gt;
419 int id, ret;
420
421 for_each_gt(gt, i915, id) {
422 ret = intel_pcode_init(gt->uncore);
423 if (ret) {
424 drm_err(>->i915->drm, "gt%d: intel_pcode_init failed %d\n", id, ret);
425 return ret;
426 }
427 }
428
429 return 0;
430 }
431
432 /**
433 * i915_driver_hw_probe - setup state requiring device access
434 * @dev_priv: device private
435 *
436 * Setup state that requires accessing the device, but doesn't require
437 * exposing the driver via kernel internal or userspace interfaces.
438 */
i915_driver_hw_probe(struct drm_i915_private * dev_priv)439 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
440 {
441 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
442 struct pci_dev *root_pdev;
443 int ret;
444
445 if (i915_inject_probe_failure(dev_priv))
446 return -ENODEV;
447
448 if (HAS_PPGTT(dev_priv)) {
449 if (intel_vgpu_active(dev_priv) &&
450 !intel_vgpu_has_full_ppgtt(dev_priv)) {
451 i915_report_error(dev_priv,
452 "incompatible vGPU found, support for isolated ppGTT required\n");
453 return -ENXIO;
454 }
455 }
456
457 if (HAS_EXECLISTS(dev_priv)) {
458 /*
459 * Older GVT emulation depends upon intercepting CSB mmio,
460 * which we no longer use, preferring to use the HWSP cache
461 * instead.
462 */
463 if (intel_vgpu_active(dev_priv) &&
464 !intel_vgpu_has_hwsp_emulation(dev_priv)) {
465 i915_report_error(dev_priv,
466 "old vGPU host found, support for HWSP emulation required\n");
467 return -ENXIO;
468 }
469 }
470
471 /* needs to be done before ggtt probe */
472 intel_dram_edram_detect(dev_priv);
473
474 ret = i915_set_dma_info(dev_priv);
475 if (ret)
476 return ret;
477
478 i915_perf_init(dev_priv);
479
480 ret = i915_ggtt_probe_hw(dev_priv);
481 if (ret)
482 goto err_perf;
483
484 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver);
485 if (ret)
486 goto err_ggtt;
487
488 ret = i915_ggtt_init_hw(dev_priv);
489 if (ret)
490 goto err_ggtt;
491
492 ret = intel_memory_regions_hw_probe(dev_priv);
493 if (ret)
494 goto err_ggtt;
495
496 ret = intel_gt_tiles_init(dev_priv);
497 if (ret)
498 goto err_mem_regions;
499
500 ret = i915_ggtt_enable_hw(dev_priv);
501 if (ret) {
502 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
503 goto err_mem_regions;
504 }
505
506 pci_set_master(pdev);
507
508 /* On the 945G/GM, the chipset reports the MSI capability on the
509 * integrated graphics even though the support isn't actually there
510 * according to the published specs. It doesn't appear to function
511 * correctly in testing on 945G.
512 * This may be a side effect of MSI having been made available for PEG
513 * and the registers being closely associated.
514 *
515 * According to chipset errata, on the 965GM, MSI interrupts may
516 * be lost or delayed, and was defeatured. MSI interrupts seem to
517 * get lost on g4x as well, and interrupt delivery seems to stay
518 * properly dead afterwards. So we'll just disable them for all
519 * pre-gen5 chipsets.
520 *
521 * dp aux and gmbus irq on gen4 seems to be able to generate legacy
522 * interrupts even when in MSI mode. This results in spurious
523 * interrupt warnings if the legacy irq no. is shared with another
524 * device. The kernel then disables that interrupt source and so
525 * prevents the other device from working properly.
526 */
527 if (GRAPHICS_VER(dev_priv) >= 5) {
528 if (pci_enable_msi(pdev) < 0)
529 drm_dbg(&dev_priv->drm, "can't enable MSI");
530 }
531
532 ret = intel_gvt_init(dev_priv);
533 if (ret)
534 goto err_msi;
535
536 intel_opregion_setup(dev_priv);
537
538 ret = i915_pcode_init(dev_priv);
539 if (ret)
540 goto err_msi;
541
542 /*
543 * Fill the dram structure to get the system dram info. This will be
544 * used for memory latency calculation.
545 */
546 intel_dram_detect(dev_priv);
547
548 intel_bw_init_hw(dev_priv);
549
550 /*
551 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
552 * This should be totally removed when we handle the pci states properly
553 * on runtime PM and on s2idle cases.
554 */
555 root_pdev = pcie_find_root_port(pdev);
556 if (root_pdev)
557 pci_d3cold_disable(root_pdev);
558
559 return 0;
560
561 err_msi:
562 if (pdev->msi_enabled)
563 pci_disable_msi(pdev);
564 err_mem_regions:
565 intel_memory_regions_driver_release(dev_priv);
566 err_ggtt:
567 i915_ggtt_driver_release(dev_priv);
568 i915_gem_drain_freed_objects(dev_priv);
569 i915_ggtt_driver_late_release(dev_priv);
570 err_perf:
571 i915_perf_fini(dev_priv);
572 return ret;
573 }
574
575 /**
576 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
577 * @dev_priv: device private
578 */
i915_driver_hw_remove(struct drm_i915_private * dev_priv)579 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
580 {
581 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
582 struct pci_dev *root_pdev;
583
584 i915_perf_fini(dev_priv);
585
586 if (pdev->msi_enabled)
587 pci_disable_msi(pdev);
588
589 root_pdev = pcie_find_root_port(pdev);
590 if (root_pdev)
591 pci_d3cold_enable(root_pdev);
592 }
593
594 /**
595 * i915_driver_register - register the driver with the rest of the system
596 * @dev_priv: device private
597 *
598 * Perform any steps necessary to make the driver available via kernel
599 * internal or userspace interfaces.
600 */
i915_driver_register(struct drm_i915_private * dev_priv)601 static void i915_driver_register(struct drm_i915_private *dev_priv)
602 {
603 struct intel_gt *gt;
604 unsigned int i;
605
606 i915_gem_driver_register(dev_priv);
607 i915_pmu_register(dev_priv);
608
609 intel_vgpu_register(dev_priv);
610
611 /* Reveal our presence to userspace */
612 if (drm_dev_register(&dev_priv->drm, 0)) {
613 drm_err(&dev_priv->drm,
614 "Failed to register driver for userspace access!\n");
615 return;
616 }
617
618 i915_debugfs_register(dev_priv);
619 i915_setup_sysfs(dev_priv);
620
621 /* Depends on sysfs having been initialized */
622 i915_perf_register(dev_priv);
623
624 for_each_gt(gt, dev_priv, i)
625 intel_gt_driver_register(gt);
626
627 intel_pxp_debugfs_register(dev_priv->pxp);
628
629 i915_hwmon_register(dev_priv);
630
631 intel_display_driver_register(dev_priv);
632
633 intel_power_domains_enable(dev_priv);
634 intel_runtime_pm_enable(&dev_priv->runtime_pm);
635
636 intel_register_dsm_handler();
637
638 if (i915_switcheroo_register(dev_priv))
639 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
640 }
641
642 /**
643 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
644 * @dev_priv: device private
645 */
i915_driver_unregister(struct drm_i915_private * dev_priv)646 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
647 {
648 struct intel_gt *gt;
649 unsigned int i;
650
651 i915_switcheroo_unregister(dev_priv);
652
653 intel_unregister_dsm_handler();
654
655 intel_runtime_pm_disable(&dev_priv->runtime_pm);
656 intel_power_domains_disable(dev_priv);
657
658 intel_display_driver_unregister(dev_priv);
659
660 intel_pxp_fini(dev_priv);
661
662 for_each_gt(gt, dev_priv, i)
663 intel_gt_driver_unregister(gt);
664
665 i915_hwmon_unregister(dev_priv);
666
667 i915_perf_unregister(dev_priv);
668 i915_pmu_unregister(dev_priv);
669
670 i915_teardown_sysfs(dev_priv);
671 drm_dev_unplug(&dev_priv->drm);
672
673 i915_gem_driver_unregister(dev_priv);
674 }
675
676 void
i915_print_iommu_status(struct drm_i915_private * i915,struct drm_printer * p)677 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p)
678 {
679 drm_printf(p, "iommu: %s\n",
680 str_enabled_disabled(i915_vtd_active(i915)));
681 }
682
i915_welcome_messages(struct drm_i915_private * dev_priv)683 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
684 {
685 if (drm_debug_enabled(DRM_UT_DRIVER)) {
686 struct drm_printer p = drm_debug_printer("i915 device info:");
687 struct intel_gt *gt;
688 unsigned int i;
689
690 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
691 INTEL_DEVID(dev_priv),
692 INTEL_REVID(dev_priv),
693 intel_platform_name(INTEL_INFO(dev_priv)->platform),
694 intel_subplatform(RUNTIME_INFO(dev_priv),
695 INTEL_INFO(dev_priv)->platform),
696 GRAPHICS_VER(dev_priv));
697
698 intel_device_info_print(INTEL_INFO(dev_priv),
699 RUNTIME_INFO(dev_priv), &p);
700 i915_print_iommu_status(dev_priv, &p);
701 for_each_gt(gt, dev_priv, i)
702 intel_gt_info_print(>->info, &p);
703 }
704
705 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
706 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
707 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
708 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
709 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
710 drm_info(&dev_priv->drm,
711 "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
712 }
713
714 static struct drm_i915_private *
i915_driver_create(struct pci_dev * pdev,const struct pci_device_id * ent)715 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
716 {
717 const struct intel_device_info *match_info =
718 (struct intel_device_info *)ent->driver_data;
719 struct intel_device_info *device_info;
720 struct intel_runtime_info *runtime;
721 struct drm_i915_private *i915;
722
723 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver,
724 struct drm_i915_private, drm);
725 if (IS_ERR(i915))
726 return i915;
727
728 pci_set_drvdata(pdev, i915);
729
730 /* Device parameters start as a copy of module parameters. */
731 i915_params_copy(&i915->params, &i915_modparams);
732
733 /* Setup the write-once "constant" device info */
734 device_info = mkwrite_device_info(i915);
735 memcpy(device_info, match_info, sizeof(*device_info));
736
737 /* Initialize initial runtime info from static const data and pdev. */
738 runtime = RUNTIME_INFO(i915);
739 memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
740 runtime->device_id = pdev->device;
741
742 return i915;
743 }
744
745 /**
746 * i915_driver_probe - setup chip and create an initial config
747 * @pdev: PCI device
748 * @ent: matching PCI ID entry
749 *
750 * The driver probe routine has to do several things:
751 * - drive output discovery via intel_modeset_init()
752 * - initialize the memory manager
753 * - allocate initial config memory
754 * - setup the DRM framebuffer with the allocated memory
755 */
i915_driver_probe(struct pci_dev * pdev,const struct pci_device_id * ent)756 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
757 {
758 struct drm_i915_private *i915;
759 int ret;
760
761 i915 = i915_driver_create(pdev, ent);
762 if (IS_ERR(i915))
763 return PTR_ERR(i915);
764
765 ret = pci_enable_device(pdev);
766 if (ret)
767 goto out_fini;
768
769 ret = i915_driver_early_probe(i915);
770 if (ret < 0)
771 goto out_pci_disable;
772
773 disable_rpm_wakeref_asserts(&i915->runtime_pm);
774
775 intel_vgpu_detect(i915);
776
777 ret = intel_gt_probe_all(i915);
778 if (ret < 0)
779 goto out_runtime_pm_put;
780
781 ret = i915_driver_mmio_probe(i915);
782 if (ret < 0)
783 goto out_tiles_cleanup;
784
785 ret = i915_driver_hw_probe(i915);
786 if (ret < 0)
787 goto out_cleanup_mmio;
788
789 ret = intel_modeset_init_noirq(i915);
790 if (ret < 0)
791 goto out_cleanup_hw;
792
793 ret = intel_irq_install(i915);
794 if (ret)
795 goto out_cleanup_modeset;
796
797 ret = intel_modeset_init_nogem(i915);
798 if (ret)
799 goto out_cleanup_irq;
800
801 ret = i915_gem_init(i915);
802 if (ret)
803 goto out_cleanup_modeset2;
804
805 intel_pxp_init(i915);
806
807 ret = intel_modeset_init(i915);
808 if (ret)
809 goto out_cleanup_gem;
810
811 i915_driver_register(i915);
812
813 enable_rpm_wakeref_asserts(&i915->runtime_pm);
814
815 i915_welcome_messages(i915);
816
817 i915->do_release = true;
818
819 return 0;
820
821 out_cleanup_gem:
822 i915_gem_suspend(i915);
823 i915_gem_driver_remove(i915);
824 i915_gem_driver_release(i915);
825 out_cleanup_modeset2:
826 /* FIXME clean up the error path */
827 intel_modeset_driver_remove(i915);
828 intel_irq_uninstall(i915);
829 intel_modeset_driver_remove_noirq(i915);
830 goto out_cleanup_modeset;
831 out_cleanup_irq:
832 intel_irq_uninstall(i915);
833 out_cleanup_modeset:
834 intel_modeset_driver_remove_nogem(i915);
835 out_cleanup_hw:
836 i915_driver_hw_remove(i915);
837 intel_memory_regions_driver_release(i915);
838 i915_ggtt_driver_release(i915);
839 i915_gem_drain_freed_objects(i915);
840 i915_ggtt_driver_late_release(i915);
841 out_cleanup_mmio:
842 i915_driver_mmio_release(i915);
843 out_tiles_cleanup:
844 intel_gt_release_all(i915);
845 out_runtime_pm_put:
846 enable_rpm_wakeref_asserts(&i915->runtime_pm);
847 i915_driver_late_release(i915);
848 out_pci_disable:
849 pci_disable_device(pdev);
850 out_fini:
851 i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
852 return ret;
853 }
854
i915_driver_remove(struct drm_i915_private * i915)855 void i915_driver_remove(struct drm_i915_private *i915)
856 {
857 intel_wakeref_t wakeref;
858
859 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
860
861 i915_driver_unregister(i915);
862
863 /* Flush any external code that still may be under the RCU lock */
864 synchronize_rcu();
865
866 i915_gem_suspend(i915);
867
868 intel_gvt_driver_remove(i915);
869
870 intel_modeset_driver_remove(i915);
871
872 intel_irq_uninstall(i915);
873
874 intel_modeset_driver_remove_noirq(i915);
875
876 i915_reset_error_state(i915);
877 i915_gem_driver_remove(i915);
878
879 intel_modeset_driver_remove_nogem(i915);
880
881 i915_driver_hw_remove(i915);
882
883 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
884 }
885
i915_driver_release(struct drm_device * dev)886 static void i915_driver_release(struct drm_device *dev)
887 {
888 struct drm_i915_private *dev_priv = to_i915(dev);
889 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
890 intel_wakeref_t wakeref;
891
892 if (!dev_priv->do_release)
893 return;
894
895 wakeref = intel_runtime_pm_get(rpm);
896
897 i915_gem_driver_release(dev_priv);
898
899 intel_memory_regions_driver_release(dev_priv);
900 i915_ggtt_driver_release(dev_priv);
901 i915_gem_drain_freed_objects(dev_priv);
902 i915_ggtt_driver_late_release(dev_priv);
903
904 i915_driver_mmio_release(dev_priv);
905
906 intel_runtime_pm_put(rpm, wakeref);
907
908 intel_runtime_pm_driver_release(rpm);
909
910 i915_driver_late_release(dev_priv);
911 }
912
i915_driver_open(struct drm_device * dev,struct drm_file * file)913 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
914 {
915 struct drm_i915_private *i915 = to_i915(dev);
916 int ret;
917
918 ret = i915_gem_open(i915, file);
919 if (ret)
920 return ret;
921
922 return 0;
923 }
924
925 /**
926 * i915_driver_lastclose - clean up after all DRM clients have exited
927 * @dev: DRM device
928 *
929 * Take care of cleaning up after all DRM clients have exited. In the
930 * mode setting case, we want to restore the kernel's initial mode (just
931 * in case the last client left us in a bad state).
932 *
933 * Additionally, in the non-mode setting case, we'll tear down the GTT
934 * and DMA structures, since the kernel won't be using them, and clea
935 * up any GEM state.
936 */
i915_driver_lastclose(struct drm_device * dev)937 static void i915_driver_lastclose(struct drm_device *dev)
938 {
939 intel_fbdev_restore_mode(dev);
940
941 vga_switcheroo_process_delayed_switch();
942 }
943
i915_driver_postclose(struct drm_device * dev,struct drm_file * file)944 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
945 {
946 struct drm_i915_file_private *file_priv = file->driver_priv;
947
948 i915_gem_context_close(file);
949 i915_drm_client_put(file_priv->client);
950
951 kfree_rcu(file_priv, rcu);
952
953 /* Catch up with all the deferred frees from "this" client */
954 i915_gem_flush_free_objects(to_i915(dev));
955 }
956
intel_suspend_encoders(struct drm_i915_private * dev_priv)957 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
958 {
959 struct intel_encoder *encoder;
960
961 if (!HAS_DISPLAY(dev_priv))
962 return;
963
964 drm_modeset_lock_all(&dev_priv->drm);
965 for_each_intel_encoder(&dev_priv->drm, encoder)
966 if (encoder->suspend)
967 encoder->suspend(encoder);
968 drm_modeset_unlock_all(&dev_priv->drm);
969 }
970
intel_shutdown_encoders(struct drm_i915_private * dev_priv)971 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv)
972 {
973 struct intel_encoder *encoder;
974
975 if (!HAS_DISPLAY(dev_priv))
976 return;
977
978 drm_modeset_lock_all(&dev_priv->drm);
979 for_each_intel_encoder(&dev_priv->drm, encoder)
980 if (encoder->shutdown)
981 encoder->shutdown(encoder);
982 drm_modeset_unlock_all(&dev_priv->drm);
983 }
984
i915_driver_shutdown(struct drm_i915_private * i915)985 void i915_driver_shutdown(struct drm_i915_private *i915)
986 {
987 disable_rpm_wakeref_asserts(&i915->runtime_pm);
988 intel_runtime_pm_disable(&i915->runtime_pm);
989 intel_power_domains_disable(i915);
990
991 if (HAS_DISPLAY(i915)) {
992 drm_kms_helper_poll_disable(&i915->drm);
993
994 drm_atomic_helper_shutdown(&i915->drm);
995 }
996
997 intel_dp_mst_suspend(i915);
998
999 intel_runtime_pm_disable_interrupts(i915);
1000 intel_hpd_cancel_work(i915);
1001
1002 intel_suspend_encoders(i915);
1003 intel_shutdown_encoders(i915);
1004
1005 intel_dmc_ucode_suspend(i915);
1006
1007 i915_gem_suspend(i915);
1008
1009 /*
1010 * The only requirement is to reboot with display DC states disabled,
1011 * for now leaving all display power wells in the INIT power domain
1012 * enabled.
1013 *
1014 * TODO:
1015 * - unify the pci_driver::shutdown sequence here with the
1016 * pci_driver.driver.pm.poweroff,poweroff_late sequence.
1017 * - unify the driver remove and system/runtime suspend sequences with
1018 * the above unified shutdown/poweroff sequence.
1019 */
1020 intel_power_domains_driver_remove(i915);
1021 enable_rpm_wakeref_asserts(&i915->runtime_pm);
1022
1023 intel_runtime_pm_driver_release(&i915->runtime_pm);
1024 }
1025
suspend_to_idle(struct drm_i915_private * dev_priv)1026 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1027 {
1028 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1029 if (acpi_target_system_state() < ACPI_STATE_S3)
1030 return true;
1031 #endif
1032 return false;
1033 }
1034
i915_drm_prepare(struct drm_device * dev)1035 static int i915_drm_prepare(struct drm_device *dev)
1036 {
1037 struct drm_i915_private *i915 = to_i915(dev);
1038
1039 intel_pxp_suspend_prepare(i915->pxp);
1040
1041 /*
1042 * NB intel_display_suspend() may issue new requests after we've
1043 * ostensibly marked the GPU as ready-to-sleep here. We need to
1044 * split out that work and pull it forward so that after point,
1045 * the GPU is not woken again.
1046 */
1047 return i915_gem_backup_suspend(i915);
1048 }
1049
i915_drm_suspend(struct drm_device * dev)1050 static int i915_drm_suspend(struct drm_device *dev)
1051 {
1052 struct drm_i915_private *dev_priv = to_i915(dev);
1053 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1054 pci_power_t opregion_target_state;
1055
1056 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1057
1058 /* We do a lot of poking in a lot of registers, make sure they work
1059 * properly. */
1060 intel_power_domains_disable(dev_priv);
1061 if (HAS_DISPLAY(dev_priv))
1062 drm_kms_helper_poll_disable(dev);
1063
1064 pci_save_state(pdev);
1065
1066 intel_display_suspend(dev);
1067
1068 intel_dp_mst_suspend(dev_priv);
1069
1070 intel_runtime_pm_disable_interrupts(dev_priv);
1071 intel_hpd_cancel_work(dev_priv);
1072
1073 intel_suspend_encoders(dev_priv);
1074
1075 intel_suspend_hw(dev_priv);
1076
1077 /* Must be called before GGTT is suspended. */
1078 intel_dpt_suspend(dev_priv);
1079 i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
1080
1081 i915_save_display(dev_priv);
1082
1083 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1084 intel_opregion_suspend(dev_priv, opregion_target_state);
1085
1086 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1087
1088 dev_priv->suspend_count++;
1089
1090 intel_dmc_ucode_suspend(dev_priv);
1091
1092 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1093
1094 i915_gem_drain_freed_objects(dev_priv);
1095
1096 return 0;
1097 }
1098
1099 static enum i915_drm_suspend_mode
get_suspend_mode(struct drm_i915_private * dev_priv,bool hibernate)1100 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1101 {
1102 if (hibernate)
1103 return I915_DRM_SUSPEND_HIBERNATE;
1104
1105 if (suspend_to_idle(dev_priv))
1106 return I915_DRM_SUSPEND_IDLE;
1107
1108 return I915_DRM_SUSPEND_MEM;
1109 }
1110
i915_drm_suspend_late(struct drm_device * dev,bool hibernation)1111 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1112 {
1113 struct drm_i915_private *dev_priv = to_i915(dev);
1114 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1115 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1116 struct intel_gt *gt;
1117 int ret, i;
1118
1119 disable_rpm_wakeref_asserts(rpm);
1120
1121 intel_pxp_suspend(dev_priv->pxp);
1122
1123 i915_gem_suspend_late(dev_priv);
1124
1125 for_each_gt(gt, dev_priv, i)
1126 intel_uncore_suspend(gt->uncore);
1127
1128 intel_power_domains_suspend(dev_priv,
1129 get_suspend_mode(dev_priv, hibernation));
1130
1131 intel_display_power_suspend_late(dev_priv);
1132
1133 ret = vlv_suspend_complete(dev_priv);
1134 if (ret) {
1135 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1136 intel_power_domains_resume(dev_priv);
1137
1138 goto out;
1139 }
1140
1141 pci_disable_device(pdev);
1142 /*
1143 * During hibernation on some platforms the BIOS may try to access
1144 * the device even though it's already in D3 and hang the machine. So
1145 * leave the device in D0 on those platforms and hope the BIOS will
1146 * power down the device properly. The issue was seen on multiple old
1147 * GENs with different BIOS vendors, so having an explicit blacklist
1148 * is inpractical; apply the workaround on everything pre GEN6. The
1149 * platforms where the issue was seen:
1150 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1151 * Fujitsu FSC S7110
1152 * Acer Aspire 1830T
1153 */
1154 if (!(hibernation && GRAPHICS_VER(dev_priv) < 6))
1155 pci_set_power_state(pdev, PCI_D3hot);
1156
1157 out:
1158 enable_rpm_wakeref_asserts(rpm);
1159 if (!dev_priv->uncore.user_forcewake_count)
1160 intel_runtime_pm_driver_release(rpm);
1161
1162 return ret;
1163 }
1164
i915_driver_suspend_switcheroo(struct drm_i915_private * i915,pm_message_t state)1165 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915,
1166 pm_message_t state)
1167 {
1168 int error;
1169
1170 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1171 state.event != PM_EVENT_FREEZE))
1172 return -EINVAL;
1173
1174 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1175 return 0;
1176
1177 error = i915_drm_suspend(&i915->drm);
1178 if (error)
1179 return error;
1180
1181 return i915_drm_suspend_late(&i915->drm, false);
1182 }
1183
i915_drm_resume(struct drm_device * dev)1184 static int i915_drm_resume(struct drm_device *dev)
1185 {
1186 struct drm_i915_private *dev_priv = to_i915(dev);
1187 struct intel_gt *gt;
1188 int ret, i;
1189
1190 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1191
1192 ret = i915_pcode_init(dev_priv);
1193 if (ret)
1194 return ret;
1195
1196 sanitize_gpu(dev_priv);
1197
1198 ret = i915_ggtt_enable_hw(dev_priv);
1199 if (ret)
1200 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1201
1202 i915_ggtt_resume(to_gt(dev_priv)->ggtt);
1203
1204 for_each_gt(gt, dev_priv, i)
1205 if (GRAPHICS_VER(gt->i915) >= 8)
1206 setup_private_pat(gt);
1207
1208 /* Must be called after GGTT is resumed. */
1209 intel_dpt_resume(dev_priv);
1210
1211 intel_dmc_ucode_resume(dev_priv);
1212
1213 i915_restore_display(dev_priv);
1214 intel_pps_unlock_regs_wa(dev_priv);
1215
1216 intel_init_pch_refclk(dev_priv);
1217
1218 /*
1219 * Interrupts have to be enabled before any batches are run. If not the
1220 * GPU will hang. i915_gem_init_hw() will initiate batches to
1221 * update/restore the context.
1222 *
1223 * drm_mode_config_reset() needs AUX interrupts.
1224 *
1225 * Modeset enabling in intel_modeset_init_hw() also needs working
1226 * interrupts.
1227 */
1228 intel_runtime_pm_enable_interrupts(dev_priv);
1229
1230 if (HAS_DISPLAY(dev_priv))
1231 drm_mode_config_reset(dev);
1232
1233 i915_gem_resume(dev_priv);
1234
1235 intel_pxp_resume(dev_priv->pxp);
1236
1237 intel_modeset_init_hw(dev_priv);
1238 intel_init_clock_gating(dev_priv);
1239 intel_hpd_init(dev_priv);
1240
1241 /* MST sideband requires HPD interrupts enabled */
1242 intel_dp_mst_resume(dev_priv);
1243 intel_display_resume(dev);
1244
1245 intel_hpd_poll_disable(dev_priv);
1246 if (HAS_DISPLAY(dev_priv))
1247 drm_kms_helper_poll_enable(dev);
1248
1249 intel_opregion_resume(dev_priv);
1250
1251 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1252
1253 intel_power_domains_enable(dev_priv);
1254
1255 intel_gvt_resume(dev_priv);
1256
1257 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1258
1259 return 0;
1260 }
1261
i915_drm_resume_early(struct drm_device * dev)1262 static int i915_drm_resume_early(struct drm_device *dev)
1263 {
1264 struct drm_i915_private *dev_priv = to_i915(dev);
1265 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1266 struct intel_gt *gt;
1267 int ret, i;
1268
1269 /*
1270 * We have a resume ordering issue with the snd-hda driver also
1271 * requiring our device to be power up. Due to the lack of a
1272 * parent/child relationship we currently solve this with an early
1273 * resume hook.
1274 *
1275 * FIXME: This should be solved with a special hdmi sink device or
1276 * similar so that power domains can be employed.
1277 */
1278
1279 /*
1280 * Note that we need to set the power state explicitly, since we
1281 * powered off the device during freeze and the PCI core won't power
1282 * it back up for us during thaw. Powering off the device during
1283 * freeze is not a hard requirement though, and during the
1284 * suspend/resume phases the PCI core makes sure we get here with the
1285 * device powered on. So in case we change our freeze logic and keep
1286 * the device powered we can also remove the following set power state
1287 * call.
1288 */
1289 ret = pci_set_power_state(pdev, PCI_D0);
1290 if (ret) {
1291 drm_err(&dev_priv->drm,
1292 "failed to set PCI D0 power state (%d)\n", ret);
1293 return ret;
1294 }
1295
1296 /*
1297 * Note that pci_enable_device() first enables any parent bridge
1298 * device and only then sets the power state for this device. The
1299 * bridge enabling is a nop though, since bridge devices are resumed
1300 * first. The order of enabling power and enabling the device is
1301 * imposed by the PCI core as described above, so here we preserve the
1302 * same order for the freeze/thaw phases.
1303 *
1304 * TODO: eventually we should remove pci_disable_device() /
1305 * pci_enable_enable_device() from suspend/resume. Due to how they
1306 * depend on the device enable refcount we can't anyway depend on them
1307 * disabling/enabling the device.
1308 */
1309 if (pci_enable_device(pdev))
1310 return -EIO;
1311
1312 pci_set_master(pdev);
1313
1314 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1315
1316 ret = vlv_resume_prepare(dev_priv, false);
1317 if (ret)
1318 drm_err(&dev_priv->drm,
1319 "Resume prepare failed: %d, continuing anyway\n", ret);
1320
1321 for_each_gt(gt, dev_priv, i) {
1322 intel_uncore_resume_early(gt->uncore);
1323 intel_gt_check_and_clear_faults(gt);
1324 }
1325
1326 intel_display_power_resume_early(dev_priv);
1327
1328 intel_power_domains_resume(dev_priv);
1329
1330 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1331
1332 return ret;
1333 }
1334
i915_driver_resume_switcheroo(struct drm_i915_private * i915)1335 int i915_driver_resume_switcheroo(struct drm_i915_private *i915)
1336 {
1337 int ret;
1338
1339 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1340 return 0;
1341
1342 ret = i915_drm_resume_early(&i915->drm);
1343 if (ret)
1344 return ret;
1345
1346 return i915_drm_resume(&i915->drm);
1347 }
1348
i915_pm_prepare(struct device * kdev)1349 static int i915_pm_prepare(struct device *kdev)
1350 {
1351 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1352
1353 if (!i915) {
1354 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1355 return -ENODEV;
1356 }
1357
1358 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1359 return 0;
1360
1361 return i915_drm_prepare(&i915->drm);
1362 }
1363
i915_pm_suspend(struct device * kdev)1364 static int i915_pm_suspend(struct device *kdev)
1365 {
1366 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1367
1368 if (!i915) {
1369 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1370 return -ENODEV;
1371 }
1372
1373 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1374 return 0;
1375
1376 return i915_drm_suspend(&i915->drm);
1377 }
1378
i915_pm_suspend_late(struct device * kdev)1379 static int i915_pm_suspend_late(struct device *kdev)
1380 {
1381 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1382
1383 /*
1384 * We have a suspend ordering issue with the snd-hda driver also
1385 * requiring our device to be power up. Due to the lack of a
1386 * parent/child relationship we currently solve this with an late
1387 * suspend hook.
1388 *
1389 * FIXME: This should be solved with a special hdmi sink device or
1390 * similar so that power domains can be employed.
1391 */
1392 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1393 return 0;
1394
1395 return i915_drm_suspend_late(&i915->drm, false);
1396 }
1397
i915_pm_poweroff_late(struct device * kdev)1398 static int i915_pm_poweroff_late(struct device *kdev)
1399 {
1400 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1401
1402 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1403 return 0;
1404
1405 return i915_drm_suspend_late(&i915->drm, true);
1406 }
1407
i915_pm_resume_early(struct device * kdev)1408 static int i915_pm_resume_early(struct device *kdev)
1409 {
1410 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1411
1412 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1413 return 0;
1414
1415 return i915_drm_resume_early(&i915->drm);
1416 }
1417
i915_pm_resume(struct device * kdev)1418 static int i915_pm_resume(struct device *kdev)
1419 {
1420 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1421
1422 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1423 return 0;
1424
1425 return i915_drm_resume(&i915->drm);
1426 }
1427
1428 /* freeze: before creating the hibernation_image */
i915_pm_freeze(struct device * kdev)1429 static int i915_pm_freeze(struct device *kdev)
1430 {
1431 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1432 int ret;
1433
1434 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1435 ret = i915_drm_suspend(&i915->drm);
1436 if (ret)
1437 return ret;
1438 }
1439
1440 ret = i915_gem_freeze(i915);
1441 if (ret)
1442 return ret;
1443
1444 return 0;
1445 }
1446
i915_pm_freeze_late(struct device * kdev)1447 static int i915_pm_freeze_late(struct device *kdev)
1448 {
1449 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1450 int ret;
1451
1452 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1453 ret = i915_drm_suspend_late(&i915->drm, true);
1454 if (ret)
1455 return ret;
1456 }
1457
1458 ret = i915_gem_freeze_late(i915);
1459 if (ret)
1460 return ret;
1461
1462 return 0;
1463 }
1464
1465 /* thaw: called after creating the hibernation image, but before turning off. */
i915_pm_thaw_early(struct device * kdev)1466 static int i915_pm_thaw_early(struct device *kdev)
1467 {
1468 return i915_pm_resume_early(kdev);
1469 }
1470
i915_pm_thaw(struct device * kdev)1471 static int i915_pm_thaw(struct device *kdev)
1472 {
1473 return i915_pm_resume(kdev);
1474 }
1475
1476 /* restore: called after loading the hibernation image. */
i915_pm_restore_early(struct device * kdev)1477 static int i915_pm_restore_early(struct device *kdev)
1478 {
1479 return i915_pm_resume_early(kdev);
1480 }
1481
i915_pm_restore(struct device * kdev)1482 static int i915_pm_restore(struct device *kdev)
1483 {
1484 return i915_pm_resume(kdev);
1485 }
1486
intel_runtime_suspend(struct device * kdev)1487 static int intel_runtime_suspend(struct device *kdev)
1488 {
1489 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1490 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1491 struct intel_gt *gt;
1492 int ret, i;
1493
1494 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1495 return -ENODEV;
1496
1497 drm_dbg(&dev_priv->drm, "Suspending device\n");
1498
1499 disable_rpm_wakeref_asserts(rpm);
1500
1501 /*
1502 * We are safe here against re-faults, since the fault handler takes
1503 * an RPM reference.
1504 */
1505 i915_gem_runtime_suspend(dev_priv);
1506
1507 intel_pxp_runtime_suspend(dev_priv->pxp);
1508
1509 for_each_gt(gt, dev_priv, i)
1510 intel_gt_runtime_suspend(gt);
1511
1512 intel_runtime_pm_disable_interrupts(dev_priv);
1513
1514 for_each_gt(gt, dev_priv, i)
1515 intel_uncore_suspend(gt->uncore);
1516
1517 intel_display_power_suspend(dev_priv);
1518
1519 ret = vlv_suspend_complete(dev_priv);
1520 if (ret) {
1521 drm_err(&dev_priv->drm,
1522 "Runtime suspend failed, disabling it (%d)\n", ret);
1523 intel_uncore_runtime_resume(&dev_priv->uncore);
1524
1525 intel_runtime_pm_enable_interrupts(dev_priv);
1526
1527 for_each_gt(gt, dev_priv, i)
1528 intel_gt_runtime_resume(gt);
1529
1530 enable_rpm_wakeref_asserts(rpm);
1531
1532 return ret;
1533 }
1534
1535 enable_rpm_wakeref_asserts(rpm);
1536 intel_runtime_pm_driver_release(rpm);
1537
1538 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1539 drm_err(&dev_priv->drm,
1540 "Unclaimed access detected prior to suspending\n");
1541
1542 rpm->suspended = true;
1543
1544 /*
1545 * FIXME: We really should find a document that references the arguments
1546 * used below!
1547 */
1548 if (IS_BROADWELL(dev_priv)) {
1549 /*
1550 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1551 * being detected, and the call we do at intel_runtime_resume()
1552 * won't be able to restore them. Since PCI_D3hot matches the
1553 * actual specification and appears to be working, use it.
1554 */
1555 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1556 } else {
1557 /*
1558 * current versions of firmware which depend on this opregion
1559 * notification have repurposed the D1 definition to mean
1560 * "runtime suspended" vs. what you would normally expect (D3)
1561 * to distinguish it from notifications that might be sent via
1562 * the suspend path.
1563 */
1564 intel_opregion_notify_adapter(dev_priv, PCI_D1);
1565 }
1566
1567 assert_forcewakes_inactive(&dev_priv->uncore);
1568
1569 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1570 intel_hpd_poll_enable(dev_priv);
1571
1572 drm_dbg(&dev_priv->drm, "Device suspended\n");
1573 return 0;
1574 }
1575
intel_runtime_resume(struct device * kdev)1576 static int intel_runtime_resume(struct device *kdev)
1577 {
1578 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1579 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1580 struct intel_gt *gt;
1581 int ret, i;
1582
1583 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1584 return -ENODEV;
1585
1586 drm_dbg(&dev_priv->drm, "Resuming device\n");
1587
1588 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1589 disable_rpm_wakeref_asserts(rpm);
1590
1591 intel_opregion_notify_adapter(dev_priv, PCI_D0);
1592 rpm->suspended = false;
1593 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1594 drm_dbg(&dev_priv->drm,
1595 "Unclaimed access during suspend, bios?\n");
1596
1597 intel_display_power_resume(dev_priv);
1598
1599 ret = vlv_resume_prepare(dev_priv, true);
1600
1601 for_each_gt(gt, dev_priv, i)
1602 intel_uncore_runtime_resume(gt->uncore);
1603
1604 intel_runtime_pm_enable_interrupts(dev_priv);
1605
1606 /*
1607 * No point of rolling back things in case of an error, as the best
1608 * we can do is to hope that things will still work (and disable RPM).
1609 */
1610 for_each_gt(gt, dev_priv, i)
1611 intel_gt_runtime_resume(gt);
1612
1613 intel_pxp_runtime_resume(dev_priv->pxp);
1614
1615 /*
1616 * On VLV/CHV display interrupts are part of the display
1617 * power well, so hpd is reinitialized from there. For
1618 * everyone else do it here.
1619 */
1620 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1621 intel_hpd_init(dev_priv);
1622 intel_hpd_poll_disable(dev_priv);
1623 }
1624
1625 skl_watermark_ipc_update(dev_priv);
1626
1627 enable_rpm_wakeref_asserts(rpm);
1628
1629 if (ret)
1630 drm_err(&dev_priv->drm,
1631 "Runtime resume failed, disabling it (%d)\n", ret);
1632 else
1633 drm_dbg(&dev_priv->drm, "Device resumed\n");
1634
1635 return ret;
1636 }
1637
1638 const struct dev_pm_ops i915_pm_ops = {
1639 /*
1640 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1641 * PMSG_RESUME]
1642 */
1643 .prepare = i915_pm_prepare,
1644 .suspend = i915_pm_suspend,
1645 .suspend_late = i915_pm_suspend_late,
1646 .resume_early = i915_pm_resume_early,
1647 .resume = i915_pm_resume,
1648
1649 /*
1650 * S4 event handlers
1651 * @freeze, @freeze_late : called (1) before creating the
1652 * hibernation image [PMSG_FREEZE] and
1653 * (2) after rebooting, before restoring
1654 * the image [PMSG_QUIESCE]
1655 * @thaw, @thaw_early : called (1) after creating the hibernation
1656 * image, before writing it [PMSG_THAW]
1657 * and (2) after failing to create or
1658 * restore the image [PMSG_RECOVER]
1659 * @poweroff, @poweroff_late: called after writing the hibernation
1660 * image, before rebooting [PMSG_HIBERNATE]
1661 * @restore, @restore_early : called after rebooting and restoring the
1662 * hibernation image [PMSG_RESTORE]
1663 */
1664 .freeze = i915_pm_freeze,
1665 .freeze_late = i915_pm_freeze_late,
1666 .thaw_early = i915_pm_thaw_early,
1667 .thaw = i915_pm_thaw,
1668 .poweroff = i915_pm_suspend,
1669 .poweroff_late = i915_pm_poweroff_late,
1670 .restore_early = i915_pm_restore_early,
1671 .restore = i915_pm_restore,
1672
1673 /* S0ix (via runtime suspend) event handlers */
1674 .runtime_suspend = intel_runtime_suspend,
1675 .runtime_resume = intel_runtime_resume,
1676 };
1677
1678 static const struct file_operations i915_driver_fops = {
1679 .owner = THIS_MODULE,
1680 .open = drm_open,
1681 .release = drm_release_noglobal,
1682 .unlocked_ioctl = drm_ioctl,
1683 .mmap = i915_gem_mmap,
1684 .poll = drm_poll,
1685 .read = drm_read,
1686 .compat_ioctl = i915_ioc32_compat_ioctl,
1687 .llseek = noop_llseek,
1688 #ifdef CONFIG_PROC_FS
1689 .show_fdinfo = i915_drm_client_fdinfo,
1690 #endif
1691 };
1692
1693 static int
i915_gem_reject_pin_ioctl(struct drm_device * dev,void * data,struct drm_file * file)1694 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1695 struct drm_file *file)
1696 {
1697 return -ENODEV;
1698 }
1699
1700 static const struct drm_ioctl_desc i915_ioctls[] = {
1701 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1702 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1703 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1704 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1705 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1706 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1707 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1708 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1709 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1710 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1711 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1712 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1713 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1714 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1715 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
1716 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1717 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1718 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1719 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH),
1720 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1721 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1722 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1723 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1724 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1725 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1726 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1727 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1728 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1729 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1730 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW),
1731 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1732 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1733 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1734 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1735 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1736 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1737 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1738 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1739 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1740 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1741 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1742 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1743 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1744 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1745 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1746 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1747 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1748 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1749 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1750 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1751 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1752 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1753 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1754 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1755 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1756 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1757 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1758 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1759 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1760 };
1761
1762 /*
1763 * Interface history:
1764 *
1765 * 1.1: Original.
1766 * 1.2: Add Power Management
1767 * 1.3: Add vblank support
1768 * 1.4: Fix cmdbuffer path, add heap destroy
1769 * 1.5: Add vblank pipe configuration
1770 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
1771 * - Support vertical blank on secondary display pipe
1772 */
1773 #define DRIVER_MAJOR 1
1774 #define DRIVER_MINOR 6
1775 #define DRIVER_PATCHLEVEL 0
1776
1777 static const struct drm_driver i915_drm_driver = {
1778 /* Don't use MTRRs here; the Xserver or userspace app should
1779 * deal with them for Intel hardware.
1780 */
1781 .driver_features =
1782 DRIVER_GEM |
1783 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1784 DRIVER_SYNCOBJ_TIMELINE,
1785 .release = i915_driver_release,
1786 .open = i915_driver_open,
1787 .lastclose = i915_driver_lastclose,
1788 .postclose = i915_driver_postclose,
1789
1790 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1791 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1792 .gem_prime_import = i915_gem_prime_import,
1793
1794 .dumb_create = i915_gem_dumb_create,
1795 .dumb_map_offset = i915_gem_dumb_mmap_offset,
1796
1797 .ioctls = i915_ioctls,
1798 .num_ioctls = ARRAY_SIZE(i915_ioctls),
1799 .fops = &i915_driver_fops,
1800 .name = DRIVER_NAME,
1801 .desc = DRIVER_DESC,
1802 .date = DRIVER_DATE,
1803 .major = DRIVER_MAJOR,
1804 .minor = DRIVER_MINOR,
1805 .patchlevel = DRIVER_PATCHLEVEL,
1806 };
1807