1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015 MediaTek Inc.
4 */
5
6 #include <drm/drm_fourcc.h>
7
8 #include <linux/clk.h>
9 #include <linux/component.h>
10 #include <linux/module.h>
11 #include <linux/of_device.h>
12 #include <linux/of_irq.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/soc/mediatek/mtk-cmdq.h>
16
17 #include "mtk_disp_drv.h"
18 #include "mtk_drm_crtc.h"
19 #include "mtk_drm_ddp_comp.h"
20 #include "mtk_drm_drv.h"
21
22 #define DISP_REG_RDMA_INT_ENABLE 0x0000
23 #define DISP_REG_RDMA_INT_STATUS 0x0004
24 #define RDMA_TARGET_LINE_INT BIT(5)
25 #define RDMA_FIFO_UNDERFLOW_INT BIT(4)
26 #define RDMA_EOF_ABNORMAL_INT BIT(3)
27 #define RDMA_FRAME_END_INT BIT(2)
28 #define RDMA_FRAME_START_INT BIT(1)
29 #define RDMA_REG_UPDATE_INT BIT(0)
30 #define DISP_REG_RDMA_GLOBAL_CON 0x0010
31 #define RDMA_ENGINE_EN BIT(0)
32 #define RDMA_MODE_MEMORY BIT(1)
33 #define DISP_REG_RDMA_SIZE_CON_0 0x0014
34 #define RDMA_MATRIX_ENABLE BIT(17)
35 #define RDMA_MATRIX_INT_MTX_SEL GENMASK(23, 20)
36 #define RDMA_MATRIX_INT_MTX_BT601_to_RGB (6 << 20)
37 #define DISP_REG_RDMA_SIZE_CON_1 0x0018
38 #define DISP_REG_RDMA_TARGET_LINE 0x001c
39 #define DISP_RDMA_MEM_CON 0x0024
40 #define MEM_MODE_INPUT_FORMAT_RGB565 (0x000 << 4)
41 #define MEM_MODE_INPUT_FORMAT_RGB888 (0x001 << 4)
42 #define MEM_MODE_INPUT_FORMAT_RGBA8888 (0x002 << 4)
43 #define MEM_MODE_INPUT_FORMAT_ARGB8888 (0x003 << 4)
44 #define MEM_MODE_INPUT_FORMAT_UYVY (0x004 << 4)
45 #define MEM_MODE_INPUT_FORMAT_YUYV (0x005 << 4)
46 #define MEM_MODE_INPUT_SWAP BIT(8)
47 #define DISP_RDMA_MEM_SRC_PITCH 0x002c
48 #define DISP_RDMA_MEM_GMC_SETTING_0 0x0030
49 #define DISP_REG_RDMA_FIFO_CON 0x0040
50 #define RDMA_FIFO_UNDERFLOW_EN BIT(31)
51 #define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16)
52 #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16)
53 #define RDMA_FIFO_SIZE(rdma) ((rdma)->data->fifo_size)
54 #define DISP_RDMA_MEM_START_ADDR 0x0f00
55
56 #define RDMA_MEM_GMC 0x40402020
57
58 struct mtk_disp_rdma_data {
59 unsigned int fifo_size;
60 };
61
62 /*
63 * struct mtk_disp_rdma - DISP_RDMA driver structure
64 * @data: local driver data
65 */
66 struct mtk_disp_rdma {
67 struct clk *clk;
68 void __iomem *regs;
69 struct cmdq_client_reg cmdq_reg;
70 const struct mtk_disp_rdma_data *data;
71 void (*vblank_cb)(void *data);
72 void *vblank_cb_data;
73 u32 fifo_size;
74 };
75
mtk_disp_rdma_irq_handler(int irq,void * dev_id)76 static irqreturn_t mtk_disp_rdma_irq_handler(int irq, void *dev_id)
77 {
78 struct mtk_disp_rdma *priv = dev_id;
79
80 /* Clear frame completion interrupt */
81 writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS);
82
83 if (!priv->vblank_cb)
84 return IRQ_NONE;
85
86 priv->vblank_cb(priv->vblank_cb_data);
87
88 return IRQ_HANDLED;
89 }
90
rdma_update_bits(struct device * dev,unsigned int reg,unsigned int mask,unsigned int val)91 static void rdma_update_bits(struct device *dev, unsigned int reg,
92 unsigned int mask, unsigned int val)
93 {
94 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
95 unsigned int tmp = readl(rdma->regs + reg);
96
97 tmp = (tmp & ~mask) | (val & mask);
98 writel(tmp, rdma->regs + reg);
99 }
100
mtk_rdma_register_vblank_cb(struct device * dev,void (* vblank_cb)(void *),void * vblank_cb_data)101 void mtk_rdma_register_vblank_cb(struct device *dev,
102 void (*vblank_cb)(void *),
103 void *vblank_cb_data)
104 {
105 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
106
107 rdma->vblank_cb = vblank_cb;
108 rdma->vblank_cb_data = vblank_cb_data;
109 }
110
mtk_rdma_unregister_vblank_cb(struct device * dev)111 void mtk_rdma_unregister_vblank_cb(struct device *dev)
112 {
113 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
114
115 rdma->vblank_cb = NULL;
116 rdma->vblank_cb_data = NULL;
117 }
118
mtk_rdma_enable_vblank(struct device * dev)119 void mtk_rdma_enable_vblank(struct device *dev)
120 {
121 rdma_update_bits(dev, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT,
122 RDMA_FRAME_END_INT);
123 }
124
mtk_rdma_disable_vblank(struct device * dev)125 void mtk_rdma_disable_vblank(struct device *dev)
126 {
127 rdma_update_bits(dev, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 0);
128 }
129
mtk_rdma_clk_enable(struct device * dev)130 int mtk_rdma_clk_enable(struct device *dev)
131 {
132 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
133
134 return clk_prepare_enable(rdma->clk);
135 }
136
mtk_rdma_clk_disable(struct device * dev)137 void mtk_rdma_clk_disable(struct device *dev)
138 {
139 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
140
141 clk_disable_unprepare(rdma->clk);
142 }
143
mtk_rdma_start(struct device * dev)144 void mtk_rdma_start(struct device *dev)
145 {
146 rdma_update_bits(dev, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN,
147 RDMA_ENGINE_EN);
148 }
149
mtk_rdma_stop(struct device * dev)150 void mtk_rdma_stop(struct device *dev)
151 {
152 rdma_update_bits(dev, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0);
153 }
154
mtk_rdma_config(struct device * dev,unsigned int width,unsigned int height,unsigned int vrefresh,unsigned int bpc,struct cmdq_pkt * cmdq_pkt)155 void mtk_rdma_config(struct device *dev, unsigned int width,
156 unsigned int height, unsigned int vrefresh,
157 unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
158 {
159 unsigned int threshold;
160 unsigned int reg;
161 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
162 u32 rdma_fifo_size;
163
164 mtk_ddp_write_mask(cmdq_pkt, width, &rdma->cmdq_reg, rdma->regs,
165 DISP_REG_RDMA_SIZE_CON_0, 0xfff);
166 mtk_ddp_write_mask(cmdq_pkt, height, &rdma->cmdq_reg, rdma->regs,
167 DISP_REG_RDMA_SIZE_CON_1, 0xfffff);
168
169 if (rdma->fifo_size)
170 rdma_fifo_size = rdma->fifo_size;
171 else
172 rdma_fifo_size = RDMA_FIFO_SIZE(rdma);
173
174 /*
175 * Enable FIFO underflow since DSI and DPI can't be blocked.
176 * Keep the FIFO pseudo size reset default of 8 KiB. Set the
177 * output threshold to 70% of max fifo size to make sure the
178 * threhold will not overflow
179 */
180 threshold = rdma_fifo_size * 7 / 10;
181 reg = RDMA_FIFO_UNDERFLOW_EN |
182 RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) |
183 RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
184 mtk_ddp_write(cmdq_pkt, reg, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_FIFO_CON);
185 }
186
rdma_fmt_convert(struct mtk_disp_rdma * rdma,unsigned int fmt)187 static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
188 unsigned int fmt)
189 {
190 /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"
191 * is defined in mediatek HW data sheet.
192 * The alphabet order in XXX is no relation to data
193 * arrangement in memory.
194 */
195 switch (fmt) {
196 default:
197 case DRM_FORMAT_RGB565:
198 return MEM_MODE_INPUT_FORMAT_RGB565;
199 case DRM_FORMAT_BGR565:
200 return MEM_MODE_INPUT_FORMAT_RGB565 | MEM_MODE_INPUT_SWAP;
201 case DRM_FORMAT_RGB888:
202 return MEM_MODE_INPUT_FORMAT_RGB888;
203 case DRM_FORMAT_BGR888:
204 return MEM_MODE_INPUT_FORMAT_RGB888 | MEM_MODE_INPUT_SWAP;
205 case DRM_FORMAT_RGBX8888:
206 case DRM_FORMAT_RGBA8888:
207 return MEM_MODE_INPUT_FORMAT_ARGB8888;
208 case DRM_FORMAT_BGRX8888:
209 case DRM_FORMAT_BGRA8888:
210 return MEM_MODE_INPUT_FORMAT_ARGB8888 | MEM_MODE_INPUT_SWAP;
211 case DRM_FORMAT_XRGB8888:
212 case DRM_FORMAT_ARGB8888:
213 return MEM_MODE_INPUT_FORMAT_RGBA8888;
214 case DRM_FORMAT_XBGR8888:
215 case DRM_FORMAT_ABGR8888:
216 return MEM_MODE_INPUT_FORMAT_RGBA8888 | MEM_MODE_INPUT_SWAP;
217 case DRM_FORMAT_UYVY:
218 return MEM_MODE_INPUT_FORMAT_UYVY;
219 case DRM_FORMAT_YUYV:
220 return MEM_MODE_INPUT_FORMAT_YUYV;
221 }
222 }
223
mtk_rdma_layer_nr(struct device * dev)224 unsigned int mtk_rdma_layer_nr(struct device *dev)
225 {
226 return 1;
227 }
228
mtk_rdma_layer_config(struct device * dev,unsigned int idx,struct mtk_plane_state * state,struct cmdq_pkt * cmdq_pkt)229 void mtk_rdma_layer_config(struct device *dev, unsigned int idx,
230 struct mtk_plane_state *state,
231 struct cmdq_pkt *cmdq_pkt)
232 {
233 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
234 struct mtk_plane_pending_state *pending = &state->pending;
235 unsigned int addr = pending->addr;
236 unsigned int pitch = pending->pitch & 0xffff;
237 unsigned int fmt = pending->format;
238 unsigned int con;
239
240 con = rdma_fmt_convert(rdma, fmt);
241 mtk_ddp_write_relaxed(cmdq_pkt, con, &rdma->cmdq_reg, rdma->regs, DISP_RDMA_MEM_CON);
242
243 if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) {
244 mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, &rdma->cmdq_reg, rdma->regs,
245 DISP_REG_RDMA_SIZE_CON_0,
246 RDMA_MATRIX_ENABLE);
247 mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB,
248 &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_SIZE_CON_0,
249 RDMA_MATRIX_INT_MTX_SEL);
250 } else {
251 mtk_ddp_write_mask(cmdq_pkt, 0, &rdma->cmdq_reg, rdma->regs,
252 DISP_REG_RDMA_SIZE_CON_0,
253 RDMA_MATRIX_ENABLE);
254 }
255 mtk_ddp_write_relaxed(cmdq_pkt, addr, &rdma->cmdq_reg, rdma->regs,
256 DISP_RDMA_MEM_START_ADDR);
257 mtk_ddp_write_relaxed(cmdq_pkt, pitch, &rdma->cmdq_reg, rdma->regs,
258 DISP_RDMA_MEM_SRC_PITCH);
259 mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, &rdma->cmdq_reg, rdma->regs,
260 DISP_RDMA_MEM_GMC_SETTING_0);
261 mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, &rdma->cmdq_reg, rdma->regs,
262 DISP_REG_RDMA_GLOBAL_CON, RDMA_MODE_MEMORY);
263
264 }
265
mtk_disp_rdma_bind(struct device * dev,struct device * master,void * data)266 static int mtk_disp_rdma_bind(struct device *dev, struct device *master,
267 void *data)
268 {
269 return 0;
270
271 }
272
mtk_disp_rdma_unbind(struct device * dev,struct device * master,void * data)273 static void mtk_disp_rdma_unbind(struct device *dev, struct device *master,
274 void *data)
275 {
276 }
277
278 static const struct component_ops mtk_disp_rdma_component_ops = {
279 .bind = mtk_disp_rdma_bind,
280 .unbind = mtk_disp_rdma_unbind,
281 };
282
mtk_disp_rdma_probe(struct platform_device * pdev)283 static int mtk_disp_rdma_probe(struct platform_device *pdev)
284 {
285 struct device *dev = &pdev->dev;
286 struct mtk_disp_rdma *priv;
287 struct resource *res;
288 int irq;
289 int ret;
290
291 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
292 if (!priv)
293 return -ENOMEM;
294
295 irq = platform_get_irq(pdev, 0);
296 if (irq < 0)
297 return irq;
298
299 priv->clk = devm_clk_get(dev, NULL);
300 if (IS_ERR(priv->clk)) {
301 dev_err(dev, "failed to get rdma clk\n");
302 return PTR_ERR(priv->clk);
303 }
304
305 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
306 priv->regs = devm_ioremap_resource(dev, res);
307 if (IS_ERR(priv->regs)) {
308 dev_err(dev, "failed to ioremap rdma\n");
309 return PTR_ERR(priv->regs);
310 }
311 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
312 ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
313 if (ret)
314 dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
315 #endif
316
317 if (of_find_property(dev->of_node, "mediatek,rdma-fifo-size", &ret)) {
318 ret = of_property_read_u32(dev->of_node,
319 "mediatek,rdma-fifo-size",
320 &priv->fifo_size);
321 if (ret) {
322 dev_err(dev, "Failed to get rdma fifo size\n");
323 return ret;
324 }
325 }
326
327 /* Disable and clear pending interrupts */
328 writel(0x0, priv->regs + DISP_REG_RDMA_INT_ENABLE);
329 writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS);
330
331 ret = devm_request_irq(dev, irq, mtk_disp_rdma_irq_handler,
332 IRQF_TRIGGER_NONE, dev_name(dev), priv);
333 if (ret < 0) {
334 dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
335 return ret;
336 }
337
338 priv->data = of_device_get_match_data(dev);
339
340 platform_set_drvdata(pdev, priv);
341
342 pm_runtime_enable(dev);
343
344 ret = component_add(dev, &mtk_disp_rdma_component_ops);
345 if (ret) {
346 pm_runtime_disable(dev);
347 dev_err(dev, "Failed to add component: %d\n", ret);
348 }
349
350 return ret;
351 }
352
mtk_disp_rdma_remove(struct platform_device * pdev)353 static int mtk_disp_rdma_remove(struct platform_device *pdev)
354 {
355 component_del(&pdev->dev, &mtk_disp_rdma_component_ops);
356
357 pm_runtime_disable(&pdev->dev);
358
359 return 0;
360 }
361
362 static const struct mtk_disp_rdma_data mt2701_rdma_driver_data = {
363 .fifo_size = SZ_4K,
364 };
365
366 static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = {
367 .fifo_size = SZ_8K,
368 };
369
370 static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
371 .fifo_size = 5 * SZ_1K,
372 };
373
374 static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
375 .fifo_size = 1920,
376 };
377
378 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
379 { .compatible = "mediatek,mt2701-disp-rdma",
380 .data = &mt2701_rdma_driver_data},
381 { .compatible = "mediatek,mt8173-disp-rdma",
382 .data = &mt8173_rdma_driver_data},
383 { .compatible = "mediatek,mt8183-disp-rdma",
384 .data = &mt8183_rdma_driver_data},
385 { .compatible = "mediatek,mt8195-disp-rdma",
386 .data = &mt8195_rdma_driver_data},
387 {},
388 };
389 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
390
391 struct platform_driver mtk_disp_rdma_driver = {
392 .probe = mtk_disp_rdma_probe,
393 .remove = mtk_disp_rdma_remove,
394 .driver = {
395 .name = "mediatek-disp-rdma",
396 .owner = THIS_MODULE,
397 .of_match_table = mtk_disp_rdma_driver_dt_match,
398 },
399 };
400