1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * R-Car LVDS Encoder
4  *
5  * Copyright (C) 2013-2018 Renesas Electronics Corporation
6  *
7  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8  */
9 
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/io.h>
13 #include <linux/media-bus-format.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_device.h>
17 #include <linux/of_graph.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/reset.h>
21 #include <linux/slab.h>
22 #include <linux/sys_soc.h>
23 
24 #include <drm/drm_atomic.h>
25 #include <drm/drm_atomic_helper.h>
26 #include <drm/drm_bridge.h>
27 #include <drm/drm_of.h>
28 #include <drm/drm_panel.h>
29 #include <drm/drm_print.h>
30 #include <drm/drm_probe_helper.h>
31 
32 #include "rcar_lvds.h"
33 #include "rcar_lvds_regs.h"
34 
35 struct rcar_lvds;
36 
37 /* Keep in sync with the LVDCR0.LVMD hardware register values. */
38 enum rcar_lvds_mode {
39 	RCAR_LVDS_MODE_JEIDA = 0,
40 	RCAR_LVDS_MODE_MIRROR = 1,
41 	RCAR_LVDS_MODE_VESA = 4,
42 };
43 
44 enum rcar_lvds_link_type {
45 	RCAR_LVDS_SINGLE_LINK = 0,
46 	RCAR_LVDS_DUAL_LINK_EVEN_ODD_PIXELS = 1,
47 	RCAR_LVDS_DUAL_LINK_ODD_EVEN_PIXELS = 2,
48 };
49 
50 #define RCAR_LVDS_QUIRK_LANES		BIT(0)	/* LVDS lanes 1 and 3 inverted */
51 #define RCAR_LVDS_QUIRK_GEN3_LVEN	BIT(1)	/* LVEN bit needs to be set on R8A77970/R8A7799x */
52 #define RCAR_LVDS_QUIRK_PWD		BIT(2)	/* PWD bit available (all of Gen3 but E3) */
53 #define RCAR_LVDS_QUIRK_EXT_PLL		BIT(3)	/* Has extended PLL */
54 #define RCAR_LVDS_QUIRK_DUAL_LINK	BIT(4)	/* Supports dual-link operation */
55 
56 struct rcar_lvds_device_info {
57 	unsigned int gen;
58 	unsigned int quirks;
59 	void (*pll_setup)(struct rcar_lvds *lvds, unsigned int freq);
60 };
61 
62 struct rcar_lvds {
63 	struct device *dev;
64 	const struct rcar_lvds_device_info *info;
65 	struct reset_control *rstc;
66 
67 	struct drm_bridge bridge;
68 
69 	struct drm_bridge *next_bridge;
70 	struct drm_panel *panel;
71 
72 	void __iomem *mmio;
73 	struct {
74 		struct clk *mod;		/* CPG module clock */
75 		struct clk *extal;		/* External clock */
76 		struct clk *dotclkin[2];	/* External DU clocks */
77 	} clocks;
78 
79 	struct drm_bridge *companion;
80 	enum rcar_lvds_link_type link_type;
81 };
82 
83 #define bridge_to_rcar_lvds(b) \
84 	container_of(b, struct rcar_lvds, bridge)
85 
rcar_lvds_read(struct rcar_lvds * lvds,u32 reg)86 static u32 rcar_lvds_read(struct rcar_lvds *lvds, u32 reg)
87 {
88 	return ioread32(lvds->mmio + reg);
89 }
90 
rcar_lvds_write(struct rcar_lvds * lvds,u32 reg,u32 data)91 static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data)
92 {
93 	iowrite32(data, lvds->mmio + reg);
94 }
95 
96 /* -----------------------------------------------------------------------------
97  * PLL Setup
98  */
99 
rcar_lvds_pll_setup_gen2(struct rcar_lvds * lvds,unsigned int freq)100 static void rcar_lvds_pll_setup_gen2(struct rcar_lvds *lvds, unsigned int freq)
101 {
102 	u32 val;
103 
104 	if (freq < 39000000)
105 		val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M;
106 	else if (freq < 61000000)
107 		val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M;
108 	else if (freq < 121000000)
109 		val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M;
110 	else
111 		val = LVDPLLCR_PLLDLYCNT_150M;
112 
113 	rcar_lvds_write(lvds, LVDPLLCR, val);
114 }
115 
rcar_lvds_pll_setup_gen3(struct rcar_lvds * lvds,unsigned int freq)116 static void rcar_lvds_pll_setup_gen3(struct rcar_lvds *lvds, unsigned int freq)
117 {
118 	u32 val;
119 
120 	if (freq < 42000000)
121 		val = LVDPLLCR_PLLDIVCNT_42M;
122 	else if (freq < 85000000)
123 		val = LVDPLLCR_PLLDIVCNT_85M;
124 	else if (freq < 128000000)
125 		val = LVDPLLCR_PLLDIVCNT_128M;
126 	else
127 		val = LVDPLLCR_PLLDIVCNT_148M;
128 
129 	rcar_lvds_write(lvds, LVDPLLCR, val);
130 }
131 
132 struct pll_info {
133 	unsigned long diff;
134 	unsigned int pll_m;
135 	unsigned int pll_n;
136 	unsigned int pll_e;
137 	unsigned int div;
138 	u32 clksel;
139 };
140 
rcar_lvds_d3_e3_pll_calc(struct rcar_lvds * lvds,struct clk * clk,unsigned long target,struct pll_info * pll,u32 clksel,bool dot_clock_only)141 static void rcar_lvds_d3_e3_pll_calc(struct rcar_lvds *lvds, struct clk *clk,
142 				     unsigned long target, struct pll_info *pll,
143 				     u32 clksel, bool dot_clock_only)
144 {
145 	unsigned int div7 = dot_clock_only ? 1 : 7;
146 	unsigned long output;
147 	unsigned long fin;
148 	unsigned int m_min;
149 	unsigned int m_max;
150 	unsigned int m;
151 	int error;
152 
153 	if (!clk)
154 		return;
155 
156 	/*
157 	 * The LVDS PLL is made of a pre-divider and a multiplier (strangely
158 	 * enough called M and N respectively), followed by a post-divider E.
159 	 *
160 	 *         ,-----.         ,-----.     ,-----.         ,-----.
161 	 * Fin --> | 1/M | -Fpdf-> | PFD | --> | VCO | -Fvco-> | 1/E | --> Fout
162 	 *         `-----'     ,-> |     |     `-----'   |     `-----'
163 	 *                     |   `-----'               |
164 	 *                     |         ,-----.         |
165 	 *                     `-------- | 1/N | <-------'
166 	 *                               `-----'
167 	 *
168 	 * The clock output by the PLL is then further divided by a programmable
169 	 * divider DIV to achieve the desired target frequency. Finally, an
170 	 * optional fixed /7 divider is used to convert the bit clock to a pixel
171 	 * clock (as LVDS transmits 7 bits per lane per clock sample).
172 	 *
173 	 *          ,-------.     ,-----.     |\
174 	 * Fout --> | 1/DIV | --> | 1/7 | --> | |
175 	 *          `-------'  |  `-----'     | | --> dot clock
176 	 *                     `------------> | |
177 	 *                                    |/
178 	 *
179 	 * The /7 divider is optional, it is enabled when the LVDS PLL is used
180 	 * to drive the LVDS encoder, and disabled when  used to generate a dot
181 	 * clock for the DU RGB output, without using the LVDS encoder.
182 	 *
183 	 * The PLL allowed input frequency range is 12 MHz to 192 MHz.
184 	 */
185 
186 	fin = clk_get_rate(clk);
187 	if (fin < 12000000 || fin > 192000000)
188 		return;
189 
190 	/*
191 	 * The comparison frequency range is 12 MHz to 24 MHz, which limits the
192 	 * allowed values for the pre-divider M (normal range 1-8).
193 	 *
194 	 * Fpfd = Fin / M
195 	 */
196 	m_min = max_t(unsigned int, 1, DIV_ROUND_UP(fin, 24000000));
197 	m_max = min_t(unsigned int, 8, fin / 12000000);
198 
199 	for (m = m_min; m <= m_max; ++m) {
200 		unsigned long fpfd;
201 		unsigned int n_min;
202 		unsigned int n_max;
203 		unsigned int n;
204 
205 		/*
206 		 * The VCO operating range is 900 Mhz to 1800 MHz, which limits
207 		 * the allowed values for the multiplier N (normal range
208 		 * 60-120).
209 		 *
210 		 * Fvco = Fin * N / M
211 		 */
212 		fpfd = fin / m;
213 		n_min = max_t(unsigned int, 60, DIV_ROUND_UP(900000000, fpfd));
214 		n_max = min_t(unsigned int, 120, 1800000000 / fpfd);
215 
216 		for (n = n_min; n < n_max; ++n) {
217 			unsigned long fvco;
218 			unsigned int e_min;
219 			unsigned int e;
220 
221 			/*
222 			 * The output frequency is limited to 1039.5 MHz,
223 			 * limiting again the allowed values for the
224 			 * post-divider E (normal value 1, 2 or 4).
225 			 *
226 			 * Fout = Fvco / E
227 			 */
228 			fvco = fpfd * n;
229 			e_min = fvco > 1039500000 ? 1 : 0;
230 
231 			for (e = e_min; e < 3; ++e) {
232 				unsigned long fout;
233 				unsigned long diff;
234 				unsigned int div;
235 
236 				/*
237 				 * Finally we have a programable divider after
238 				 * the PLL, followed by a an optional fixed /7
239 				 * divider.
240 				 */
241 				fout = fvco / (1 << e) / div7;
242 				div = max(1UL, DIV_ROUND_CLOSEST(fout, target));
243 				diff = abs(fout / div - target);
244 
245 				if (diff < pll->diff) {
246 					pll->diff = diff;
247 					pll->pll_m = m;
248 					pll->pll_n = n;
249 					pll->pll_e = e;
250 					pll->div = div;
251 					pll->clksel = clksel;
252 
253 					if (diff == 0)
254 						goto done;
255 				}
256 			}
257 		}
258 	}
259 
260 done:
261 	output = fin * pll->pll_n / pll->pll_m / (1 << pll->pll_e)
262 	       / div7 / pll->div;
263 	error = (long)(output - target) * 10000 / (long)target;
264 
265 	dev_dbg(lvds->dev,
266 		"%pC %lu Hz -> Fout %lu Hz (target %lu Hz, error %d.%02u%%), PLL M/N/E/DIV %u/%u/%u/%u\n",
267 		clk, fin, output, target, error / 100,
268 		error < 0 ? -error % 100 : error % 100,
269 		pll->pll_m, pll->pll_n, pll->pll_e, pll->div);
270 }
271 
__rcar_lvds_pll_setup_d3_e3(struct rcar_lvds * lvds,unsigned int freq,bool dot_clock_only)272 static void __rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds,
273 					unsigned int freq, bool dot_clock_only)
274 {
275 	struct pll_info pll = { .diff = (unsigned long)-1 };
276 	u32 lvdpllcr;
277 
278 	rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[0], freq, &pll,
279 				 LVDPLLCR_CKSEL_DU_DOTCLKIN(0), dot_clock_only);
280 	rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[1], freq, &pll,
281 				 LVDPLLCR_CKSEL_DU_DOTCLKIN(1), dot_clock_only);
282 	rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.extal, freq, &pll,
283 				 LVDPLLCR_CKSEL_EXTAL, dot_clock_only);
284 
285 	lvdpllcr = LVDPLLCR_PLLON | pll.clksel | LVDPLLCR_CLKOUT
286 		 | LVDPLLCR_PLLN(pll.pll_n - 1) | LVDPLLCR_PLLM(pll.pll_m - 1);
287 
288 	if (pll.pll_e > 0)
289 		lvdpllcr |= LVDPLLCR_STP_CLKOUTE | LVDPLLCR_OUTCLKSEL
290 			 |  LVDPLLCR_PLLE(pll.pll_e - 1);
291 
292 	if (dot_clock_only)
293 		lvdpllcr |= LVDPLLCR_OCKSEL;
294 
295 	rcar_lvds_write(lvds, LVDPLLCR, lvdpllcr);
296 
297 	if (pll.div > 1)
298 		/*
299 		 * The DIVRESET bit is a misnomer, setting it to 1 deasserts the
300 		 * divisor reset.
301 		 */
302 		rcar_lvds_write(lvds, LVDDIV, LVDDIV_DIVSEL |
303 				LVDDIV_DIVRESET | LVDDIV_DIV(pll.div - 1));
304 	else
305 		rcar_lvds_write(lvds, LVDDIV, 0);
306 }
307 
rcar_lvds_pll_setup_d3_e3(struct rcar_lvds * lvds,unsigned int freq)308 static void rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds, unsigned int freq)
309 {
310 	__rcar_lvds_pll_setup_d3_e3(lvds, freq, false);
311 }
312 
313 /* -----------------------------------------------------------------------------
314  * Clock - D3/E3 only
315  */
316 
rcar_lvds_pclk_enable(struct drm_bridge * bridge,unsigned long freq)317 int rcar_lvds_pclk_enable(struct drm_bridge *bridge, unsigned long freq)
318 {
319 	struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
320 	int ret;
321 
322 	if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)))
323 		return -ENODEV;
324 
325 	dev_dbg(lvds->dev, "enabling LVDS PLL, freq=%luHz\n", freq);
326 
327 	ret = pm_runtime_resume_and_get(lvds->dev);
328 	if (ret)
329 		return ret;
330 
331 	__rcar_lvds_pll_setup_d3_e3(lvds, freq, true);
332 
333 	return 0;
334 }
335 EXPORT_SYMBOL_GPL(rcar_lvds_pclk_enable);
336 
rcar_lvds_pclk_disable(struct drm_bridge * bridge)337 void rcar_lvds_pclk_disable(struct drm_bridge *bridge)
338 {
339 	struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
340 
341 	if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)))
342 		return;
343 
344 	dev_dbg(lvds->dev, "disabling LVDS PLL\n");
345 
346 	rcar_lvds_write(lvds, LVDPLLCR, 0);
347 
348 	pm_runtime_put_sync(lvds->dev);
349 }
350 EXPORT_SYMBOL_GPL(rcar_lvds_pclk_disable);
351 
352 /* -----------------------------------------------------------------------------
353  * Bridge
354  */
355 
rcar_lvds_get_lvds_mode(struct rcar_lvds * lvds,const struct drm_connector * connector)356 static enum rcar_lvds_mode rcar_lvds_get_lvds_mode(struct rcar_lvds *lvds,
357 					const struct drm_connector *connector)
358 {
359 	const struct drm_display_info *info;
360 	enum rcar_lvds_mode mode;
361 
362 	/*
363 	 * There is no API yet to retrieve LVDS mode from a bridge, only panels
364 	 * are supported.
365 	 */
366 	if (!lvds->panel)
367 		return RCAR_LVDS_MODE_JEIDA;
368 
369 	info = &connector->display_info;
370 	if (!info->num_bus_formats || !info->bus_formats) {
371 		dev_warn(lvds->dev,
372 			 "no LVDS bus format reported, using JEIDA\n");
373 		return RCAR_LVDS_MODE_JEIDA;
374 	}
375 
376 	switch (info->bus_formats[0]) {
377 	case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
378 	case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
379 		mode = RCAR_LVDS_MODE_JEIDA;
380 		break;
381 	case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
382 		mode = RCAR_LVDS_MODE_VESA;
383 		break;
384 	default:
385 		dev_warn(lvds->dev,
386 			 "unsupported LVDS bus format 0x%04x, using JEIDA\n",
387 			 info->bus_formats[0]);
388 		return RCAR_LVDS_MODE_JEIDA;
389 	}
390 
391 	if (info->bus_flags & DRM_BUS_FLAG_DATA_LSB_TO_MSB)
392 		mode |= RCAR_LVDS_MODE_MIRROR;
393 
394 	return mode;
395 }
396 
__rcar_lvds_atomic_enable(struct drm_bridge * bridge,struct drm_atomic_state * state,struct drm_crtc * crtc,struct drm_connector * connector)397 static void __rcar_lvds_atomic_enable(struct drm_bridge *bridge,
398 				      struct drm_atomic_state *state,
399 				      struct drm_crtc *crtc,
400 				      struct drm_connector *connector)
401 {
402 	struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
403 	u32 lvdhcr;
404 	u32 lvdcr0;
405 	int ret;
406 
407 	ret = pm_runtime_resume_and_get(lvds->dev);
408 	if (ret)
409 		return;
410 
411 	/* Enable the companion LVDS encoder in dual-link mode. */
412 	if (lvds->link_type != RCAR_LVDS_SINGLE_LINK && lvds->companion)
413 		__rcar_lvds_atomic_enable(lvds->companion, state, crtc,
414 					  connector);
415 
416 	/*
417 	 * Hardcode the channels and control signals routing for now.
418 	 *
419 	 * HSYNC -> CTRL0
420 	 * VSYNC -> CTRL1
421 	 * DISP  -> CTRL2
422 	 * 0     -> CTRL3
423 	 */
424 	rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO |
425 			LVDCTRCR_CTR2SEL_DISP | LVDCTRCR_CTR1SEL_VSYNC |
426 			LVDCTRCR_CTR0SEL_HSYNC);
427 
428 	if (lvds->info->quirks & RCAR_LVDS_QUIRK_LANES)
429 		lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 3)
430 		       | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 1);
431 	else
432 		lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 1)
433 		       | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 3);
434 
435 	rcar_lvds_write(lvds, LVDCHCR, lvdhcr);
436 
437 	if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK) {
438 		u32 lvdstripe = 0;
439 
440 		if (lvds->link_type != RCAR_LVDS_SINGLE_LINK) {
441 			/*
442 			 * By default we generate even pixels from the primary
443 			 * encoder and odd pixels from the companion encoder.
444 			 * Swap pixels around if the sink requires odd pixels
445 			 * from the primary encoder and even pixels from the
446 			 * companion encoder.
447 			 */
448 			bool swap_pixels = lvds->link_type ==
449 				RCAR_LVDS_DUAL_LINK_ODD_EVEN_PIXELS;
450 
451 			/*
452 			 * Configure vertical stripe since we are dealing with
453 			 * an LVDS dual-link connection.
454 			 *
455 			 * ST_SWAP is reserved for the companion encoder, only
456 			 * set it in the primary encoder.
457 			 */
458 			lvdstripe = LVDSTRIPE_ST_ON
459 				  | (lvds->companion && swap_pixels ?
460 				     LVDSTRIPE_ST_SWAP : 0);
461 		}
462 		rcar_lvds_write(lvds, LVDSTRIPE, lvdstripe);
463 	}
464 
465 	/*
466 	 * PLL clock configuration on all instances but the companion in
467 	 * dual-link mode.
468 	 */
469 	if (lvds->link_type == RCAR_LVDS_SINGLE_LINK || lvds->companion) {
470 		const struct drm_crtc_state *crtc_state =
471 			drm_atomic_get_new_crtc_state(state, crtc);
472 		const struct drm_display_mode *mode =
473 			&crtc_state->adjusted_mode;
474 
475 		lvds->info->pll_setup(lvds, mode->clock * 1000);
476 	}
477 
478 	/* Set the LVDS mode and select the input. */
479 	lvdcr0 = rcar_lvds_get_lvds_mode(lvds, connector) << LVDCR0_LVMD_SHIFT;
480 
481 	if (lvds->bridge.encoder) {
482 		if (drm_crtc_index(crtc) == 2)
483 			lvdcr0 |= LVDCR0_DUSEL;
484 	}
485 
486 	rcar_lvds_write(lvds, LVDCR0, lvdcr0);
487 
488 	/* Turn all the channels on. */
489 	rcar_lvds_write(lvds, LVDCR1,
490 			LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
491 			LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
492 
493 	if (lvds->info->gen < 3) {
494 		/* Enable LVDS operation and turn the bias circuitry on. */
495 		lvdcr0 |= LVDCR0_BEN | LVDCR0_LVEN;
496 		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
497 	}
498 
499 	if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
500 		/*
501 		 * Turn the PLL on (simple PLL only, extended PLL is fully
502 		 * controlled through LVDPLLCR).
503 		 */
504 		lvdcr0 |= LVDCR0_PLLON;
505 		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
506 	}
507 
508 	if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) {
509 		/* Set LVDS normal mode. */
510 		lvdcr0 |= LVDCR0_PWD;
511 		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
512 	}
513 
514 	if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) {
515 		/*
516 		 * Turn on the LVDS PHY. On D3, the LVEN and LVRES bit must be
517 		 * set at the same time, so don't write the register yet.
518 		 */
519 		lvdcr0 |= LVDCR0_LVEN;
520 		if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_PWD))
521 			rcar_lvds_write(lvds, LVDCR0, lvdcr0);
522 	}
523 
524 	if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
525 		/* Wait for the PLL startup delay (simple PLL only). */
526 		usleep_range(100, 150);
527 	}
528 
529 	/* Turn the output on. */
530 	lvdcr0 |= LVDCR0_LVRES;
531 	rcar_lvds_write(lvds, LVDCR0, lvdcr0);
532 }
533 
rcar_lvds_atomic_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)534 static void rcar_lvds_atomic_enable(struct drm_bridge *bridge,
535 				    struct drm_bridge_state *old_bridge_state)
536 {
537 	struct drm_atomic_state *state = old_bridge_state->base.state;
538 	struct drm_connector *connector;
539 	struct drm_crtc *crtc;
540 
541 	connector = drm_atomic_get_new_connector_for_encoder(state,
542 							     bridge->encoder);
543 	crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
544 
545 	__rcar_lvds_atomic_enable(bridge, state, crtc, connector);
546 }
547 
rcar_lvds_atomic_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)548 static void rcar_lvds_atomic_disable(struct drm_bridge *bridge,
549 				     struct drm_bridge_state *old_bridge_state)
550 {
551 	struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
552 	u32 lvdcr0;
553 
554 	/*
555 	 * Clear the LVDCR0 bits in the order specified by the hardware
556 	 * documentation, ending with a write of 0 to the full register to
557 	 * clear all remaining bits.
558 	 */
559 	lvdcr0 = rcar_lvds_read(lvds, LVDCR0);
560 
561 	lvdcr0 &= ~LVDCR0_LVRES;
562 	rcar_lvds_write(lvds, LVDCR0, lvdcr0);
563 
564 	if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) {
565 		lvdcr0 &= ~LVDCR0_LVEN;
566 		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
567 	}
568 
569 	if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) {
570 		lvdcr0 &= ~LVDCR0_PWD;
571 		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
572 	}
573 
574 	if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
575 		lvdcr0 &= ~LVDCR0_PLLON;
576 		rcar_lvds_write(lvds, LVDCR0, lvdcr0);
577 	}
578 
579 	rcar_lvds_write(lvds, LVDCR0, 0);
580 	rcar_lvds_write(lvds, LVDCR1, 0);
581 	rcar_lvds_write(lvds, LVDPLLCR, 0);
582 
583 	/* Disable the companion LVDS encoder in dual-link mode. */
584 	if (lvds->link_type != RCAR_LVDS_SINGLE_LINK && lvds->companion)
585 		lvds->companion->funcs->atomic_disable(lvds->companion,
586 						       old_bridge_state);
587 
588 	pm_runtime_put_sync(lvds->dev);
589 }
590 
rcar_lvds_mode_fixup(struct drm_bridge * bridge,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)591 static bool rcar_lvds_mode_fixup(struct drm_bridge *bridge,
592 				 const struct drm_display_mode *mode,
593 				 struct drm_display_mode *adjusted_mode)
594 {
595 	struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
596 	int min_freq;
597 
598 	/*
599 	 * The internal LVDS encoder has a restricted clock frequency operating
600 	 * range, from 5MHz to 148.5MHz on D3 and E3, and from 31MHz to
601 	 * 148.5MHz on all other platforms. Clamp the clock accordingly.
602 	 */
603 	min_freq = lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL ? 5000 : 31000;
604 	adjusted_mode->clock = clamp(adjusted_mode->clock, min_freq, 148500);
605 
606 	return true;
607 }
608 
rcar_lvds_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)609 static int rcar_lvds_attach(struct drm_bridge *bridge,
610 			    enum drm_bridge_attach_flags flags)
611 {
612 	struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
613 
614 	if (!lvds->next_bridge)
615 		return 0;
616 
617 	return drm_bridge_attach(bridge->encoder, lvds->next_bridge, bridge,
618 				 flags);
619 }
620 
621 static const struct drm_bridge_funcs rcar_lvds_bridge_ops = {
622 	.attach = rcar_lvds_attach,
623 	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
624 	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
625 	.atomic_reset = drm_atomic_helper_bridge_reset,
626 	.atomic_enable = rcar_lvds_atomic_enable,
627 	.atomic_disable = rcar_lvds_atomic_disable,
628 	.mode_fixup = rcar_lvds_mode_fixup,
629 };
630 
rcar_lvds_dual_link(struct drm_bridge * bridge)631 bool rcar_lvds_dual_link(struct drm_bridge *bridge)
632 {
633 	struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
634 
635 	return lvds->link_type != RCAR_LVDS_SINGLE_LINK;
636 }
637 EXPORT_SYMBOL_GPL(rcar_lvds_dual_link);
638 
rcar_lvds_is_connected(struct drm_bridge * bridge)639 bool rcar_lvds_is_connected(struct drm_bridge *bridge)
640 {
641 	struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
642 
643 	return lvds->next_bridge != NULL;
644 }
645 EXPORT_SYMBOL_GPL(rcar_lvds_is_connected);
646 
647 /* -----------------------------------------------------------------------------
648  * Probe & Remove
649  */
650 
rcar_lvds_parse_dt_companion(struct rcar_lvds * lvds)651 static int rcar_lvds_parse_dt_companion(struct rcar_lvds *lvds)
652 {
653 	const struct of_device_id *match;
654 	struct device_node *companion;
655 	struct device_node *port0, *port1;
656 	struct rcar_lvds *companion_lvds;
657 	struct device *dev = lvds->dev;
658 	int dual_link;
659 	int ret = 0;
660 
661 	/* Locate the companion LVDS encoder for dual-link operation, if any. */
662 	companion = of_parse_phandle(dev->of_node, "renesas,companion", 0);
663 	if (!companion)
664 		return 0;
665 
666 	/*
667 	 * Sanity check: the companion encoder must have the same compatible
668 	 * string.
669 	 */
670 	match = of_match_device(dev->driver->of_match_table, dev);
671 	if (!of_device_is_compatible(companion, match->compatible)) {
672 		dev_err(dev, "Companion LVDS encoder is invalid\n");
673 		ret = -ENXIO;
674 		goto done;
675 	}
676 
677 	/*
678 	 * We need to work out if the sink is expecting us to function in
679 	 * dual-link mode. We do this by looking at the DT port nodes we are
680 	 * connected to, if they are marked as expecting even pixels and
681 	 * odd pixels than we need to enable vertical stripe output.
682 	 */
683 	port0 = of_graph_get_port_by_id(dev->of_node, 1);
684 	port1 = of_graph_get_port_by_id(companion, 1);
685 	dual_link = drm_of_lvds_get_dual_link_pixel_order(port0, port1);
686 	of_node_put(port0);
687 	of_node_put(port1);
688 
689 	switch (dual_link) {
690 	case DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS:
691 		lvds->link_type = RCAR_LVDS_DUAL_LINK_ODD_EVEN_PIXELS;
692 		break;
693 	case DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS:
694 		lvds->link_type = RCAR_LVDS_DUAL_LINK_EVEN_ODD_PIXELS;
695 		break;
696 	default:
697 		/*
698 		 * Early dual-link bridge specific implementations populate the
699 		 * timings field of drm_bridge. If the flag is set, we assume
700 		 * that we are expected to generate even pixels from the primary
701 		 * encoder, and odd pixels from the companion encoder.
702 		 */
703 		if (lvds->next_bridge->timings &&
704 		    lvds->next_bridge->timings->dual_link)
705 			lvds->link_type = RCAR_LVDS_DUAL_LINK_EVEN_ODD_PIXELS;
706 		else
707 			lvds->link_type = RCAR_LVDS_SINGLE_LINK;
708 	}
709 
710 	if (lvds->link_type == RCAR_LVDS_SINGLE_LINK) {
711 		dev_dbg(dev, "Single-link configuration detected\n");
712 		goto done;
713 	}
714 
715 	lvds->companion = of_drm_find_bridge(companion);
716 	if (!lvds->companion) {
717 		ret = -EPROBE_DEFER;
718 		goto done;
719 	}
720 
721 	dev_dbg(dev,
722 		"Dual-link configuration detected (companion encoder %pOF)\n",
723 		companion);
724 
725 	if (lvds->link_type == RCAR_LVDS_DUAL_LINK_ODD_EVEN_PIXELS)
726 		dev_dbg(dev, "Data swapping required\n");
727 
728 	/*
729 	 * FIXME: We should not be messing with the companion encoder private
730 	 * data from the primary encoder, we should rather let the companion
731 	 * encoder work things out on its own. However, the companion encoder
732 	 * doesn't hold a reference to the primary encoder, and
733 	 * drm_of_lvds_get_dual_link_pixel_order needs to be given references
734 	 * to the output ports of both encoders, therefore leave it like this
735 	 * for the time being.
736 	 */
737 	companion_lvds = bridge_to_rcar_lvds(lvds->companion);
738 	companion_lvds->link_type = lvds->link_type;
739 
740 done:
741 	of_node_put(companion);
742 
743 	return ret;
744 }
745 
rcar_lvds_parse_dt(struct rcar_lvds * lvds)746 static int rcar_lvds_parse_dt(struct rcar_lvds *lvds)
747 {
748 	int ret;
749 
750 	ret = drm_of_find_panel_or_bridge(lvds->dev->of_node, 1, 0,
751 					  &lvds->panel, &lvds->next_bridge);
752 	if (ret)
753 		goto done;
754 
755 	if (lvds->panel) {
756 		lvds->next_bridge = devm_drm_panel_bridge_add(lvds->dev,
757 							      lvds->panel);
758 		if (IS_ERR_OR_NULL(lvds->next_bridge)) {
759 			ret = -EINVAL;
760 			goto done;
761 		}
762 	}
763 
764 	if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK)
765 		ret = rcar_lvds_parse_dt_companion(lvds);
766 
767 done:
768 	/*
769 	 * On D3/E3 the LVDS encoder provides a clock to the DU, which can be
770 	 * used for the DPAD output even when the LVDS output is not connected.
771 	 * Don't fail probe in that case as the DU will need the bridge to
772 	 * control the clock.
773 	 */
774 	if (lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)
775 		return ret == -ENODEV ? 0 : ret;
776 
777 	return ret;
778 }
779 
rcar_lvds_get_clock(struct rcar_lvds * lvds,const char * name,bool optional)780 static struct clk *rcar_lvds_get_clock(struct rcar_lvds *lvds, const char *name,
781 				       bool optional)
782 {
783 	struct clk *clk;
784 
785 	clk = devm_clk_get(lvds->dev, name);
786 	if (!IS_ERR(clk))
787 		return clk;
788 
789 	if (PTR_ERR(clk) == -ENOENT && optional)
790 		return NULL;
791 
792 	dev_err_probe(lvds->dev, PTR_ERR(clk), "failed to get %s clock\n",
793 		      name ? name : "module");
794 
795 	return clk;
796 }
797 
rcar_lvds_get_clocks(struct rcar_lvds * lvds)798 static int rcar_lvds_get_clocks(struct rcar_lvds *lvds)
799 {
800 	lvds->clocks.mod = rcar_lvds_get_clock(lvds, NULL, false);
801 	if (IS_ERR(lvds->clocks.mod))
802 		return PTR_ERR(lvds->clocks.mod);
803 
804 	/*
805 	 * LVDS encoders without an extended PLL have no external clock inputs.
806 	 */
807 	if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL))
808 		return 0;
809 
810 	lvds->clocks.extal = rcar_lvds_get_clock(lvds, "extal", true);
811 	if (IS_ERR(lvds->clocks.extal))
812 		return PTR_ERR(lvds->clocks.extal);
813 
814 	lvds->clocks.dotclkin[0] = rcar_lvds_get_clock(lvds, "dclkin.0", true);
815 	if (IS_ERR(lvds->clocks.dotclkin[0]))
816 		return PTR_ERR(lvds->clocks.dotclkin[0]);
817 
818 	lvds->clocks.dotclkin[1] = rcar_lvds_get_clock(lvds, "dclkin.1", true);
819 	if (IS_ERR(lvds->clocks.dotclkin[1]))
820 		return PTR_ERR(lvds->clocks.dotclkin[1]);
821 
822 	/* At least one input to the PLL must be available. */
823 	if (!lvds->clocks.extal && !lvds->clocks.dotclkin[0] &&
824 	    !lvds->clocks.dotclkin[1]) {
825 		dev_err(lvds->dev,
826 			"no input clock (extal, dclkin.0 or dclkin.1)\n");
827 		return -EINVAL;
828 	}
829 
830 	return 0;
831 }
832 
833 static const struct rcar_lvds_device_info rcar_lvds_r8a7790es1_info = {
834 	.gen = 2,
835 	.quirks = RCAR_LVDS_QUIRK_LANES,
836 	.pll_setup = rcar_lvds_pll_setup_gen2,
837 };
838 
839 static const struct soc_device_attribute lvds_quirk_matches[] = {
840 	{
841 		.soc_id = "r8a7790", .revision = "ES1.*",
842 		.data = &rcar_lvds_r8a7790es1_info,
843 	},
844 	{ /* sentinel */ }
845 };
846 
rcar_lvds_probe(struct platform_device * pdev)847 static int rcar_lvds_probe(struct platform_device *pdev)
848 {
849 	const struct soc_device_attribute *attr;
850 	struct rcar_lvds *lvds;
851 	int ret;
852 
853 	lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
854 	if (lvds == NULL)
855 		return -ENOMEM;
856 
857 	platform_set_drvdata(pdev, lvds);
858 
859 	lvds->dev = &pdev->dev;
860 	lvds->info = of_device_get_match_data(&pdev->dev);
861 
862 	attr = soc_device_match(lvds_quirk_matches);
863 	if (attr)
864 		lvds->info = attr->data;
865 
866 	ret = rcar_lvds_parse_dt(lvds);
867 	if (ret < 0)
868 		return ret;
869 
870 	lvds->bridge.funcs = &rcar_lvds_bridge_ops;
871 	lvds->bridge.of_node = pdev->dev.of_node;
872 
873 	lvds->mmio = devm_platform_ioremap_resource(pdev, 0);
874 	if (IS_ERR(lvds->mmio))
875 		return PTR_ERR(lvds->mmio);
876 
877 	ret = rcar_lvds_get_clocks(lvds);
878 	if (ret < 0)
879 		return ret;
880 
881 	lvds->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
882 	if (IS_ERR(lvds->rstc))
883 		return dev_err_probe(&pdev->dev, PTR_ERR(lvds->rstc),
884 				     "failed to get cpg reset\n");
885 
886 	pm_runtime_enable(&pdev->dev);
887 
888 	drm_bridge_add(&lvds->bridge);
889 
890 	return 0;
891 }
892 
rcar_lvds_remove(struct platform_device * pdev)893 static int rcar_lvds_remove(struct platform_device *pdev)
894 {
895 	struct rcar_lvds *lvds = platform_get_drvdata(pdev);
896 
897 	drm_bridge_remove(&lvds->bridge);
898 
899 	pm_runtime_disable(&pdev->dev);
900 
901 	return 0;
902 }
903 
904 static const struct rcar_lvds_device_info rcar_lvds_gen2_info = {
905 	.gen = 2,
906 	.pll_setup = rcar_lvds_pll_setup_gen2,
907 };
908 
909 static const struct rcar_lvds_device_info rcar_lvds_gen3_info = {
910 	.gen = 3,
911 	.quirks = RCAR_LVDS_QUIRK_PWD,
912 	.pll_setup = rcar_lvds_pll_setup_gen3,
913 };
914 
915 static const struct rcar_lvds_device_info rcar_lvds_r8a77970_info = {
916 	.gen = 3,
917 	.quirks = RCAR_LVDS_QUIRK_PWD | RCAR_LVDS_QUIRK_GEN3_LVEN,
918 	.pll_setup = rcar_lvds_pll_setup_gen2,
919 };
920 
921 static const struct rcar_lvds_device_info rcar_lvds_r8a77990_info = {
922 	.gen = 3,
923 	.quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_EXT_PLL
924 		| RCAR_LVDS_QUIRK_DUAL_LINK,
925 	.pll_setup = rcar_lvds_pll_setup_d3_e3,
926 };
927 
928 static const struct rcar_lvds_device_info rcar_lvds_r8a77995_info = {
929 	.gen = 3,
930 	.quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_PWD
931 		| RCAR_LVDS_QUIRK_EXT_PLL | RCAR_LVDS_QUIRK_DUAL_LINK,
932 	.pll_setup = rcar_lvds_pll_setup_d3_e3,
933 };
934 
935 static const struct of_device_id rcar_lvds_of_table[] = {
936 	{ .compatible = "renesas,r8a7742-lvds", .data = &rcar_lvds_gen2_info },
937 	{ .compatible = "renesas,r8a7743-lvds", .data = &rcar_lvds_gen2_info },
938 	{ .compatible = "renesas,r8a7744-lvds", .data = &rcar_lvds_gen2_info },
939 	{ .compatible = "renesas,r8a774a1-lvds", .data = &rcar_lvds_gen3_info },
940 	{ .compatible = "renesas,r8a774b1-lvds", .data = &rcar_lvds_gen3_info },
941 	{ .compatible = "renesas,r8a774c0-lvds", .data = &rcar_lvds_r8a77990_info },
942 	{ .compatible = "renesas,r8a774e1-lvds", .data = &rcar_lvds_gen3_info },
943 	{ .compatible = "renesas,r8a7790-lvds", .data = &rcar_lvds_gen2_info },
944 	{ .compatible = "renesas,r8a7791-lvds", .data = &rcar_lvds_gen2_info },
945 	{ .compatible = "renesas,r8a7793-lvds", .data = &rcar_lvds_gen2_info },
946 	{ .compatible = "renesas,r8a7795-lvds", .data = &rcar_lvds_gen3_info },
947 	{ .compatible = "renesas,r8a7796-lvds", .data = &rcar_lvds_gen3_info },
948 	{ .compatible = "renesas,r8a77961-lvds", .data = &rcar_lvds_gen3_info },
949 	{ .compatible = "renesas,r8a77965-lvds", .data = &rcar_lvds_gen3_info },
950 	{ .compatible = "renesas,r8a77970-lvds", .data = &rcar_lvds_r8a77970_info },
951 	{ .compatible = "renesas,r8a77980-lvds", .data = &rcar_lvds_gen3_info },
952 	{ .compatible = "renesas,r8a77990-lvds", .data = &rcar_lvds_r8a77990_info },
953 	{ .compatible = "renesas,r8a77995-lvds", .data = &rcar_lvds_r8a77995_info },
954 	{ }
955 };
956 
957 MODULE_DEVICE_TABLE(of, rcar_lvds_of_table);
958 
rcar_lvds_runtime_suspend(struct device * dev)959 static int rcar_lvds_runtime_suspend(struct device *dev)
960 {
961 	struct rcar_lvds *lvds = dev_get_drvdata(dev);
962 
963 	clk_disable_unprepare(lvds->clocks.mod);
964 
965 	reset_control_assert(lvds->rstc);
966 
967 	return 0;
968 }
969 
rcar_lvds_runtime_resume(struct device * dev)970 static int rcar_lvds_runtime_resume(struct device *dev)
971 {
972 	struct rcar_lvds *lvds = dev_get_drvdata(dev);
973 	int ret;
974 
975 	ret = reset_control_deassert(lvds->rstc);
976 	if (ret)
977 		return ret;
978 
979 	ret = clk_prepare_enable(lvds->clocks.mod);
980 	if (ret < 0)
981 		goto err_reset_assert;
982 
983 	return 0;
984 
985 err_reset_assert:
986 	reset_control_assert(lvds->rstc);
987 
988 	return ret;
989 }
990 
991 static const struct dev_pm_ops rcar_lvds_pm_ops = {
992 	SET_RUNTIME_PM_OPS(rcar_lvds_runtime_suspend, rcar_lvds_runtime_resume, NULL)
993 };
994 
995 static struct platform_driver rcar_lvds_platform_driver = {
996 	.probe		= rcar_lvds_probe,
997 	.remove		= rcar_lvds_remove,
998 	.driver		= {
999 		.name	= "rcar-lvds",
1000 		.pm	= &rcar_lvds_pm_ops,
1001 		.of_match_table = rcar_lvds_of_table,
1002 	},
1003 };
1004 
1005 module_platform_driver(rcar_lvds_platform_driver);
1006 
1007 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
1008 MODULE_DESCRIPTION("Renesas R-Car LVDS Encoder Driver");
1009 MODULE_LICENSE("GPL");
1010