1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * AD7190 AD7192 AD7193 AD7195 SPI ADC driver
4 *
5 * Copyright 2011-2015 Analog Devices Inc.
6 */
7
8 #include <linux/interrupt.h>
9 #include <linux/clk.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/sysfs.h>
14 #include <linux/spi/spi.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/err.h>
17 #include <linux/sched.h>
18 #include <linux/delay.h>
19 #include <linux/of_device.h>
20
21 #include <linux/iio/iio.h>
22 #include <linux/iio/sysfs.h>
23 #include <linux/iio/buffer.h>
24 #include <linux/iio/trigger.h>
25 #include <linux/iio/trigger_consumer.h>
26 #include <linux/iio/triggered_buffer.h>
27 #include <linux/iio/adc/ad_sigma_delta.h>
28
29 /* Registers */
30 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
31 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
32 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
33 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
34 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
35 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
36 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
37 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */
38 /* (AD7792)/24-bit (AD7192)) */
39 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register */
40 /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */
41
42 /* Communications Register Bit Designations (AD7192_REG_COMM) */
43 #define AD7192_COMM_WEN BIT(7) /* Write Enable */
44 #define AD7192_COMM_WRITE 0 /* Write Operation */
45 #define AD7192_COMM_READ BIT(6) /* Read Operation */
46 #define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
47 #define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */
48
49 /* Status Register Bit Designations (AD7192_REG_STAT) */
50 #define AD7192_STAT_RDY BIT(7) /* Ready */
51 #define AD7192_STAT_ERR BIT(6) /* Error (Overrange, Underrange) */
52 #define AD7192_STAT_NOREF BIT(5) /* Error no external reference */
53 #define AD7192_STAT_PARITY BIT(4) /* Parity */
54 #define AD7192_STAT_CH3 BIT(2) /* Channel 3 */
55 #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */
56 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */
57
58 /* Mode Register Bit Designations (AD7192_REG_MODE) */
59 #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */
60 #define AD7192_MODE_SEL_MASK (0x7 << 21) /* Operation Mode Select Mask */
61 #define AD7192_MODE_STA(x) (((x) & 0x1) << 20) /* Status Register transmission */
62 #define AD7192_MODE_STA_MASK BIT(20) /* Status Register transmission Mask */
63 #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */
64 #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */
65 #define AD7192_MODE_ACX BIT(14) /* AC excitation enable(AD7195 only)*/
66 #define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */
67 #define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/
68 #define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */
69 #define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */
70 #define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */
71
72 /* Mode Register: AD7192_MODE_SEL options */
73 #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */
74 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
75 #define AD7192_MODE_IDLE 2 /* Idle Mode */
76 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
77 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
78 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
79 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
80 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
81
82 /* Mode Register: AD7192_MODE_CLKSRC options */
83 #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected*/
84 /* from MCLK1 to MCLK2 */
85 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
86 #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not */
87 /* available at the MCLK2 pin */
88 #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available*/
89 /* at the MCLK2 pin */
90
91 /* Configuration Register Bit Designations (AD7192_REG_CONF) */
92
93 #define AD7192_CONF_CHOP BIT(23) /* CHOP enable */
94 #define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */
95 #define AD7192_CONF_CHAN(x) ((x) << 8) /* Channel select */
96 #define AD7192_CONF_CHAN_MASK (0x7FF << 8) /* Channel select mask */
97 #define AD7192_CONF_BURN BIT(7) /* Burnout current enable */
98 #define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */
99 #define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */
100 #define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */
101 #define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */
102
103 #define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */
104 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */
105 #define AD7192_CH_TEMP BIT(2) /* Temp Sensor */
106 #define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */
107 #define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */
108 #define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */
109 #define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */
110 #define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */
111
112 #define AD7193_CH_AIN1P_AIN2M 0x001 /* AIN1(+) - AIN2(-) */
113 #define AD7193_CH_AIN3P_AIN4M 0x002 /* AIN3(+) - AIN4(-) */
114 #define AD7193_CH_AIN5P_AIN6M 0x004 /* AIN5(+) - AIN6(-) */
115 #define AD7193_CH_AIN7P_AIN8M 0x008 /* AIN7(+) - AIN8(-) */
116 #define AD7193_CH_TEMP 0x100 /* Temp senseor */
117 #define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */
118 #define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */
119 #define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */
120 #define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */
121 #define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */
122 #define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */
123 #define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */
124 #define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */
125 #define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */
126 #define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */
127
128 /* ID Register Bit Designations (AD7192_REG_ID) */
129 #define CHIPID_AD7190 0x4
130 #define CHIPID_AD7192 0x0
131 #define CHIPID_AD7193 0x2
132 #define CHIPID_AD7195 0x6
133 #define AD7192_ID_MASK 0x0F
134
135 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */
136 #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */
137 #define AD7192_GPOCON_GP32EN BIT(5) /* Digital Output P3 and P2 enable */
138 #define AD7192_GPOCON_GP10EN BIT(4) /* Digital Output P1 and P0 enable */
139 #define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */
140 #define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */
141 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
142 #define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */
143
144 #define AD7192_EXT_FREQ_MHZ_MIN 2457600
145 #define AD7192_EXT_FREQ_MHZ_MAX 5120000
146 #define AD7192_INT_FREQ_MHZ 4915200
147
148 #define AD7192_NO_SYNC_FILTER 1
149 #define AD7192_SYNC3_FILTER 3
150 #define AD7192_SYNC4_FILTER 4
151
152 /* NOTE:
153 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
154 * In order to avoid contentions on the SPI bus, it's therefore necessary
155 * to use spi bus locking.
156 *
157 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
158 */
159
160 enum {
161 AD7192_SYSCALIB_ZERO_SCALE,
162 AD7192_SYSCALIB_FULL_SCALE,
163 };
164
165 enum {
166 ID_AD7190,
167 ID_AD7192,
168 ID_AD7193,
169 ID_AD7195,
170 };
171
172 struct ad7192_chip_info {
173 unsigned int chip_id;
174 const char *name;
175 };
176
177 struct ad7192_state {
178 const struct ad7192_chip_info *chip_info;
179 struct regulator *avdd;
180 struct clk *mclk;
181 u16 int_vref_mv;
182 u32 fclk;
183 u32 f_order;
184 u32 mode;
185 u32 conf;
186 u32 scale_avail[8][2];
187 u8 gpocon;
188 u8 clock_sel;
189 struct mutex lock; /* protect sensor state */
190 u8 syscalib_mode[8];
191
192 struct ad_sigma_delta sd;
193 };
194
195 static const char * const ad7192_syscalib_modes[] = {
196 [AD7192_SYSCALIB_ZERO_SCALE] = "zero_scale",
197 [AD7192_SYSCALIB_FULL_SCALE] = "full_scale",
198 };
199
ad7192_set_syscalib_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int mode)200 static int ad7192_set_syscalib_mode(struct iio_dev *indio_dev,
201 const struct iio_chan_spec *chan,
202 unsigned int mode)
203 {
204 struct ad7192_state *st = iio_priv(indio_dev);
205
206 st->syscalib_mode[chan->channel] = mode;
207
208 return 0;
209 }
210
ad7192_get_syscalib_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)211 static int ad7192_get_syscalib_mode(struct iio_dev *indio_dev,
212 const struct iio_chan_spec *chan)
213 {
214 struct ad7192_state *st = iio_priv(indio_dev);
215
216 return st->syscalib_mode[chan->channel];
217 }
218
ad7192_write_syscalib(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)219 static ssize_t ad7192_write_syscalib(struct iio_dev *indio_dev,
220 uintptr_t private,
221 const struct iio_chan_spec *chan,
222 const char *buf, size_t len)
223 {
224 struct ad7192_state *st = iio_priv(indio_dev);
225 bool sys_calib;
226 int ret, temp;
227
228 ret = kstrtobool(buf, &sys_calib);
229 if (ret)
230 return ret;
231
232 temp = st->syscalib_mode[chan->channel];
233 if (sys_calib) {
234 if (temp == AD7192_SYSCALIB_ZERO_SCALE)
235 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO,
236 chan->address);
237 else
238 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL,
239 chan->address);
240 }
241
242 return ret ? ret : len;
243 }
244
245 static const struct iio_enum ad7192_syscalib_mode_enum = {
246 .items = ad7192_syscalib_modes,
247 .num_items = ARRAY_SIZE(ad7192_syscalib_modes),
248 .set = ad7192_set_syscalib_mode,
249 .get = ad7192_get_syscalib_mode
250 };
251
252 static const struct iio_chan_spec_ext_info ad7192_calibsys_ext_info[] = {
253 {
254 .name = "sys_calibration",
255 .write = ad7192_write_syscalib,
256 .shared = IIO_SEPARATE,
257 },
258 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE,
259 &ad7192_syscalib_mode_enum),
260 IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE,
261 &ad7192_syscalib_mode_enum),
262 {}
263 };
264
ad_sigma_delta_to_ad7192(struct ad_sigma_delta * sd)265 static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd)
266 {
267 return container_of(sd, struct ad7192_state, sd);
268 }
269
ad7192_set_channel(struct ad_sigma_delta * sd,unsigned int channel)270 static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
271 {
272 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
273
274 st->conf &= ~AD7192_CONF_CHAN_MASK;
275 st->conf |= AD7192_CONF_CHAN(channel);
276
277 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
278 }
279
ad7192_set_mode(struct ad_sigma_delta * sd,enum ad_sigma_delta_mode mode)280 static int ad7192_set_mode(struct ad_sigma_delta *sd,
281 enum ad_sigma_delta_mode mode)
282 {
283 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
284
285 st->mode &= ~AD7192_MODE_SEL_MASK;
286 st->mode |= AD7192_MODE_SEL(mode);
287
288 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
289 }
290
ad7192_append_status(struct ad_sigma_delta * sd,bool append)291 static int ad7192_append_status(struct ad_sigma_delta *sd, bool append)
292 {
293 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
294 unsigned int mode = st->mode;
295 int ret;
296
297 mode &= ~AD7192_MODE_STA_MASK;
298 mode |= AD7192_MODE_STA(append);
299
300 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, mode);
301 if (ret < 0)
302 return ret;
303
304 st->mode = mode;
305
306 return 0;
307 }
308
ad7192_disable_all(struct ad_sigma_delta * sd)309 static int ad7192_disable_all(struct ad_sigma_delta *sd)
310 {
311 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
312 u32 conf = st->conf;
313 int ret;
314
315 conf &= ~AD7192_CONF_CHAN_MASK;
316
317 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);
318 if (ret < 0)
319 return ret;
320
321 st->conf = conf;
322
323 return 0;
324 }
325
326 static const struct ad_sigma_delta_info ad7192_sigma_delta_info = {
327 .set_channel = ad7192_set_channel,
328 .append_status = ad7192_append_status,
329 .disable_all = ad7192_disable_all,
330 .set_mode = ad7192_set_mode,
331 .has_registers = true,
332 .addr_shift = 3,
333 .read_mask = BIT(6),
334 .status_ch_mask = GENMASK(3, 0),
335 .num_slots = 4,
336 .irq_flags = IRQF_TRIGGER_FALLING,
337 };
338
339 static const struct ad_sd_calib_data ad7192_calib_arr[8] = {
340 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
341 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
342 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
343 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
344 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
345 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
346 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
347 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
348 };
349
ad7192_calibrate_all(struct ad7192_state * st)350 static int ad7192_calibrate_all(struct ad7192_state *st)
351 {
352 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr,
353 ARRAY_SIZE(ad7192_calib_arr));
354 }
355
ad7192_valid_external_frequency(u32 freq)356 static inline bool ad7192_valid_external_frequency(u32 freq)
357 {
358 return (freq >= AD7192_EXT_FREQ_MHZ_MIN &&
359 freq <= AD7192_EXT_FREQ_MHZ_MAX);
360 }
361
ad7192_of_clock_select(struct ad7192_state * st)362 static int ad7192_of_clock_select(struct ad7192_state *st)
363 {
364 struct device_node *np = st->sd.spi->dev.of_node;
365 unsigned int clock_sel;
366
367 clock_sel = AD7192_CLK_INT;
368
369 /* use internal clock */
370 if (st->mclk) {
371 if (of_property_read_bool(np, "adi,int-clock-output-enable"))
372 clock_sel = AD7192_CLK_INT_CO;
373 } else {
374 if (of_property_read_bool(np, "adi,clock-xtal"))
375 clock_sel = AD7192_CLK_EXT_MCLK1_2;
376 else
377 clock_sel = AD7192_CLK_EXT_MCLK2;
378 }
379
380 return clock_sel;
381 }
382
ad7192_setup(struct ad7192_state * st,struct device_node * np)383 static int ad7192_setup(struct ad7192_state *st, struct device_node *np)
384 {
385 struct iio_dev *indio_dev = spi_get_drvdata(st->sd.spi);
386 bool rej60_en, refin2_en;
387 bool buf_en, bipolar, burnout_curr_en;
388 unsigned long long scale_uv;
389 int i, ret, id;
390
391 /* reset the serial interface */
392 ret = ad_sd_reset(&st->sd, 48);
393 if (ret < 0)
394 return ret;
395 usleep_range(500, 1000); /* Wait for at least 500us */
396
397 /* write/read test for device presence */
398 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id);
399 if (ret)
400 return ret;
401
402 id &= AD7192_ID_MASK;
403
404 if (id != st->chip_info->chip_id)
405 dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X)\n",
406 id);
407
408 st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) |
409 AD7192_MODE_CLKSRC(st->clock_sel) |
410 AD7192_MODE_RATE(480);
411
412 st->conf = AD7192_CONF_GAIN(0);
413
414 rej60_en = of_property_read_bool(np, "adi,rejection-60-Hz-enable");
415 if (rej60_en)
416 st->mode |= AD7192_MODE_REJ60;
417
418 refin2_en = of_property_read_bool(np, "adi,refin2-pins-enable");
419 if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195)
420 st->conf |= AD7192_CONF_REFSEL;
421
422 st->conf &= ~AD7192_CONF_CHOP;
423 st->f_order = AD7192_NO_SYNC_FILTER;
424
425 buf_en = of_property_read_bool(np, "adi,buffer-enable");
426 if (buf_en)
427 st->conf |= AD7192_CONF_BUF;
428
429 bipolar = of_property_read_bool(np, "bipolar");
430 if (!bipolar)
431 st->conf |= AD7192_CONF_UNIPOLAR;
432
433 burnout_curr_en = of_property_read_bool(np,
434 "adi,burnout-currents-enable");
435 if (burnout_curr_en && buf_en) {
436 st->conf |= AD7192_CONF_BURN;
437 } else if (burnout_curr_en) {
438 dev_warn(&st->sd.spi->dev,
439 "Can't enable burnout currents: see CHOP or buffer\n");
440 }
441
442 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
443 if (ret)
444 return ret;
445
446 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
447 if (ret)
448 return ret;
449
450 ret = ad7192_calibrate_all(st);
451 if (ret)
452 return ret;
453
454 /* Populate available ADC input ranges */
455 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
456 scale_uv = ((u64)st->int_vref_mv * 100000000)
457 >> (indio_dev->channels[0].scan_type.realbits -
458 ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1));
459 scale_uv >>= i;
460
461 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
462 st->scale_avail[i][0] = scale_uv;
463 }
464
465 return 0;
466 }
467
ad7192_show_ac_excitation(struct device * dev,struct device_attribute * attr,char * buf)468 static ssize_t ad7192_show_ac_excitation(struct device *dev,
469 struct device_attribute *attr,
470 char *buf)
471 {
472 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
473 struct ad7192_state *st = iio_priv(indio_dev);
474
475 return sysfs_emit(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX));
476 }
477
ad7192_show_bridge_switch(struct device * dev,struct device_attribute * attr,char * buf)478 static ssize_t ad7192_show_bridge_switch(struct device *dev,
479 struct device_attribute *attr,
480 char *buf)
481 {
482 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
483 struct ad7192_state *st = iio_priv(indio_dev);
484
485 return sysfs_emit(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW));
486 }
487
ad7192_set(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)488 static ssize_t ad7192_set(struct device *dev,
489 struct device_attribute *attr,
490 const char *buf,
491 size_t len)
492 {
493 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
494 struct ad7192_state *st = iio_priv(indio_dev);
495 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
496 int ret;
497 bool val;
498
499 ret = kstrtobool(buf, &val);
500 if (ret < 0)
501 return ret;
502
503 ret = iio_device_claim_direct_mode(indio_dev);
504 if (ret)
505 return ret;
506
507 switch ((u32)this_attr->address) {
508 case AD7192_REG_GPOCON:
509 if (val)
510 st->gpocon |= AD7192_GPOCON_BPDSW;
511 else
512 st->gpocon &= ~AD7192_GPOCON_BPDSW;
513
514 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon);
515 break;
516 case AD7192_REG_MODE:
517 if (val)
518 st->mode |= AD7192_MODE_ACX;
519 else
520 st->mode &= ~AD7192_MODE_ACX;
521
522 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
523 break;
524 default:
525 ret = -EINVAL;
526 }
527
528 iio_device_release_direct_mode(indio_dev);
529
530 return ret ? ret : len;
531 }
532
ad7192_get_available_filter_freq(struct ad7192_state * st,int * freq)533 static void ad7192_get_available_filter_freq(struct ad7192_state *st,
534 int *freq)
535 {
536 unsigned int fadc;
537
538 /* Formulas for filter at page 25 of the datasheet */
539 fadc = DIV_ROUND_CLOSEST(st->fclk,
540 AD7192_SYNC4_FILTER * AD7192_MODE_RATE(st->mode));
541 freq[0] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
542
543 fadc = DIV_ROUND_CLOSEST(st->fclk,
544 AD7192_SYNC3_FILTER * AD7192_MODE_RATE(st->mode));
545 freq[1] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
546
547 fadc = DIV_ROUND_CLOSEST(st->fclk, AD7192_MODE_RATE(st->mode));
548 freq[2] = DIV_ROUND_CLOSEST(fadc * 230, 1024);
549 freq[3] = DIV_ROUND_CLOSEST(fadc * 272, 1024);
550 }
551
ad7192_show_filter_avail(struct device * dev,struct device_attribute * attr,char * buf)552 static ssize_t ad7192_show_filter_avail(struct device *dev,
553 struct device_attribute *attr,
554 char *buf)
555 {
556 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
557 struct ad7192_state *st = iio_priv(indio_dev);
558 unsigned int freq_avail[4], i;
559 size_t len = 0;
560
561 ad7192_get_available_filter_freq(st, freq_avail);
562
563 for (i = 0; i < ARRAY_SIZE(freq_avail); i++)
564 len += scnprintf(buf + len, PAGE_SIZE - len,
565 "%d.%d ", freq_avail[i] / 1000,
566 freq_avail[i] % 1000);
567
568 buf[len - 1] = '\n';
569
570 return len;
571 }
572
573 static IIO_DEVICE_ATTR(filter_low_pass_3db_frequency_available,
574 0444, ad7192_show_filter_avail, NULL, 0);
575
576 static IIO_DEVICE_ATTR(bridge_switch_en, 0644,
577 ad7192_show_bridge_switch, ad7192_set,
578 AD7192_REG_GPOCON);
579
580 static IIO_DEVICE_ATTR(ac_excitation_en, 0644,
581 ad7192_show_ac_excitation, ad7192_set,
582 AD7192_REG_MODE);
583
584 static struct attribute *ad7192_attributes[] = {
585 &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr,
586 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
587 &iio_dev_attr_ac_excitation_en.dev_attr.attr,
588 NULL
589 };
590
591 static const struct attribute_group ad7192_attribute_group = {
592 .attrs = ad7192_attributes,
593 };
594
595 static struct attribute *ad7195_attributes[] = {
596 &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr,
597 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
598 NULL
599 };
600
601 static const struct attribute_group ad7195_attribute_group = {
602 .attrs = ad7195_attributes,
603 };
604
ad7192_get_temp_scale(bool unipolar)605 static unsigned int ad7192_get_temp_scale(bool unipolar)
606 {
607 return unipolar ? 2815 * 2 : 2815;
608 }
609
ad7192_set_3db_filter_freq(struct ad7192_state * st,int val,int val2)610 static int ad7192_set_3db_filter_freq(struct ad7192_state *st,
611 int val, int val2)
612 {
613 int freq_avail[4], i, ret, freq;
614 unsigned int diff_new, diff_old;
615 int idx = 0;
616
617 diff_old = U32_MAX;
618 freq = val * 1000 + val2;
619
620 ad7192_get_available_filter_freq(st, freq_avail);
621
622 for (i = 0; i < ARRAY_SIZE(freq_avail); i++) {
623 diff_new = abs(freq - freq_avail[i]);
624 if (diff_new < diff_old) {
625 diff_old = diff_new;
626 idx = i;
627 }
628 }
629
630 switch (idx) {
631 case 0:
632 st->f_order = AD7192_SYNC4_FILTER;
633 st->mode &= ~AD7192_MODE_SINC3;
634
635 st->conf |= AD7192_CONF_CHOP;
636 break;
637 case 1:
638 st->f_order = AD7192_SYNC3_FILTER;
639 st->mode |= AD7192_MODE_SINC3;
640
641 st->conf |= AD7192_CONF_CHOP;
642 break;
643 case 2:
644 st->f_order = AD7192_NO_SYNC_FILTER;
645 st->mode &= ~AD7192_MODE_SINC3;
646
647 st->conf &= ~AD7192_CONF_CHOP;
648 break;
649 case 3:
650 st->f_order = AD7192_NO_SYNC_FILTER;
651 st->mode |= AD7192_MODE_SINC3;
652
653 st->conf &= ~AD7192_CONF_CHOP;
654 break;
655 }
656
657 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
658 if (ret < 0)
659 return ret;
660
661 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
662 }
663
ad7192_get_3db_filter_freq(struct ad7192_state * st)664 static int ad7192_get_3db_filter_freq(struct ad7192_state *st)
665 {
666 unsigned int fadc;
667
668 fadc = DIV_ROUND_CLOSEST(st->fclk,
669 st->f_order * AD7192_MODE_RATE(st->mode));
670
671 if (st->conf & AD7192_CONF_CHOP)
672 return DIV_ROUND_CLOSEST(fadc * 240, 1024);
673 if (st->mode & AD7192_MODE_SINC3)
674 return DIV_ROUND_CLOSEST(fadc * 272, 1024);
675 else
676 return DIV_ROUND_CLOSEST(fadc * 230, 1024);
677 }
678
ad7192_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)679 static int ad7192_read_raw(struct iio_dev *indio_dev,
680 struct iio_chan_spec const *chan,
681 int *val,
682 int *val2,
683 long m)
684 {
685 struct ad7192_state *st = iio_priv(indio_dev);
686 bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR);
687
688 switch (m) {
689 case IIO_CHAN_INFO_RAW:
690 return ad_sigma_delta_single_conversion(indio_dev, chan, val);
691 case IIO_CHAN_INFO_SCALE:
692 switch (chan->type) {
693 case IIO_VOLTAGE:
694 mutex_lock(&st->lock);
695 *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0];
696 *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1];
697 mutex_unlock(&st->lock);
698 return IIO_VAL_INT_PLUS_NANO;
699 case IIO_TEMP:
700 *val = 0;
701 *val2 = 1000000000 / ad7192_get_temp_scale(unipolar);
702 return IIO_VAL_INT_PLUS_NANO;
703 default:
704 return -EINVAL;
705 }
706 case IIO_CHAN_INFO_OFFSET:
707 if (!unipolar)
708 *val = -(1 << (chan->scan_type.realbits - 1));
709 else
710 *val = 0;
711 /* Kelvin to Celsius */
712 if (chan->type == IIO_TEMP)
713 *val -= 273 * ad7192_get_temp_scale(unipolar);
714 return IIO_VAL_INT;
715 case IIO_CHAN_INFO_SAMP_FREQ:
716 *val = st->fclk /
717 (st->f_order * 1024 * AD7192_MODE_RATE(st->mode));
718 return IIO_VAL_INT;
719 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
720 *val = ad7192_get_3db_filter_freq(st);
721 *val2 = 1000;
722 return IIO_VAL_FRACTIONAL;
723 }
724
725 return -EINVAL;
726 }
727
ad7192_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)728 static int ad7192_write_raw(struct iio_dev *indio_dev,
729 struct iio_chan_spec const *chan,
730 int val,
731 int val2,
732 long mask)
733 {
734 struct ad7192_state *st = iio_priv(indio_dev);
735 int ret, i, div;
736 unsigned int tmp;
737
738 ret = iio_device_claim_direct_mode(indio_dev);
739 if (ret)
740 return ret;
741
742 switch (mask) {
743 case IIO_CHAN_INFO_SCALE:
744 ret = -EINVAL;
745 mutex_lock(&st->lock);
746 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
747 if (val2 == st->scale_avail[i][1]) {
748 ret = 0;
749 tmp = st->conf;
750 st->conf &= ~AD7192_CONF_GAIN(-1);
751 st->conf |= AD7192_CONF_GAIN(i);
752 if (tmp == st->conf)
753 break;
754 ad_sd_write_reg(&st->sd, AD7192_REG_CONF,
755 3, st->conf);
756 ad7192_calibrate_all(st);
757 break;
758 }
759 mutex_unlock(&st->lock);
760 break;
761 case IIO_CHAN_INFO_SAMP_FREQ:
762 if (!val) {
763 ret = -EINVAL;
764 break;
765 }
766
767 div = st->fclk / (val * st->f_order * 1024);
768 if (div < 1 || div > 1023) {
769 ret = -EINVAL;
770 break;
771 }
772
773 st->mode &= ~AD7192_MODE_RATE(-1);
774 st->mode |= AD7192_MODE_RATE(div);
775 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
776 break;
777 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
778 ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000);
779 break;
780 default:
781 ret = -EINVAL;
782 }
783
784 iio_device_release_direct_mode(indio_dev);
785
786 return ret;
787 }
788
ad7192_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)789 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
790 struct iio_chan_spec const *chan,
791 long mask)
792 {
793 switch (mask) {
794 case IIO_CHAN_INFO_SCALE:
795 return IIO_VAL_INT_PLUS_NANO;
796 case IIO_CHAN_INFO_SAMP_FREQ:
797 return IIO_VAL_INT;
798 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
799 return IIO_VAL_INT_PLUS_MICRO;
800 default:
801 return -EINVAL;
802 }
803 }
804
ad7192_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)805 static int ad7192_read_avail(struct iio_dev *indio_dev,
806 struct iio_chan_spec const *chan,
807 const int **vals, int *type, int *length,
808 long mask)
809 {
810 struct ad7192_state *st = iio_priv(indio_dev);
811
812 switch (mask) {
813 case IIO_CHAN_INFO_SCALE:
814 *vals = (int *)st->scale_avail;
815 *type = IIO_VAL_INT_PLUS_NANO;
816 /* Values are stored in a 2D matrix */
817 *length = ARRAY_SIZE(st->scale_avail) * 2;
818
819 return IIO_AVAIL_LIST;
820 }
821
822 return -EINVAL;
823 }
824
ad7192_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)825 static int ad7192_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask)
826 {
827 struct ad7192_state *st = iio_priv(indio_dev);
828 u32 conf = st->conf;
829 int ret;
830 int i;
831
832 conf &= ~AD7192_CONF_CHAN_MASK;
833 for_each_set_bit(i, scan_mask, 8)
834 conf |= AD7192_CONF_CHAN(i);
835
836 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);
837 if (ret < 0)
838 return ret;
839
840 st->conf = conf;
841
842 return 0;
843 }
844
845 static const struct iio_info ad7192_info = {
846 .read_raw = ad7192_read_raw,
847 .write_raw = ad7192_write_raw,
848 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
849 .read_avail = ad7192_read_avail,
850 .attrs = &ad7192_attribute_group,
851 .validate_trigger = ad_sd_validate_trigger,
852 .update_scan_mode = ad7192_update_scan_mode,
853 };
854
855 static const struct iio_info ad7195_info = {
856 .read_raw = ad7192_read_raw,
857 .write_raw = ad7192_write_raw,
858 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
859 .read_avail = ad7192_read_avail,
860 .attrs = &ad7195_attribute_group,
861 .validate_trigger = ad_sd_validate_trigger,
862 .update_scan_mode = ad7192_update_scan_mode,
863 };
864
865 #define __AD719x_CHANNEL(_si, _channel1, _channel2, _address, _extend_name, \
866 _type, _mask_type_av, _ext_info) \
867 { \
868 .type = (_type), \
869 .differential = ((_channel2) == -1 ? 0 : 1), \
870 .indexed = 1, \
871 .channel = (_channel1), \
872 .channel2 = (_channel2), \
873 .address = (_address), \
874 .extend_name = (_extend_name), \
875 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
876 BIT(IIO_CHAN_INFO_OFFSET), \
877 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
878 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
879 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
880 .info_mask_shared_by_type_available = (_mask_type_av), \
881 .ext_info = (_ext_info), \
882 .scan_index = (_si), \
883 .scan_type = { \
884 .sign = 'u', \
885 .realbits = 24, \
886 .storagebits = 32, \
887 .endianness = IIO_BE, \
888 }, \
889 }
890
891 #define AD719x_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \
892 __AD719x_CHANNEL(_si, _channel1, _channel2, _address, NULL, \
893 IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE), \
894 ad7192_calibsys_ext_info)
895
896 #define AD719x_CHANNEL(_si, _channel1, _address) \
897 __AD719x_CHANNEL(_si, _channel1, -1, _address, NULL, IIO_VOLTAGE, \
898 BIT(IIO_CHAN_INFO_SCALE), ad7192_calibsys_ext_info)
899
900 #define AD719x_SHORTED_CHANNEL(_si, _channel1, _address) \
901 __AD719x_CHANNEL(_si, _channel1, -1, _address, "shorted", IIO_VOLTAGE, \
902 BIT(IIO_CHAN_INFO_SCALE), ad7192_calibsys_ext_info)
903
904 #define AD719x_TEMP_CHANNEL(_si, _address) \
905 __AD719x_CHANNEL(_si, 0, -1, _address, NULL, IIO_TEMP, 0, NULL)
906
907 static const struct iio_chan_spec ad7192_channels[] = {
908 AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M),
909 AD719x_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M),
910 AD719x_TEMP_CHANNEL(2, AD7192_CH_TEMP),
911 AD719x_SHORTED_CHANNEL(3, 2, AD7192_CH_AIN2P_AIN2M),
912 AD719x_CHANNEL(4, 1, AD7192_CH_AIN1),
913 AD719x_CHANNEL(5, 2, AD7192_CH_AIN2),
914 AD719x_CHANNEL(6, 3, AD7192_CH_AIN3),
915 AD719x_CHANNEL(7, 4, AD7192_CH_AIN4),
916 IIO_CHAN_SOFT_TIMESTAMP(8),
917 };
918
919 static const struct iio_chan_spec ad7193_channels[] = {
920 AD719x_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M),
921 AD719x_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M),
922 AD719x_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M),
923 AD719x_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M),
924 AD719x_TEMP_CHANNEL(4, AD7193_CH_TEMP),
925 AD719x_SHORTED_CHANNEL(5, 2, AD7193_CH_AIN2P_AIN2M),
926 AD719x_CHANNEL(6, 1, AD7193_CH_AIN1),
927 AD719x_CHANNEL(7, 2, AD7193_CH_AIN2),
928 AD719x_CHANNEL(8, 3, AD7193_CH_AIN3),
929 AD719x_CHANNEL(9, 4, AD7193_CH_AIN4),
930 AD719x_CHANNEL(10, 5, AD7193_CH_AIN5),
931 AD719x_CHANNEL(11, 6, AD7193_CH_AIN6),
932 AD719x_CHANNEL(12, 7, AD7193_CH_AIN7),
933 AD719x_CHANNEL(13, 8, AD7193_CH_AIN8),
934 IIO_CHAN_SOFT_TIMESTAMP(14),
935 };
936
937 static const struct ad7192_chip_info ad7192_chip_info_tbl[] = {
938 [ID_AD7190] = {
939 .chip_id = CHIPID_AD7190,
940 .name = "ad7190",
941 },
942 [ID_AD7192] = {
943 .chip_id = CHIPID_AD7192,
944 .name = "ad7192",
945 },
946 [ID_AD7193] = {
947 .chip_id = CHIPID_AD7193,
948 .name = "ad7193",
949 },
950 [ID_AD7195] = {
951 .chip_id = CHIPID_AD7195,
952 .name = "ad7195",
953 },
954 };
955
ad7192_channels_config(struct iio_dev * indio_dev)956 static int ad7192_channels_config(struct iio_dev *indio_dev)
957 {
958 struct ad7192_state *st = iio_priv(indio_dev);
959
960 switch (st->chip_info->chip_id) {
961 case CHIPID_AD7193:
962 indio_dev->channels = ad7193_channels;
963 indio_dev->num_channels = ARRAY_SIZE(ad7193_channels);
964 break;
965 default:
966 indio_dev->channels = ad7192_channels;
967 indio_dev->num_channels = ARRAY_SIZE(ad7192_channels);
968 break;
969 }
970
971 return 0;
972 }
973
ad7192_reg_disable(void * reg)974 static void ad7192_reg_disable(void *reg)
975 {
976 regulator_disable(reg);
977 }
978
ad7192_clk_disable(void * clk)979 static void ad7192_clk_disable(void *clk)
980 {
981 clk_disable_unprepare(clk);
982 }
983
ad7192_probe(struct spi_device * spi)984 static int ad7192_probe(struct spi_device *spi)
985 {
986 struct ad7192_state *st;
987 struct iio_dev *indio_dev;
988 int ret;
989
990 if (!spi->irq) {
991 dev_err(&spi->dev, "no IRQ?\n");
992 return -ENODEV;
993 }
994
995 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
996 if (!indio_dev)
997 return -ENOMEM;
998
999 st = iio_priv(indio_dev);
1000
1001 mutex_init(&st->lock);
1002
1003 st->avdd = devm_regulator_get(&spi->dev, "avdd");
1004 if (IS_ERR(st->avdd))
1005 return PTR_ERR(st->avdd);
1006
1007 ret = regulator_enable(st->avdd);
1008 if (ret) {
1009 dev_err(&spi->dev, "Failed to enable specified AVdd supply\n");
1010 return ret;
1011 }
1012
1013 ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->avdd);
1014 if (ret)
1015 return ret;
1016
1017 ret = devm_regulator_get_enable(&spi->dev, "dvdd");
1018 if (ret)
1019 return dev_err_probe(&spi->dev, ret, "Failed to enable specified DVdd supply\n");
1020
1021 ret = regulator_get_voltage(st->avdd);
1022 if (ret < 0) {
1023 dev_err(&spi->dev, "Device tree error, reference voltage undefined\n");
1024 return ret;
1025 }
1026 st->int_vref_mv = ret / 1000;
1027
1028 st->chip_info = of_device_get_match_data(&spi->dev);
1029 if (!st->chip_info)
1030 st->chip_info = (void *)spi_get_device_id(spi)->driver_data;
1031 indio_dev->name = st->chip_info->name;
1032 indio_dev->modes = INDIO_DIRECT_MODE;
1033
1034 ret = ad7192_channels_config(indio_dev);
1035 if (ret < 0)
1036 return ret;
1037
1038 if (st->chip_info->chip_id == CHIPID_AD7195)
1039 indio_dev->info = &ad7195_info;
1040 else
1041 indio_dev->info = &ad7192_info;
1042
1043 ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info);
1044
1045 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev);
1046 if (ret)
1047 return ret;
1048
1049 st->fclk = AD7192_INT_FREQ_MHZ;
1050
1051 st->mclk = devm_clk_get_optional(&spi->dev, "mclk");
1052 if (IS_ERR(st->mclk))
1053 return PTR_ERR(st->mclk);
1054
1055 st->clock_sel = ad7192_of_clock_select(st);
1056
1057 if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 ||
1058 st->clock_sel == AD7192_CLK_EXT_MCLK2) {
1059 ret = clk_prepare_enable(st->mclk);
1060 if (ret < 0)
1061 return ret;
1062
1063 ret = devm_add_action_or_reset(&spi->dev, ad7192_clk_disable,
1064 st->mclk);
1065 if (ret)
1066 return ret;
1067
1068 st->fclk = clk_get_rate(st->mclk);
1069 if (!ad7192_valid_external_frequency(st->fclk)) {
1070 dev_err(&spi->dev,
1071 "External clock frequency out of bounds\n");
1072 return -EINVAL;
1073 }
1074 }
1075
1076 ret = ad7192_setup(st, spi->dev.of_node);
1077 if (ret)
1078 return ret;
1079
1080 return devm_iio_device_register(&spi->dev, indio_dev);
1081 }
1082
1083 static const struct of_device_id ad7192_of_match[] = {
1084 { .compatible = "adi,ad7190", .data = &ad7192_chip_info_tbl[ID_AD7190] },
1085 { .compatible = "adi,ad7192", .data = &ad7192_chip_info_tbl[ID_AD7192] },
1086 { .compatible = "adi,ad7193", .data = &ad7192_chip_info_tbl[ID_AD7193] },
1087 { .compatible = "adi,ad7195", .data = &ad7192_chip_info_tbl[ID_AD7195] },
1088 {}
1089 };
1090 MODULE_DEVICE_TABLE(of, ad7192_of_match);
1091
1092 static const struct spi_device_id ad7192_ids[] = {
1093 { "ad7190", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7190] },
1094 { "ad7192", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7192] },
1095 { "ad7193", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7193] },
1096 { "ad7195", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7195] },
1097 {}
1098 };
1099 MODULE_DEVICE_TABLE(spi, ad7192_ids);
1100
1101 static struct spi_driver ad7192_driver = {
1102 .driver = {
1103 .name = "ad7192",
1104 .of_match_table = ad7192_of_match,
1105 },
1106 .probe = ad7192_probe,
1107 .id_table = ad7192_ids,
1108 };
1109 module_spi_driver(ad7192_driver);
1110
1111 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
1112 MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7193, AD7195 ADC");
1113 MODULE_LICENSE("GPL v2");
1114 MODULE_IMPORT_NS(IIO_AD_SIGMA_DELTA);
1115