1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
4 *
5 * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
12 #include <linux/io.h>
13 #include <linux/iio/iio.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
16 #include <linux/nvmem-consumer.h>
17 #include <linux/interrupt.h>
18 #include <linux/of.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/regmap.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/mfd/syscon.h>
25
26 #define MESON_SAR_ADC_REG0 0x00
27 #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31)
28 #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
29 #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30)
30 #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29)
31 #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
32 #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27)
33 #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26)
34 #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
35 #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
36 #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
37 #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
38 #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14)
39 #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
40 #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
41 #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
42 #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
43 #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
44 #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2)
45 #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
46 #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
47
48 #define MESON_SAR_ADC_CHAN_LIST 0x04
49 #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
50 #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \
51 (GENMASK(2, 0) << ((_chan) * 3))
52
53 #define MESON_SAR_ADC_AVG_CNTL 0x08
54 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
55 (16 + ((_chan) * 2))
56 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
57 (GENMASK(17, 16) << ((_chan) * 2))
58 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
59 (0 + ((_chan) * 2))
60 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
61 (GENMASK(1, 0) << ((_chan) * 2))
62
63 #define MESON_SAR_ADC_REG3 0x0c
64 #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
65 #define MESON_SAR_ADC_REG3_CLK_EN BIT(30)
66 #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
67 #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
68 #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
69 #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
70 #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22)
71 #define MESON_SAR_ADC_REG3_ADC_EN BIT(21)
72 #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
73 #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
74 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
75 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
76 #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
77 #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
78
79 #define MESON_SAR_ADC_DELAY 0x10
80 #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
81 #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15)
82 #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
83 #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
84 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
85 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
86
87 #define MESON_SAR_ADC_LAST_RD 0x14
88 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
89 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
90
91 #define MESON_SAR_ADC_FIFO_RD 0x18
92 #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
93 #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
94
95 #define MESON_SAR_ADC_AUX_SW 0x1c
96 #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(_chan) \
97 (8 + (((_chan) - 2) * 3))
98 #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
99 #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
100 #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4)
101 #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
102 #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
103 #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
104 #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
105
106 #define MESON_SAR_ADC_CHAN_10_SW 0x20
107 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
108 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
109 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
110 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
111 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
112 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
113 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
114 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
115 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
116 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
117 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
118 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
119 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
120 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
121 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
122 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
123
124 #define MESON_SAR_ADC_DETECT_IDLE_SW 0x24
125 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
126 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23)
127 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22)
128 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21)
129 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
130 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19)
131 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18)
132 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17)
133 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16)
134 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7)
135 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6)
136 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5)
137 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
138 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3)
139 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2)
140 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1)
141 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0)
142
143 #define MESON_SAR_ADC_DELTA_10 0x28
144 #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
145 #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
146 #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
147 #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
148 #define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
149 #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
150 #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
151
152 /*
153 * NOTE: registers from here are undocumented (the vendor Linux kernel driver
154 * and u-boot source served as reference). These only seem to be relevant on
155 * GXBB and newer.
156 */
157 #define MESON_SAR_ADC_REG11 0x2c
158 #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13)
159
160 #define MESON_SAR_ADC_REG13 0x34
161 #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
162
163 #define MESON_SAR_ADC_MAX_FIFO_SIZE 32
164 #define MESON_SAR_ADC_TIMEOUT 100 /* ms */
165 #define MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL 6
166 #define MESON_SAR_ADC_TEMP_OFFSET 27
167
168 /* temperature sensor calibration information in eFuse */
169 #define MESON_SAR_ADC_EFUSE_BYTES 4
170 #define MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL GENMASK(6, 0)
171 #define MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED BIT(7)
172
173 #define MESON_HHI_DPLL_TOP_0 0x318
174 #define MESON_HHI_DPLL_TOP_0_TSC_BIT4 BIT(9)
175
176 /* for use with IIO_VAL_INT_PLUS_MICRO */
177 #define MILLION 1000000
178
179 #define MESON_SAR_ADC_CHAN(_chan) { \
180 .type = IIO_VOLTAGE, \
181 .indexed = 1, \
182 .channel = _chan, \
183 .address = _chan, \
184 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
185 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
186 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
187 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \
188 BIT(IIO_CHAN_INFO_CALIBSCALE), \
189 .datasheet_name = "SAR_ADC_CH"#_chan, \
190 }
191
192 #define MESON_SAR_ADC_TEMP_CHAN(_chan) { \
193 .type = IIO_TEMP, \
194 .channel = _chan, \
195 .address = MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL, \
196 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
197 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
198 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | \
199 BIT(IIO_CHAN_INFO_SCALE), \
200 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \
201 BIT(IIO_CHAN_INFO_CALIBSCALE), \
202 .datasheet_name = "TEMP_SENSOR", \
203 }
204
205 static const struct iio_chan_spec meson_sar_adc_iio_channels[] = {
206 MESON_SAR_ADC_CHAN(0),
207 MESON_SAR_ADC_CHAN(1),
208 MESON_SAR_ADC_CHAN(2),
209 MESON_SAR_ADC_CHAN(3),
210 MESON_SAR_ADC_CHAN(4),
211 MESON_SAR_ADC_CHAN(5),
212 MESON_SAR_ADC_CHAN(6),
213 MESON_SAR_ADC_CHAN(7),
214 IIO_CHAN_SOFT_TIMESTAMP(8),
215 };
216
217 static const struct iio_chan_spec meson_sar_adc_and_temp_iio_channels[] = {
218 MESON_SAR_ADC_CHAN(0),
219 MESON_SAR_ADC_CHAN(1),
220 MESON_SAR_ADC_CHAN(2),
221 MESON_SAR_ADC_CHAN(3),
222 MESON_SAR_ADC_CHAN(4),
223 MESON_SAR_ADC_CHAN(5),
224 MESON_SAR_ADC_CHAN(6),
225 MESON_SAR_ADC_CHAN(7),
226 MESON_SAR_ADC_TEMP_CHAN(8),
227 IIO_CHAN_SOFT_TIMESTAMP(9),
228 };
229
230 enum meson_sar_adc_avg_mode {
231 NO_AVERAGING = 0x0,
232 MEAN_AVERAGING = 0x1,
233 MEDIAN_AVERAGING = 0x2,
234 };
235
236 enum meson_sar_adc_num_samples {
237 ONE_SAMPLE = 0x0,
238 TWO_SAMPLES = 0x1,
239 FOUR_SAMPLES = 0x2,
240 EIGHT_SAMPLES = 0x3,
241 };
242
243 enum meson_sar_adc_chan7_mux_sel {
244 CHAN7_MUX_VSS = 0x0,
245 CHAN7_MUX_VDD_DIV4 = 0x1,
246 CHAN7_MUX_VDD_DIV2 = 0x2,
247 CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
248 CHAN7_MUX_VDD = 0x4,
249 CHAN7_MUX_CH7_INPUT = 0x7,
250 };
251
252 struct meson_sar_adc_param {
253 bool has_bl30_integration;
254 unsigned long clock_rate;
255 u32 bandgap_reg;
256 unsigned int resolution;
257 const struct regmap_config *regmap_config;
258 u8 temperature_trimming_bits;
259 unsigned int temperature_multiplier;
260 unsigned int temperature_divider;
261 };
262
263 struct meson_sar_adc_data {
264 const struct meson_sar_adc_param *param;
265 const char *name;
266 };
267
268 struct meson_sar_adc_priv {
269 struct regmap *regmap;
270 struct regulator *vref;
271 const struct meson_sar_adc_param *param;
272 struct clk *clkin;
273 struct clk *core_clk;
274 struct clk *adc_sel_clk;
275 struct clk *adc_clk;
276 struct clk_gate clk_gate;
277 struct clk *adc_div_clk;
278 struct clk_divider clk_div;
279 struct completion done;
280 /* lock to protect against multiple access to the device */
281 struct mutex lock;
282 int calibbias;
283 int calibscale;
284 struct regmap *tsc_regmap;
285 bool temperature_sensor_calibrated;
286 u8 temperature_sensor_coefficient;
287 u16 temperature_sensor_adc_val;
288 };
289
290 static const struct regmap_config meson_sar_adc_regmap_config_gxbb = {
291 .reg_bits = 8,
292 .val_bits = 32,
293 .reg_stride = 4,
294 .max_register = MESON_SAR_ADC_REG13,
295 };
296
297 static const struct regmap_config meson_sar_adc_regmap_config_meson8 = {
298 .reg_bits = 8,
299 .val_bits = 32,
300 .reg_stride = 4,
301 .max_register = MESON_SAR_ADC_DELTA_10,
302 };
303
meson_sar_adc_get_fifo_count(struct iio_dev * indio_dev)304 static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev)
305 {
306 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
307 u32 regval;
308
309 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
310
311 return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
312 }
313
meson_sar_adc_calib_val(struct iio_dev * indio_dev,int val)314 static int meson_sar_adc_calib_val(struct iio_dev *indio_dev, int val)
315 {
316 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
317 int tmp;
318
319 /* use val_calib = scale * val_raw + offset calibration function */
320 tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias;
321
322 return clamp(tmp, 0, (1 << priv->param->resolution) - 1);
323 }
324
meson_sar_adc_wait_busy_clear(struct iio_dev * indio_dev)325 static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev)
326 {
327 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
328 int val;
329
330 /*
331 * NOTE: we need a small delay before reading the status, otherwise
332 * the sample engine may not have started internally (which would
333 * seem to us that sampling is already finished).
334 */
335 udelay(1);
336 return regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_REG0, val,
337 !FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, val),
338 1, 10000);
339 }
340
meson_sar_adc_read_raw_sample(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val)341 static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev,
342 const struct iio_chan_spec *chan,
343 int *val)
344 {
345 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
346 struct device *dev = indio_dev->dev.parent;
347 int regval, fifo_chan, fifo_val, count;
348
349 if (!wait_for_completion_timeout(&priv->done,
350 msecs_to_jiffies(MESON_SAR_ADC_TIMEOUT)))
351 return -ETIMEDOUT;
352
353 count = meson_sar_adc_get_fifo_count(indio_dev);
354 if (count != 1) {
355 dev_err(dev, "ADC FIFO has %d element(s) instead of one\n", count);
356 return -EINVAL;
357 }
358
359 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val);
360 fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
361 if (fifo_chan != chan->address) {
362 dev_err(dev, "ADC FIFO entry belongs to channel %d instead of %lu\n",
363 fifo_chan, chan->address);
364 return -EINVAL;
365 }
366
367 fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval);
368 fifo_val &= GENMASK(priv->param->resolution - 1, 0);
369 *val = meson_sar_adc_calib_val(indio_dev, fifo_val);
370
371 return 0;
372 }
373
meson_sar_adc_set_averaging(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum meson_sar_adc_avg_mode mode,enum meson_sar_adc_num_samples samples)374 static void meson_sar_adc_set_averaging(struct iio_dev *indio_dev,
375 const struct iio_chan_spec *chan,
376 enum meson_sar_adc_avg_mode mode,
377 enum meson_sar_adc_num_samples samples)
378 {
379 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
380 int val, address = chan->address;
381
382 val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(address);
383 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
384 MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(address),
385 val);
386
387 val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(address);
388 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
389 MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(address), val);
390 }
391
meson_sar_adc_enable_channel(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)392 static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev,
393 const struct iio_chan_spec *chan)
394 {
395 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
396 u32 regval;
397
398 /*
399 * the SAR ADC engine allows sampling multiple channels at the same
400 * time. to keep it simple we're only working with one *internal*
401 * channel, which starts counting at index 0 (which means: count = 1).
402 */
403 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
404 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
405 MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
406
407 /* map channel index 0 to the channel which we want to read */
408 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0),
409 chan->address);
410 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
411 MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);
412
413 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
414 chan->address);
415 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
416 MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
417 regval);
418
419 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
420 chan->address);
421 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
422 MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
423 regval);
424
425 if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL) {
426 if (chan->type == IIO_TEMP)
427 regval = MESON_SAR_ADC_DELTA_10_TEMP_SEL;
428 else
429 regval = 0;
430
431 regmap_update_bits(priv->regmap,
432 MESON_SAR_ADC_DELTA_10,
433 MESON_SAR_ADC_DELTA_10_TEMP_SEL, regval);
434 }
435 }
436
meson_sar_adc_set_chan7_mux(struct iio_dev * indio_dev,enum meson_sar_adc_chan7_mux_sel sel)437 static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev,
438 enum meson_sar_adc_chan7_mux_sel sel)
439 {
440 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
441 u32 regval;
442
443 regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
444 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
445 MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
446
447 usleep_range(10, 20);
448 }
449
meson_sar_adc_start_sample_engine(struct iio_dev * indio_dev)450 static void meson_sar_adc_start_sample_engine(struct iio_dev *indio_dev)
451 {
452 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
453
454 reinit_completion(&priv->done);
455
456 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
457 MESON_SAR_ADC_REG0_FIFO_IRQ_EN,
458 MESON_SAR_ADC_REG0_FIFO_IRQ_EN);
459
460 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
461 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
462 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
463
464 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
465 MESON_SAR_ADC_REG0_SAMPLING_START,
466 MESON_SAR_ADC_REG0_SAMPLING_START);
467 }
468
meson_sar_adc_stop_sample_engine(struct iio_dev * indio_dev)469 static void meson_sar_adc_stop_sample_engine(struct iio_dev *indio_dev)
470 {
471 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
472
473 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
474 MESON_SAR_ADC_REG0_FIFO_IRQ_EN, 0);
475
476 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
477 MESON_SAR_ADC_REG0_SAMPLING_STOP,
478 MESON_SAR_ADC_REG0_SAMPLING_STOP);
479
480 /* wait until all modules are stopped */
481 meson_sar_adc_wait_busy_clear(indio_dev);
482
483 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
484 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
485 }
486
meson_sar_adc_lock(struct iio_dev * indio_dev)487 static int meson_sar_adc_lock(struct iio_dev *indio_dev)
488 {
489 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
490 int val, ret;
491
492 mutex_lock(&priv->lock);
493
494 if (priv->param->has_bl30_integration) {
495 /* prevent BL30 from using the SAR ADC while we are using it */
496 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
497 MESON_SAR_ADC_DELAY_KERNEL_BUSY,
498 MESON_SAR_ADC_DELAY_KERNEL_BUSY);
499
500 udelay(1);
501
502 /*
503 * wait until BL30 releases it's lock (so we can use the SAR
504 * ADC)
505 */
506 ret = regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_DELAY, val,
507 !(val & MESON_SAR_ADC_DELAY_BL30_BUSY),
508 1, 10000);
509 if (ret) {
510 mutex_unlock(&priv->lock);
511 return ret;
512 }
513 }
514
515 return 0;
516 }
517
meson_sar_adc_unlock(struct iio_dev * indio_dev)518 static void meson_sar_adc_unlock(struct iio_dev *indio_dev)
519 {
520 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
521
522 if (priv->param->has_bl30_integration)
523 /* allow BL30 to use the SAR ADC again */
524 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
525 MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0);
526
527 mutex_unlock(&priv->lock);
528 }
529
meson_sar_adc_clear_fifo(struct iio_dev * indio_dev)530 static void meson_sar_adc_clear_fifo(struct iio_dev *indio_dev)
531 {
532 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
533 unsigned int count, tmp;
534
535 for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {
536 if (!meson_sar_adc_get_fifo_count(indio_dev))
537 break;
538
539 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp);
540 }
541 }
542
meson_sar_adc_get_sample(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum meson_sar_adc_avg_mode avg_mode,enum meson_sar_adc_num_samples avg_samples,int * val)543 static int meson_sar_adc_get_sample(struct iio_dev *indio_dev,
544 const struct iio_chan_spec *chan,
545 enum meson_sar_adc_avg_mode avg_mode,
546 enum meson_sar_adc_num_samples avg_samples,
547 int *val)
548 {
549 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
550 struct device *dev = indio_dev->dev.parent;
551 int ret;
552
553 if (chan->type == IIO_TEMP && !priv->temperature_sensor_calibrated)
554 return -ENOTSUPP;
555
556 ret = meson_sar_adc_lock(indio_dev);
557 if (ret)
558 return ret;
559
560 /* clear the FIFO to make sure we're not reading old values */
561 meson_sar_adc_clear_fifo(indio_dev);
562
563 meson_sar_adc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
564
565 meson_sar_adc_enable_channel(indio_dev, chan);
566
567 meson_sar_adc_start_sample_engine(indio_dev);
568 ret = meson_sar_adc_read_raw_sample(indio_dev, chan, val);
569 meson_sar_adc_stop_sample_engine(indio_dev);
570
571 meson_sar_adc_unlock(indio_dev);
572
573 if (ret) {
574 dev_warn(dev, "failed to read sample for channel %lu: %d\n",
575 chan->address, ret);
576 return ret;
577 }
578
579 return IIO_VAL_INT;
580 }
581
meson_sar_adc_iio_info_read_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long mask)582 static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev,
583 const struct iio_chan_spec *chan,
584 int *val, int *val2, long mask)
585 {
586 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
587 struct device *dev = indio_dev->dev.parent;
588 int ret;
589
590 switch (mask) {
591 case IIO_CHAN_INFO_RAW:
592 return meson_sar_adc_get_sample(indio_dev, chan, NO_AVERAGING,
593 ONE_SAMPLE, val);
594
595 case IIO_CHAN_INFO_AVERAGE_RAW:
596 return meson_sar_adc_get_sample(indio_dev, chan,
597 MEAN_AVERAGING, EIGHT_SAMPLES,
598 val);
599
600 case IIO_CHAN_INFO_SCALE:
601 if (chan->type == IIO_VOLTAGE) {
602 ret = regulator_get_voltage(priv->vref);
603 if (ret < 0) {
604 dev_err(dev, "failed to get vref voltage: %d\n", ret);
605 return ret;
606 }
607
608 *val = ret / 1000;
609 *val2 = priv->param->resolution;
610 return IIO_VAL_FRACTIONAL_LOG2;
611 } else if (chan->type == IIO_TEMP) {
612 /* SoC specific multiplier and divider */
613 *val = priv->param->temperature_multiplier;
614 *val2 = priv->param->temperature_divider;
615
616 /* celsius to millicelsius */
617 *val *= 1000;
618
619 return IIO_VAL_FRACTIONAL;
620 } else {
621 return -EINVAL;
622 }
623
624 case IIO_CHAN_INFO_CALIBBIAS:
625 *val = priv->calibbias;
626 return IIO_VAL_INT;
627
628 case IIO_CHAN_INFO_CALIBSCALE:
629 *val = priv->calibscale / MILLION;
630 *val2 = priv->calibscale % MILLION;
631 return IIO_VAL_INT_PLUS_MICRO;
632
633 case IIO_CHAN_INFO_OFFSET:
634 *val = DIV_ROUND_CLOSEST(MESON_SAR_ADC_TEMP_OFFSET *
635 priv->param->temperature_divider,
636 priv->param->temperature_multiplier);
637 *val -= priv->temperature_sensor_adc_val;
638 return IIO_VAL_INT;
639
640 default:
641 return -EINVAL;
642 }
643 }
644
meson_sar_adc_clk_init(struct iio_dev * indio_dev,void __iomem * base)645 static int meson_sar_adc_clk_init(struct iio_dev *indio_dev,
646 void __iomem *base)
647 {
648 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
649 struct device *dev = indio_dev->dev.parent;
650 struct clk_init_data init;
651 const char *clk_parents[1];
652
653 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#adc_div", dev_name(dev));
654 if (!init.name)
655 return -ENOMEM;
656
657 init.flags = 0;
658 init.ops = &clk_divider_ops;
659 clk_parents[0] = __clk_get_name(priv->clkin);
660 init.parent_names = clk_parents;
661 init.num_parents = 1;
662
663 priv->clk_div.reg = base + MESON_SAR_ADC_REG3;
664 priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
665 priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
666 priv->clk_div.hw.init = &init;
667 priv->clk_div.flags = 0;
668
669 priv->adc_div_clk = devm_clk_register(dev, &priv->clk_div.hw);
670 if (WARN_ON(IS_ERR(priv->adc_div_clk)))
671 return PTR_ERR(priv->adc_div_clk);
672
673 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#adc_en", dev_name(dev));
674 if (!init.name)
675 return -ENOMEM;
676
677 init.flags = CLK_SET_RATE_PARENT;
678 init.ops = &clk_gate_ops;
679 clk_parents[0] = __clk_get_name(priv->adc_div_clk);
680 init.parent_names = clk_parents;
681 init.num_parents = 1;
682
683 priv->clk_gate.reg = base + MESON_SAR_ADC_REG3;
684 priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN);
685 priv->clk_gate.hw.init = &init;
686
687 priv->adc_clk = devm_clk_register(dev, &priv->clk_gate.hw);
688 if (WARN_ON(IS_ERR(priv->adc_clk)))
689 return PTR_ERR(priv->adc_clk);
690
691 return 0;
692 }
693
meson_sar_adc_temp_sensor_init(struct iio_dev * indio_dev)694 static int meson_sar_adc_temp_sensor_init(struct iio_dev *indio_dev)
695 {
696 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
697 u8 *buf, trimming_bits, trimming_mask, upper_adc_val;
698 struct device *dev = indio_dev->dev.parent;
699 struct nvmem_cell *temperature_calib;
700 size_t read_len;
701 int ret;
702
703 temperature_calib = devm_nvmem_cell_get(dev, "temperature_calib");
704 if (IS_ERR(temperature_calib)) {
705 ret = PTR_ERR(temperature_calib);
706
707 /*
708 * leave the temperature sensor disabled if no calibration data
709 * was passed via nvmem-cells.
710 */
711 if (ret == -ENODEV)
712 return 0;
713
714 return dev_err_probe(dev, ret, "failed to get temperature_calib cell\n");
715 }
716
717 priv->tsc_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "amlogic,hhi-sysctrl");
718 if (IS_ERR(priv->tsc_regmap))
719 return dev_err_probe(dev, PTR_ERR(priv->tsc_regmap),
720 "failed to get amlogic,hhi-sysctrl regmap\n");
721
722 read_len = MESON_SAR_ADC_EFUSE_BYTES;
723 buf = nvmem_cell_read(temperature_calib, &read_len);
724 if (IS_ERR(buf))
725 return dev_err_probe(dev, PTR_ERR(buf), "failed to read temperature_calib cell\n");
726 if (read_len != MESON_SAR_ADC_EFUSE_BYTES) {
727 kfree(buf);
728 return dev_err_probe(dev, -EINVAL, "invalid read size of temperature_calib cell\n");
729 }
730
731 trimming_bits = priv->param->temperature_trimming_bits;
732 trimming_mask = BIT(trimming_bits) - 1;
733
734 priv->temperature_sensor_calibrated =
735 buf[3] & MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED;
736 priv->temperature_sensor_coefficient = buf[2] & trimming_mask;
737
738 upper_adc_val = FIELD_GET(MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL,
739 buf[3]);
740
741 priv->temperature_sensor_adc_val = buf[2];
742 priv->temperature_sensor_adc_val |= upper_adc_val << BITS_PER_BYTE;
743 priv->temperature_sensor_adc_val >>= trimming_bits;
744
745 kfree(buf);
746
747 return 0;
748 }
749
meson_sar_adc_init(struct iio_dev * indio_dev)750 static int meson_sar_adc_init(struct iio_dev *indio_dev)
751 {
752 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
753 struct device *dev = indio_dev->dev.parent;
754 int regval, i, ret;
755
756 /*
757 * make sure we start at CH7 input since the other muxes are only used
758 * for internal calibration.
759 */
760 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
761
762 if (priv->param->has_bl30_integration) {
763 /*
764 * leave sampling delay and the input clocks as configured by
765 * BL30 to make sure BL30 gets the values it expects when
766 * reading the temperature sensor.
767 */
768 regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val);
769 if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)
770 return 0;
771 }
772
773 meson_sar_adc_stop_sample_engine(indio_dev);
774
775 /*
776 * disable this bit as seems to be only relevant for Meson6 (based
777 * on the vendor driver), which we don't support at the moment.
778 */
779 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
780 MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL, 0);
781
782 /* disable all channels by default */
783 regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);
784
785 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
786 MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
787 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
788 MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY,
789 MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY);
790
791 /* delay between two samples = (10+1) * 1uS */
792 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
793 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
794 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,
795 10));
796 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
797 MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
798 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
799 0));
800
801 /* delay between two samples = (10+1) * 1uS */
802 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
803 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
804 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
805 10));
806 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
807 MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
808 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
809 1));
810
811 /*
812 * set up the input channel muxes in MESON_SAR_ADC_CHAN_10_SW
813 * (0 = SAR_ADC_CH0, 1 = SAR_ADC_CH1)
814 */
815 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 0);
816 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
817 MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK,
818 regval);
819 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, 1);
820 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
821 MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK,
822 regval);
823
824 /*
825 * set up the input channel muxes in MESON_SAR_ADC_AUX_SW
826 * (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable
827 * MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW and
828 * MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW like the vendor driver.
829 */
830 regval = 0;
831 for (i = 2; i <= 7; i++)
832 regval |= i << MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(i);
833 regval |= MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW;
834 regval |= MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW;
835 regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval);
836
837 if (priv->temperature_sensor_calibrated) {
838 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
839 MESON_SAR_ADC_DELTA_10_TS_REVE1,
840 MESON_SAR_ADC_DELTA_10_TS_REVE1);
841 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
842 MESON_SAR_ADC_DELTA_10_TS_REVE0,
843 MESON_SAR_ADC_DELTA_10_TS_REVE0);
844
845 /*
846 * set bits [3:0] of the TSC (temperature sensor coefficient)
847 * to get the correct values when reading the temperature.
848 */
849 regval = FIELD_PREP(MESON_SAR_ADC_DELTA_10_TS_C_MASK,
850 priv->temperature_sensor_coefficient);
851 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
852 MESON_SAR_ADC_DELTA_10_TS_C_MASK, regval);
853
854 if (priv->param->temperature_trimming_bits == 5) {
855 if (priv->temperature_sensor_coefficient & BIT(4))
856 regval = MESON_HHI_DPLL_TOP_0_TSC_BIT4;
857 else
858 regval = 0;
859
860 /*
861 * bit [4] (the 5th bit when starting to count at 1)
862 * of the TSC is located in the HHI register area.
863 */
864 regmap_update_bits(priv->tsc_regmap,
865 MESON_HHI_DPLL_TOP_0,
866 MESON_HHI_DPLL_TOP_0_TSC_BIT4,
867 regval);
868 }
869 } else {
870 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
871 MESON_SAR_ADC_DELTA_10_TS_REVE1, 0);
872 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
873 MESON_SAR_ADC_DELTA_10_TS_REVE0, 0);
874 }
875
876 ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
877 if (ret)
878 return dev_err_probe(dev, ret, "failed to set adc parent to clkin\n");
879
880 ret = clk_set_rate(priv->adc_clk, priv->param->clock_rate);
881 if (ret)
882 return dev_err_probe(dev, ret, "failed to set adc clock rate\n");
883
884 return 0;
885 }
886
meson_sar_adc_set_bandgap(struct iio_dev * indio_dev,bool on_off)887 static void meson_sar_adc_set_bandgap(struct iio_dev *indio_dev, bool on_off)
888 {
889 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
890 const struct meson_sar_adc_param *param = priv->param;
891 u32 enable_mask;
892
893 if (param->bandgap_reg == MESON_SAR_ADC_REG11)
894 enable_mask = MESON_SAR_ADC_REG11_BANDGAP_EN;
895 else
896 enable_mask = MESON_SAR_ADC_DELTA_10_TS_VBG_EN;
897
898 regmap_update_bits(priv->regmap, param->bandgap_reg, enable_mask,
899 on_off ? enable_mask : 0);
900 }
901
meson_sar_adc_hw_enable(struct iio_dev * indio_dev)902 static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
903 {
904 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
905 struct device *dev = indio_dev->dev.parent;
906 int ret;
907 u32 regval;
908
909 ret = meson_sar_adc_lock(indio_dev);
910 if (ret)
911 goto err_lock;
912
913 ret = regulator_enable(priv->vref);
914 if (ret < 0) {
915 dev_err(dev, "failed to enable vref regulator\n");
916 goto err_vref;
917 }
918
919 ret = clk_prepare_enable(priv->core_clk);
920 if (ret) {
921 dev_err(dev, "failed to enable core clk\n");
922 goto err_core_clk;
923 }
924
925 regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1);
926 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
927 MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
928
929 meson_sar_adc_set_bandgap(indio_dev, true);
930
931 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
932 MESON_SAR_ADC_REG3_ADC_EN,
933 MESON_SAR_ADC_REG3_ADC_EN);
934
935 udelay(5);
936
937 ret = clk_prepare_enable(priv->adc_clk);
938 if (ret) {
939 dev_err(dev, "failed to enable adc clk\n");
940 goto err_adc_clk;
941 }
942
943 meson_sar_adc_unlock(indio_dev);
944
945 return 0;
946
947 err_adc_clk:
948 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
949 MESON_SAR_ADC_REG3_ADC_EN, 0);
950 meson_sar_adc_set_bandgap(indio_dev, false);
951 clk_disable_unprepare(priv->core_clk);
952 err_core_clk:
953 regulator_disable(priv->vref);
954 err_vref:
955 meson_sar_adc_unlock(indio_dev);
956 err_lock:
957 return ret;
958 }
959
meson_sar_adc_hw_disable(struct iio_dev * indio_dev)960 static int meson_sar_adc_hw_disable(struct iio_dev *indio_dev)
961 {
962 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
963 int ret;
964
965 ret = meson_sar_adc_lock(indio_dev);
966 if (ret)
967 return ret;
968
969 clk_disable_unprepare(priv->adc_clk);
970
971 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
972 MESON_SAR_ADC_REG3_ADC_EN, 0);
973
974 meson_sar_adc_set_bandgap(indio_dev, false);
975
976 clk_disable_unprepare(priv->core_clk);
977
978 regulator_disable(priv->vref);
979
980 meson_sar_adc_unlock(indio_dev);
981
982 return 0;
983 }
984
meson_sar_adc_irq(int irq,void * data)985 static irqreturn_t meson_sar_adc_irq(int irq, void *data)
986 {
987 struct iio_dev *indio_dev = data;
988 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
989 unsigned int cnt, threshold;
990 u32 regval;
991
992 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
993 cnt = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
994 threshold = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
995
996 if (cnt < threshold)
997 return IRQ_NONE;
998
999 complete(&priv->done);
1000
1001 return IRQ_HANDLED;
1002 }
1003
meson_sar_adc_calib(struct iio_dev * indio_dev)1004 static int meson_sar_adc_calib(struct iio_dev *indio_dev)
1005 {
1006 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1007 int ret, nominal0, nominal1, value0, value1;
1008
1009 /* use points 25% and 75% for calibration */
1010 nominal0 = (1 << priv->param->resolution) / 4;
1011 nominal1 = (1 << priv->param->resolution) * 3 / 4;
1012
1013 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_DIV4);
1014 usleep_range(10, 20);
1015 ret = meson_sar_adc_get_sample(indio_dev,
1016 &indio_dev->channels[7],
1017 MEAN_AVERAGING, EIGHT_SAMPLES, &value0);
1018 if (ret < 0)
1019 goto out;
1020
1021 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_MUL3_DIV4);
1022 usleep_range(10, 20);
1023 ret = meson_sar_adc_get_sample(indio_dev,
1024 &indio_dev->channels[7],
1025 MEAN_AVERAGING, EIGHT_SAMPLES, &value1);
1026 if (ret < 0)
1027 goto out;
1028
1029 if (value1 <= value0) {
1030 ret = -EINVAL;
1031 goto out;
1032 }
1033
1034 priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION,
1035 value1 - value0);
1036 priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale,
1037 MILLION);
1038 ret = 0;
1039 out:
1040 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
1041
1042 return ret;
1043 }
1044
1045 static const struct iio_info meson_sar_adc_iio_info = {
1046 .read_raw = meson_sar_adc_iio_info_read_raw,
1047 };
1048
1049 static const struct meson_sar_adc_param meson_sar_adc_meson8_param = {
1050 .has_bl30_integration = false,
1051 .clock_rate = 1150000,
1052 .bandgap_reg = MESON_SAR_ADC_DELTA_10,
1053 .regmap_config = &meson_sar_adc_regmap_config_meson8,
1054 .resolution = 10,
1055 .temperature_trimming_bits = 4,
1056 .temperature_multiplier = 18 * 10000,
1057 .temperature_divider = 1024 * 10 * 85,
1058 };
1059
1060 static const struct meson_sar_adc_param meson_sar_adc_meson8b_param = {
1061 .has_bl30_integration = false,
1062 .clock_rate = 1150000,
1063 .bandgap_reg = MESON_SAR_ADC_DELTA_10,
1064 .regmap_config = &meson_sar_adc_regmap_config_meson8,
1065 .resolution = 10,
1066 .temperature_trimming_bits = 5,
1067 .temperature_multiplier = 10,
1068 .temperature_divider = 32,
1069 };
1070
1071 static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = {
1072 .has_bl30_integration = true,
1073 .clock_rate = 1200000,
1074 .bandgap_reg = MESON_SAR_ADC_REG11,
1075 .regmap_config = &meson_sar_adc_regmap_config_gxbb,
1076 .resolution = 10,
1077 };
1078
1079 static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
1080 .has_bl30_integration = true,
1081 .clock_rate = 1200000,
1082 .bandgap_reg = MESON_SAR_ADC_REG11,
1083 .regmap_config = &meson_sar_adc_regmap_config_gxbb,
1084 .resolution = 12,
1085 };
1086
1087 static const struct meson_sar_adc_param meson_sar_adc_g12a_param = {
1088 .has_bl30_integration = false,
1089 .clock_rate = 1200000,
1090 .bandgap_reg = MESON_SAR_ADC_REG11,
1091 .regmap_config = &meson_sar_adc_regmap_config_gxbb,
1092 .resolution = 12,
1093 };
1094
1095 static const struct meson_sar_adc_data meson_sar_adc_meson8_data = {
1096 .param = &meson_sar_adc_meson8_param,
1097 .name = "meson-meson8-saradc",
1098 };
1099
1100 static const struct meson_sar_adc_data meson_sar_adc_meson8b_data = {
1101 .param = &meson_sar_adc_meson8b_param,
1102 .name = "meson-meson8b-saradc",
1103 };
1104
1105 static const struct meson_sar_adc_data meson_sar_adc_meson8m2_data = {
1106 .param = &meson_sar_adc_meson8b_param,
1107 .name = "meson-meson8m2-saradc",
1108 };
1109
1110 static const struct meson_sar_adc_data meson_sar_adc_gxbb_data = {
1111 .param = &meson_sar_adc_gxbb_param,
1112 .name = "meson-gxbb-saradc",
1113 };
1114
1115 static const struct meson_sar_adc_data meson_sar_adc_gxl_data = {
1116 .param = &meson_sar_adc_gxl_param,
1117 .name = "meson-gxl-saradc",
1118 };
1119
1120 static const struct meson_sar_adc_data meson_sar_adc_gxm_data = {
1121 .param = &meson_sar_adc_gxl_param,
1122 .name = "meson-gxm-saradc",
1123 };
1124
1125 static const struct meson_sar_adc_data meson_sar_adc_axg_data = {
1126 .param = &meson_sar_adc_gxl_param,
1127 .name = "meson-axg-saradc",
1128 };
1129
1130 static const struct meson_sar_adc_data meson_sar_adc_g12a_data = {
1131 .param = &meson_sar_adc_g12a_param,
1132 .name = "meson-g12a-saradc",
1133 };
1134
1135 static const struct of_device_id meson_sar_adc_of_match[] = {
1136 {
1137 .compatible = "amlogic,meson8-saradc",
1138 .data = &meson_sar_adc_meson8_data,
1139 }, {
1140 .compatible = "amlogic,meson8b-saradc",
1141 .data = &meson_sar_adc_meson8b_data,
1142 }, {
1143 .compatible = "amlogic,meson8m2-saradc",
1144 .data = &meson_sar_adc_meson8m2_data,
1145 }, {
1146 .compatible = "amlogic,meson-gxbb-saradc",
1147 .data = &meson_sar_adc_gxbb_data,
1148 }, {
1149 .compatible = "amlogic,meson-gxl-saradc",
1150 .data = &meson_sar_adc_gxl_data,
1151 }, {
1152 .compatible = "amlogic,meson-gxm-saradc",
1153 .data = &meson_sar_adc_gxm_data,
1154 }, {
1155 .compatible = "amlogic,meson-axg-saradc",
1156 .data = &meson_sar_adc_axg_data,
1157 }, {
1158 .compatible = "amlogic,meson-g12a-saradc",
1159 .data = &meson_sar_adc_g12a_data,
1160 },
1161 { /* sentinel */ }
1162 };
1163 MODULE_DEVICE_TABLE(of, meson_sar_adc_of_match);
1164
meson_sar_adc_probe(struct platform_device * pdev)1165 static int meson_sar_adc_probe(struct platform_device *pdev)
1166 {
1167 const struct meson_sar_adc_data *match_data;
1168 struct meson_sar_adc_priv *priv;
1169 struct device *dev = &pdev->dev;
1170 struct iio_dev *indio_dev;
1171 void __iomem *base;
1172 int irq, ret;
1173
1174 indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
1175 if (!indio_dev)
1176 return dev_err_probe(dev, -ENOMEM, "failed allocating iio device\n");
1177
1178 priv = iio_priv(indio_dev);
1179 init_completion(&priv->done);
1180
1181 match_data = of_device_get_match_data(dev);
1182 if (!match_data)
1183 return dev_err_probe(dev, -ENODEV, "failed to get match data\n");
1184
1185 priv->param = match_data->param;
1186
1187 indio_dev->name = match_data->name;
1188 indio_dev->modes = INDIO_DIRECT_MODE;
1189 indio_dev->info = &meson_sar_adc_iio_info;
1190
1191 base = devm_platform_ioremap_resource(pdev, 0);
1192 if (IS_ERR(base))
1193 return PTR_ERR(base);
1194
1195 priv->regmap = devm_regmap_init_mmio(dev, base, priv->param->regmap_config);
1196 if (IS_ERR(priv->regmap))
1197 return PTR_ERR(priv->regmap);
1198
1199 irq = irq_of_parse_and_map(dev->of_node, 0);
1200 if (!irq)
1201 return -EINVAL;
1202
1203 ret = devm_request_irq(dev, irq, meson_sar_adc_irq, IRQF_SHARED, dev_name(dev), indio_dev);
1204 if (ret)
1205 return ret;
1206
1207 priv->clkin = devm_clk_get(dev, "clkin");
1208 if (IS_ERR(priv->clkin))
1209 return dev_err_probe(dev, PTR_ERR(priv->clkin), "failed to get clkin\n");
1210
1211 priv->core_clk = devm_clk_get(dev, "core");
1212 if (IS_ERR(priv->core_clk))
1213 return dev_err_probe(dev, PTR_ERR(priv->core_clk), "failed to get core clk\n");
1214
1215 priv->adc_clk = devm_clk_get_optional(dev, "adc_clk");
1216 if (IS_ERR(priv->adc_clk))
1217 return dev_err_probe(dev, PTR_ERR(priv->adc_clk), "failed to get adc clk\n");
1218
1219 priv->adc_sel_clk = devm_clk_get_optional(dev, "adc_sel");
1220 if (IS_ERR(priv->adc_sel_clk))
1221 return dev_err_probe(dev, PTR_ERR(priv->adc_sel_clk), "failed to get adc_sel clk\n");
1222
1223 /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
1224 if (!priv->adc_clk) {
1225 ret = meson_sar_adc_clk_init(indio_dev, base);
1226 if (ret)
1227 return ret;
1228 }
1229
1230 priv->vref = devm_regulator_get(dev, "vref");
1231 if (IS_ERR(priv->vref))
1232 return dev_err_probe(dev, PTR_ERR(priv->vref), "failed to get vref regulator\n");
1233
1234 priv->calibscale = MILLION;
1235
1236 if (priv->param->temperature_trimming_bits) {
1237 ret = meson_sar_adc_temp_sensor_init(indio_dev);
1238 if (ret)
1239 return ret;
1240 }
1241
1242 if (priv->temperature_sensor_calibrated) {
1243 indio_dev->channels = meson_sar_adc_and_temp_iio_channels;
1244 indio_dev->num_channels =
1245 ARRAY_SIZE(meson_sar_adc_and_temp_iio_channels);
1246 } else {
1247 indio_dev->channels = meson_sar_adc_iio_channels;
1248 indio_dev->num_channels =
1249 ARRAY_SIZE(meson_sar_adc_iio_channels);
1250 }
1251
1252 ret = meson_sar_adc_init(indio_dev);
1253 if (ret)
1254 goto err;
1255
1256 mutex_init(&priv->lock);
1257
1258 ret = meson_sar_adc_hw_enable(indio_dev);
1259 if (ret)
1260 goto err;
1261
1262 ret = meson_sar_adc_calib(indio_dev);
1263 if (ret)
1264 dev_warn(dev, "calibration failed\n");
1265
1266 platform_set_drvdata(pdev, indio_dev);
1267
1268 ret = iio_device_register(indio_dev);
1269 if (ret)
1270 goto err_hw;
1271
1272 return 0;
1273
1274 err_hw:
1275 meson_sar_adc_hw_disable(indio_dev);
1276 err:
1277 return ret;
1278 }
1279
meson_sar_adc_remove(struct platform_device * pdev)1280 static int meson_sar_adc_remove(struct platform_device *pdev)
1281 {
1282 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1283
1284 iio_device_unregister(indio_dev);
1285
1286 return meson_sar_adc_hw_disable(indio_dev);
1287 }
1288
meson_sar_adc_suspend(struct device * dev)1289 static int meson_sar_adc_suspend(struct device *dev)
1290 {
1291 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1292
1293 return meson_sar_adc_hw_disable(indio_dev);
1294 }
1295
meson_sar_adc_resume(struct device * dev)1296 static int meson_sar_adc_resume(struct device *dev)
1297 {
1298 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1299
1300 return meson_sar_adc_hw_enable(indio_dev);
1301 }
1302
1303 static DEFINE_SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops,
1304 meson_sar_adc_suspend, meson_sar_adc_resume);
1305
1306 static struct platform_driver meson_sar_adc_driver = {
1307 .probe = meson_sar_adc_probe,
1308 .remove = meson_sar_adc_remove,
1309 .driver = {
1310 .name = "meson-saradc",
1311 .of_match_table = meson_sar_adc_of_match,
1312 .pm = pm_sleep_ptr(&meson_sar_adc_pm_ops),
1313 },
1314 };
1315
1316 module_platform_driver(meson_sar_adc_driver);
1317
1318 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
1319 MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
1320 MODULE_LICENSE("GPL v2");
1321