1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Xilinx XADC driver
4 *
5 * Copyright 2013-2014 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
7 *
8 * Documentation for the parts can be found at:
9 * - XADC hardmacro: Xilinx UG480
10 * - ZYNQ XADC interface: Xilinx UG585
11 * - AXI XADC interface: Xilinx PG019
12 */
13
14 #include <linux/clk.h>
15 #include <linux/device.h>
16 #include <linux/err.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/kernel.h>
20 #include <linux/mod_devicetable.h>
21 #include <linux/module.h>
22 #include <linux/overflow.h>
23 #include <linux/platform_device.h>
24 #include <linux/property.h>
25 #include <linux/slab.h>
26 #include <linux/sysfs.h>
27
28 #include <linux/iio/buffer.h>
29 #include <linux/iio/events.h>
30 #include <linux/iio/iio.h>
31 #include <linux/iio/sysfs.h>
32 #include <linux/iio/trigger.h>
33 #include <linux/iio/trigger_consumer.h>
34 #include <linux/iio/triggered_buffer.h>
35
36 #include "xilinx-xadc.h"
37
38 static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500;
39
40 /* ZYNQ register definitions */
41 #define XADC_ZYNQ_REG_CFG 0x00
42 #define XADC_ZYNQ_REG_INTSTS 0x04
43 #define XADC_ZYNQ_REG_INTMSK 0x08
44 #define XADC_ZYNQ_REG_STATUS 0x0c
45 #define XADC_ZYNQ_REG_CFIFO 0x10
46 #define XADC_ZYNQ_REG_DFIFO 0x14
47 #define XADC_ZYNQ_REG_CTL 0x18
48
49 #define XADC_ZYNQ_CFG_ENABLE BIT(31)
50 #define XADC_ZYNQ_CFG_CFIFOTH_MASK (0xf << 20)
51 #define XADC_ZYNQ_CFG_CFIFOTH_OFFSET 20
52 #define XADC_ZYNQ_CFG_DFIFOTH_MASK (0xf << 16)
53 #define XADC_ZYNQ_CFG_DFIFOTH_OFFSET 16
54 #define XADC_ZYNQ_CFG_WEDGE BIT(13)
55 #define XADC_ZYNQ_CFG_REDGE BIT(12)
56 #define XADC_ZYNQ_CFG_TCKRATE_MASK (0x3 << 8)
57 #define XADC_ZYNQ_CFG_TCKRATE_DIV2 (0x0 << 8)
58 #define XADC_ZYNQ_CFG_TCKRATE_DIV4 (0x1 << 8)
59 #define XADC_ZYNQ_CFG_TCKRATE_DIV8 (0x2 << 8)
60 #define XADC_ZYNQ_CFG_TCKRATE_DIV16 (0x3 << 8)
61 #define XADC_ZYNQ_CFG_IGAP_MASK 0x1f
62 #define XADC_ZYNQ_CFG_IGAP(x) (x)
63
64 #define XADC_ZYNQ_INT_CFIFO_LTH BIT(9)
65 #define XADC_ZYNQ_INT_DFIFO_GTH BIT(8)
66 #define XADC_ZYNQ_INT_ALARM_MASK 0xff
67 #define XADC_ZYNQ_INT_ALARM_OFFSET 0
68
69 #define XADC_ZYNQ_STATUS_CFIFO_LVL_MASK (0xf << 16)
70 #define XADC_ZYNQ_STATUS_CFIFO_LVL_OFFSET 16
71 #define XADC_ZYNQ_STATUS_DFIFO_LVL_MASK (0xf << 12)
72 #define XADC_ZYNQ_STATUS_DFIFO_LVL_OFFSET 12
73 #define XADC_ZYNQ_STATUS_CFIFOF BIT(11)
74 #define XADC_ZYNQ_STATUS_CFIFOE BIT(10)
75 #define XADC_ZYNQ_STATUS_DFIFOF BIT(9)
76 #define XADC_ZYNQ_STATUS_DFIFOE BIT(8)
77 #define XADC_ZYNQ_STATUS_OT BIT(7)
78 #define XADC_ZYNQ_STATUS_ALM(x) BIT(x)
79
80 #define XADC_ZYNQ_CTL_RESET BIT(4)
81
82 #define XADC_ZYNQ_CMD_NOP 0x00
83 #define XADC_ZYNQ_CMD_READ 0x01
84 #define XADC_ZYNQ_CMD_WRITE 0x02
85
86 #define XADC_ZYNQ_CMD(cmd, addr, data) (((cmd) << 26) | ((addr) << 16) | (data))
87
88 /* AXI register definitions */
89 #define XADC_AXI_REG_RESET 0x00
90 #define XADC_AXI_REG_STATUS 0x04
91 #define XADC_AXI_REG_ALARM_STATUS 0x08
92 #define XADC_AXI_REG_CONVST 0x0c
93 #define XADC_AXI_REG_XADC_RESET 0x10
94 #define XADC_AXI_REG_GIER 0x5c
95 #define XADC_AXI_REG_IPISR 0x60
96 #define XADC_AXI_REG_IPIER 0x68
97
98 /* 7 Series */
99 #define XADC_7S_AXI_ADC_REG_OFFSET 0x200
100
101 /* UltraScale */
102 #define XADC_US_AXI_ADC_REG_OFFSET 0x400
103
104 #define XADC_AXI_RESET_MAGIC 0xa
105 #define XADC_AXI_GIER_ENABLE BIT(31)
106
107 #define XADC_AXI_INT_EOS BIT(4)
108 #define XADC_AXI_INT_ALARM_MASK 0x3c0f
109
110 #define XADC_FLAGS_BUFFERED BIT(0)
111 #define XADC_FLAGS_IRQ_OPTIONAL BIT(1)
112
113 /*
114 * The XADC hardware supports a samplerate of up to 1MSPS. Unfortunately it does
115 * not have a hardware FIFO. Which means an interrupt is generated for each
116 * conversion sequence. At 1MSPS sample rate the CPU in ZYNQ7000 is completely
117 * overloaded by the interrupts that it soft-lockups. For this reason the driver
118 * limits the maximum samplerate 150kSPS. At this rate the CPU is fairly busy,
119 * but still responsive.
120 */
121 #define XADC_MAX_SAMPLERATE 150000
122
xadc_write_reg(struct xadc * xadc,unsigned int reg,uint32_t val)123 static void xadc_write_reg(struct xadc *xadc, unsigned int reg,
124 uint32_t val)
125 {
126 writel(val, xadc->base + reg);
127 }
128
xadc_read_reg(struct xadc * xadc,unsigned int reg,uint32_t * val)129 static void xadc_read_reg(struct xadc *xadc, unsigned int reg,
130 uint32_t *val)
131 {
132 *val = readl(xadc->base + reg);
133 }
134
135 /*
136 * The ZYNQ interface uses two asynchronous FIFOs for communication with the
137 * XADC. Reads and writes to the XADC register are performed by submitting a
138 * request to the command FIFO (CFIFO), once the request has been completed the
139 * result can be read from the data FIFO (DFIFO). The method currently used in
140 * this driver is to submit the request for a read/write operation, then go to
141 * sleep and wait for an interrupt that signals that a response is available in
142 * the data FIFO.
143 */
144
xadc_zynq_write_fifo(struct xadc * xadc,uint32_t * cmd,unsigned int n)145 static void xadc_zynq_write_fifo(struct xadc *xadc, uint32_t *cmd,
146 unsigned int n)
147 {
148 unsigned int i;
149
150 for (i = 0; i < n; i++)
151 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFIFO, cmd[i]);
152 }
153
xadc_zynq_drain_fifo(struct xadc * xadc)154 static void xadc_zynq_drain_fifo(struct xadc *xadc)
155 {
156 uint32_t status, tmp;
157
158 xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
159
160 while (!(status & XADC_ZYNQ_STATUS_DFIFOE)) {
161 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
162 xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
163 }
164 }
165
xadc_zynq_update_intmsk(struct xadc * xadc,unsigned int mask,unsigned int val)166 static void xadc_zynq_update_intmsk(struct xadc *xadc, unsigned int mask,
167 unsigned int val)
168 {
169 xadc->zynq_intmask &= ~mask;
170 xadc->zynq_intmask |= val;
171
172 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK,
173 xadc->zynq_intmask | xadc->zynq_masked_alarm);
174 }
175
xadc_zynq_write_adc_reg(struct xadc * xadc,unsigned int reg,uint16_t val)176 static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg,
177 uint16_t val)
178 {
179 uint32_t cmd[1];
180 uint32_t tmp;
181 int ret;
182
183 spin_lock_irq(&xadc->lock);
184 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
185 XADC_ZYNQ_INT_DFIFO_GTH);
186
187 reinit_completion(&xadc->completion);
188
189 cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_WRITE, reg, val);
190 xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
191 xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
192 tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
193 tmp |= 0 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
194 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
195
196 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
197 spin_unlock_irq(&xadc->lock);
198
199 ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
200 if (ret == 0)
201 ret = -EIO;
202 else
203 ret = 0;
204
205 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
206
207 return ret;
208 }
209
xadc_zynq_read_adc_reg(struct xadc * xadc,unsigned int reg,uint16_t * val)210 static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg,
211 uint16_t *val)
212 {
213 uint32_t cmd[2];
214 uint32_t resp, tmp;
215 int ret;
216
217 cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_READ, reg, 0);
218 cmd[1] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_NOP, 0, 0);
219
220 spin_lock_irq(&xadc->lock);
221 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
222 XADC_ZYNQ_INT_DFIFO_GTH);
223 xadc_zynq_drain_fifo(xadc);
224 reinit_completion(&xadc->completion);
225
226 xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
227 xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
228 tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
229 tmp |= 1 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
230 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
231
232 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
233 spin_unlock_irq(&xadc->lock);
234 ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
235 if (ret == 0)
236 ret = -EIO;
237 if (ret < 0)
238 return ret;
239
240 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
241 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
242
243 *val = resp & 0xffff;
244
245 return 0;
246 }
247
xadc_zynq_transform_alarm(unsigned int alarm)248 static unsigned int xadc_zynq_transform_alarm(unsigned int alarm)
249 {
250 return ((alarm & 0x80) >> 4) |
251 ((alarm & 0x78) << 1) |
252 (alarm & 0x07);
253 }
254
255 /*
256 * The ZYNQ threshold interrupts are level sensitive. Since we can't make the
257 * threshold condition go way from within the interrupt handler, this means as
258 * soon as a threshold condition is present we would enter the interrupt handler
259 * again and again. To work around this we mask all active thresholds interrupts
260 * in the interrupt handler and start a timer. In this timer we poll the
261 * interrupt status and only if the interrupt is inactive we unmask it again.
262 */
xadc_zynq_unmask_worker(struct work_struct * work)263 static void xadc_zynq_unmask_worker(struct work_struct *work)
264 {
265 struct xadc *xadc = container_of(work, struct xadc, zynq_unmask_work.work);
266 unsigned int misc_sts, unmask;
267
268 xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &misc_sts);
269
270 misc_sts &= XADC_ZYNQ_INT_ALARM_MASK;
271
272 spin_lock_irq(&xadc->lock);
273
274 /* Clear those bits which are not active anymore */
275 unmask = (xadc->zynq_masked_alarm ^ misc_sts) & xadc->zynq_masked_alarm;
276 xadc->zynq_masked_alarm &= misc_sts;
277
278 /* Also clear those which are masked out anyway */
279 xadc->zynq_masked_alarm &= ~xadc->zynq_intmask;
280
281 /* Clear the interrupts before we unmask them */
282 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, unmask);
283
284 xadc_zynq_update_intmsk(xadc, 0, 0);
285
286 spin_unlock_irq(&xadc->lock);
287
288 /* if still pending some alarm re-trigger the timer */
289 if (xadc->zynq_masked_alarm) {
290 schedule_delayed_work(&xadc->zynq_unmask_work,
291 msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
292 }
293
294 }
295
xadc_zynq_interrupt_handler(int irq,void * devid)296 static irqreturn_t xadc_zynq_interrupt_handler(int irq, void *devid)
297 {
298 struct iio_dev *indio_dev = devid;
299 struct xadc *xadc = iio_priv(indio_dev);
300 uint32_t status;
301
302 xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
303
304 status &= ~(xadc->zynq_intmask | xadc->zynq_masked_alarm);
305
306 if (!status)
307 return IRQ_NONE;
308
309 spin_lock(&xadc->lock);
310
311 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status);
312
313 if (status & XADC_ZYNQ_INT_DFIFO_GTH) {
314 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
315 XADC_ZYNQ_INT_DFIFO_GTH);
316 complete(&xadc->completion);
317 }
318
319 status &= XADC_ZYNQ_INT_ALARM_MASK;
320 if (status) {
321 xadc->zynq_masked_alarm |= status;
322 /*
323 * mask the current event interrupt,
324 * unmask it when the interrupt is no more active.
325 */
326 xadc_zynq_update_intmsk(xadc, 0, 0);
327
328 xadc_handle_events(indio_dev,
329 xadc_zynq_transform_alarm(status));
330
331 /* unmask the required interrupts in timer. */
332 schedule_delayed_work(&xadc->zynq_unmask_work,
333 msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
334 }
335 spin_unlock(&xadc->lock);
336
337 return IRQ_HANDLED;
338 }
339
340 #define XADC_ZYNQ_TCK_RATE_MAX 50000000
341 #define XADC_ZYNQ_IGAP_DEFAULT 20
342 #define XADC_ZYNQ_PCAP_RATE_MAX 200000000
343
xadc_zynq_setup(struct platform_device * pdev,struct iio_dev * indio_dev,int irq)344 static int xadc_zynq_setup(struct platform_device *pdev,
345 struct iio_dev *indio_dev, int irq)
346 {
347 struct xadc *xadc = iio_priv(indio_dev);
348 unsigned long pcap_rate;
349 unsigned int tck_div;
350 unsigned int div;
351 unsigned int igap;
352 unsigned int tck_rate;
353 int ret;
354
355 /* TODO: Figure out how to make igap and tck_rate configurable */
356 igap = XADC_ZYNQ_IGAP_DEFAULT;
357 tck_rate = XADC_ZYNQ_TCK_RATE_MAX;
358
359 xadc->zynq_intmask = ~0;
360
361 pcap_rate = clk_get_rate(xadc->clk);
362 if (!pcap_rate)
363 return -EINVAL;
364
365 if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) {
366 ret = clk_set_rate(xadc->clk,
367 (unsigned long)XADC_ZYNQ_PCAP_RATE_MAX);
368 if (ret)
369 return ret;
370 }
371
372 if (tck_rate > pcap_rate / 2) {
373 div = 2;
374 } else {
375 div = pcap_rate / tck_rate;
376 if (pcap_rate / div > XADC_ZYNQ_TCK_RATE_MAX)
377 div++;
378 }
379
380 if (div <= 3)
381 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV2;
382 else if (div <= 7)
383 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV4;
384 else if (div <= 15)
385 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV8;
386 else
387 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV16;
388
389 xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, XADC_ZYNQ_CTL_RESET);
390 xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, 0);
391 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, ~0);
392 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask);
393 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE |
394 XADC_ZYNQ_CFG_REDGE | XADC_ZYNQ_CFG_WEDGE |
395 tck_div | XADC_ZYNQ_CFG_IGAP(igap));
396
397 if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) {
398 ret = clk_set_rate(xadc->clk, pcap_rate);
399 if (ret)
400 return ret;
401 }
402
403 return 0;
404 }
405
xadc_zynq_get_dclk_rate(struct xadc * xadc)406 static unsigned long xadc_zynq_get_dclk_rate(struct xadc *xadc)
407 {
408 unsigned int div;
409 uint32_t val;
410
411 xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &val);
412
413 switch (val & XADC_ZYNQ_CFG_TCKRATE_MASK) {
414 case XADC_ZYNQ_CFG_TCKRATE_DIV4:
415 div = 4;
416 break;
417 case XADC_ZYNQ_CFG_TCKRATE_DIV8:
418 div = 8;
419 break;
420 case XADC_ZYNQ_CFG_TCKRATE_DIV16:
421 div = 16;
422 break;
423 default:
424 div = 2;
425 break;
426 }
427
428 return clk_get_rate(xadc->clk) / div;
429 }
430
xadc_zynq_update_alarm(struct xadc * xadc,unsigned int alarm)431 static void xadc_zynq_update_alarm(struct xadc *xadc, unsigned int alarm)
432 {
433 unsigned long flags;
434 uint32_t status;
435
436 /* Move OT to bit 7 */
437 alarm = ((alarm & 0x08) << 4) | ((alarm & 0xf0) >> 1) | (alarm & 0x07);
438
439 spin_lock_irqsave(&xadc->lock, flags);
440
441 /* Clear previous interrupts if any. */
442 xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
443 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status & alarm);
444
445 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_ALARM_MASK,
446 ~alarm & XADC_ZYNQ_INT_ALARM_MASK);
447
448 spin_unlock_irqrestore(&xadc->lock, flags);
449 }
450
451 static const struct xadc_ops xadc_zynq_ops = {
452 .read = xadc_zynq_read_adc_reg,
453 .write = xadc_zynq_write_adc_reg,
454 .setup = xadc_zynq_setup,
455 .get_dclk_rate = xadc_zynq_get_dclk_rate,
456 .interrupt_handler = xadc_zynq_interrupt_handler,
457 .update_alarm = xadc_zynq_update_alarm,
458 .type = XADC_TYPE_S7,
459 };
460
461 static const unsigned int xadc_axi_reg_offsets[] = {
462 [XADC_TYPE_S7] = XADC_7S_AXI_ADC_REG_OFFSET,
463 [XADC_TYPE_US] = XADC_US_AXI_ADC_REG_OFFSET,
464 };
465
xadc_axi_read_adc_reg(struct xadc * xadc,unsigned int reg,uint16_t * val)466 static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg,
467 uint16_t *val)
468 {
469 uint32_t val32;
470
471 xadc_read_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,
472 &val32);
473 *val = val32 & 0xffff;
474
475 return 0;
476 }
477
xadc_axi_write_adc_reg(struct xadc * xadc,unsigned int reg,uint16_t val)478 static int xadc_axi_write_adc_reg(struct xadc *xadc, unsigned int reg,
479 uint16_t val)
480 {
481 xadc_write_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,
482 val);
483
484 return 0;
485 }
486
xadc_axi_setup(struct platform_device * pdev,struct iio_dev * indio_dev,int irq)487 static int xadc_axi_setup(struct platform_device *pdev,
488 struct iio_dev *indio_dev, int irq)
489 {
490 struct xadc *xadc = iio_priv(indio_dev);
491
492 xadc_write_reg(xadc, XADC_AXI_REG_RESET, XADC_AXI_RESET_MAGIC);
493 xadc_write_reg(xadc, XADC_AXI_REG_GIER, XADC_AXI_GIER_ENABLE);
494
495 return 0;
496 }
497
xadc_axi_interrupt_handler(int irq,void * devid)498 static irqreturn_t xadc_axi_interrupt_handler(int irq, void *devid)
499 {
500 struct iio_dev *indio_dev = devid;
501 struct xadc *xadc = iio_priv(indio_dev);
502 uint32_t status, mask;
503 unsigned int events;
504
505 xadc_read_reg(xadc, XADC_AXI_REG_IPISR, &status);
506 xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &mask);
507 status &= mask;
508
509 if (!status)
510 return IRQ_NONE;
511
512 if ((status & XADC_AXI_INT_EOS) && xadc->trigger)
513 iio_trigger_poll(xadc->trigger);
514
515 if (status & XADC_AXI_INT_ALARM_MASK) {
516 /*
517 * The order of the bits in the AXI-XADC status register does
518 * not match the order of the bits in the XADC alarm enable
519 * register. xadc_handle_events() expects the events to be in
520 * the same order as the XADC alarm enable register.
521 */
522 events = (status & 0x000e) >> 1;
523 events |= (status & 0x0001) << 3;
524 events |= (status & 0x3c00) >> 6;
525 xadc_handle_events(indio_dev, events);
526 }
527
528 xadc_write_reg(xadc, XADC_AXI_REG_IPISR, status);
529
530 return IRQ_HANDLED;
531 }
532
xadc_axi_update_alarm(struct xadc * xadc,unsigned int alarm)533 static void xadc_axi_update_alarm(struct xadc *xadc, unsigned int alarm)
534 {
535 uint32_t val;
536 unsigned long flags;
537
538 /*
539 * The order of the bits in the AXI-XADC status register does not match
540 * the order of the bits in the XADC alarm enable register. We get
541 * passed the alarm mask in the same order as in the XADC alarm enable
542 * register.
543 */
544 alarm = ((alarm & 0x07) << 1) | ((alarm & 0x08) >> 3) |
545 ((alarm & 0xf0) << 6);
546
547 spin_lock_irqsave(&xadc->lock, flags);
548 xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
549 val &= ~XADC_AXI_INT_ALARM_MASK;
550 val |= alarm;
551 xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
552 spin_unlock_irqrestore(&xadc->lock, flags);
553 }
554
xadc_axi_get_dclk(struct xadc * xadc)555 static unsigned long xadc_axi_get_dclk(struct xadc *xadc)
556 {
557 return clk_get_rate(xadc->clk);
558 }
559
560 static const struct xadc_ops xadc_7s_axi_ops = {
561 .read = xadc_axi_read_adc_reg,
562 .write = xadc_axi_write_adc_reg,
563 .setup = xadc_axi_setup,
564 .get_dclk_rate = xadc_axi_get_dclk,
565 .update_alarm = xadc_axi_update_alarm,
566 .interrupt_handler = xadc_axi_interrupt_handler,
567 .flags = XADC_FLAGS_BUFFERED | XADC_FLAGS_IRQ_OPTIONAL,
568 .type = XADC_TYPE_S7,
569 };
570
571 static const struct xadc_ops xadc_us_axi_ops = {
572 .read = xadc_axi_read_adc_reg,
573 .write = xadc_axi_write_adc_reg,
574 .setup = xadc_axi_setup,
575 .get_dclk_rate = xadc_axi_get_dclk,
576 .update_alarm = xadc_axi_update_alarm,
577 .interrupt_handler = xadc_axi_interrupt_handler,
578 .flags = XADC_FLAGS_BUFFERED | XADC_FLAGS_IRQ_OPTIONAL,
579 .type = XADC_TYPE_US,
580 };
581
_xadc_update_adc_reg(struct xadc * xadc,unsigned int reg,uint16_t mask,uint16_t val)582 static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
583 uint16_t mask, uint16_t val)
584 {
585 uint16_t tmp;
586 int ret;
587
588 ret = _xadc_read_adc_reg(xadc, reg, &tmp);
589 if (ret)
590 return ret;
591
592 return _xadc_write_adc_reg(xadc, reg, (tmp & ~mask) | val);
593 }
594
xadc_update_adc_reg(struct xadc * xadc,unsigned int reg,uint16_t mask,uint16_t val)595 static int xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
596 uint16_t mask, uint16_t val)
597 {
598 int ret;
599
600 mutex_lock(&xadc->mutex);
601 ret = _xadc_update_adc_reg(xadc, reg, mask, val);
602 mutex_unlock(&xadc->mutex);
603
604 return ret;
605 }
606
xadc_get_dclk_rate(struct xadc * xadc)607 static unsigned long xadc_get_dclk_rate(struct xadc *xadc)
608 {
609 return xadc->ops->get_dclk_rate(xadc);
610 }
611
xadc_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * mask)612 static int xadc_update_scan_mode(struct iio_dev *indio_dev,
613 const unsigned long *mask)
614 {
615 struct xadc *xadc = iio_priv(indio_dev);
616 size_t new_size, n;
617 void *data;
618
619 n = bitmap_weight(mask, indio_dev->masklength);
620
621 if (check_mul_overflow(n, sizeof(*xadc->data), &new_size))
622 return -ENOMEM;
623
624 data = devm_krealloc(indio_dev->dev.parent, xadc->data,
625 new_size, GFP_KERNEL);
626 if (!data)
627 return -ENOMEM;
628
629 memset(data, 0, new_size);
630 xadc->data = data;
631
632 return 0;
633 }
634
xadc_scan_index_to_channel(unsigned int scan_index)635 static unsigned int xadc_scan_index_to_channel(unsigned int scan_index)
636 {
637 switch (scan_index) {
638 case 5:
639 return XADC_REG_VCCPINT;
640 case 6:
641 return XADC_REG_VCCPAUX;
642 case 7:
643 return XADC_REG_VCCO_DDR;
644 case 8:
645 return XADC_REG_TEMP;
646 case 9:
647 return XADC_REG_VCCINT;
648 case 10:
649 return XADC_REG_VCCAUX;
650 case 11:
651 return XADC_REG_VPVN;
652 case 12:
653 return XADC_REG_VREFP;
654 case 13:
655 return XADC_REG_VREFN;
656 case 14:
657 return XADC_REG_VCCBRAM;
658 default:
659 return XADC_REG_VAUX(scan_index - 16);
660 }
661 }
662
xadc_trigger_handler(int irq,void * p)663 static irqreturn_t xadc_trigger_handler(int irq, void *p)
664 {
665 struct iio_poll_func *pf = p;
666 struct iio_dev *indio_dev = pf->indio_dev;
667 struct xadc *xadc = iio_priv(indio_dev);
668 unsigned int chan;
669 int i, j;
670
671 if (!xadc->data)
672 goto out;
673
674 j = 0;
675 for_each_set_bit(i, indio_dev->active_scan_mask,
676 indio_dev->masklength) {
677 chan = xadc_scan_index_to_channel(i);
678 xadc_read_adc_reg(xadc, chan, &xadc->data[j]);
679 j++;
680 }
681
682 iio_push_to_buffers(indio_dev, xadc->data);
683
684 out:
685 iio_trigger_notify_done(indio_dev->trig);
686
687 return IRQ_HANDLED;
688 }
689
xadc_trigger_set_state(struct iio_trigger * trigger,bool state)690 static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state)
691 {
692 struct xadc *xadc = iio_trigger_get_drvdata(trigger);
693 unsigned long flags;
694 unsigned int convst;
695 unsigned int val;
696 int ret = 0;
697
698 mutex_lock(&xadc->mutex);
699
700 if (state) {
701 /* Only one of the two triggers can be active at a time. */
702 if (xadc->trigger != NULL) {
703 ret = -EBUSY;
704 goto err_out;
705 } else {
706 xadc->trigger = trigger;
707 if (trigger == xadc->convst_trigger)
708 convst = XADC_CONF0_EC;
709 else
710 convst = 0;
711 }
712 ret = _xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF0_EC,
713 convst);
714 if (ret)
715 goto err_out;
716 } else {
717 xadc->trigger = NULL;
718 }
719
720 spin_lock_irqsave(&xadc->lock, flags);
721 xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
722 xadc_write_reg(xadc, XADC_AXI_REG_IPISR, XADC_AXI_INT_EOS);
723 if (state)
724 val |= XADC_AXI_INT_EOS;
725 else
726 val &= ~XADC_AXI_INT_EOS;
727 xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
728 spin_unlock_irqrestore(&xadc->lock, flags);
729
730 err_out:
731 mutex_unlock(&xadc->mutex);
732
733 return ret;
734 }
735
736 static const struct iio_trigger_ops xadc_trigger_ops = {
737 .set_trigger_state = &xadc_trigger_set_state,
738 };
739
xadc_alloc_trigger(struct iio_dev * indio_dev,const char * name)740 static struct iio_trigger *xadc_alloc_trigger(struct iio_dev *indio_dev,
741 const char *name)
742 {
743 struct device *dev = indio_dev->dev.parent;
744 struct iio_trigger *trig;
745 int ret;
746
747 trig = devm_iio_trigger_alloc(dev, "%s%d-%s", indio_dev->name,
748 iio_device_id(indio_dev), name);
749 if (trig == NULL)
750 return ERR_PTR(-ENOMEM);
751
752 trig->ops = &xadc_trigger_ops;
753 iio_trigger_set_drvdata(trig, iio_priv(indio_dev));
754
755 ret = devm_iio_trigger_register(dev, trig);
756 if (ret)
757 return ERR_PTR(ret);
758
759 return trig;
760 }
761
xadc_power_adc_b(struct xadc * xadc,unsigned int seq_mode)762 static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode)
763 {
764 uint16_t val;
765
766 /*
767 * As per datasheet the power-down bits are don't care in the
768 * UltraScale, but as per reality setting the power-down bit for the
769 * non-existing ADC-B powers down the main ADC, so just return and don't
770 * do anything.
771 */
772 if (xadc->ops->type == XADC_TYPE_US)
773 return 0;
774
775 /* Powerdown the ADC-B when it is not needed. */
776 switch (seq_mode) {
777 case XADC_CONF1_SEQ_SIMULTANEOUS:
778 case XADC_CONF1_SEQ_INDEPENDENT:
779 val = 0;
780 break;
781 default:
782 val = XADC_CONF2_PD_ADC_B;
783 break;
784 }
785
786 return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_PD_MASK,
787 val);
788 }
789
xadc_get_seq_mode(struct xadc * xadc,unsigned long scan_mode)790 static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode)
791 {
792 unsigned int aux_scan_mode = scan_mode >> 16;
793
794 /* UltraScale has only one ADC and supports only continuous mode */
795 if (xadc->ops->type == XADC_TYPE_US)
796 return XADC_CONF1_SEQ_CONTINUOUS;
797
798 if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_DUAL)
799 return XADC_CONF1_SEQ_SIMULTANEOUS;
800
801 if ((aux_scan_mode & 0xff00) == 0 ||
802 (aux_scan_mode & 0x00ff) == 0)
803 return XADC_CONF1_SEQ_CONTINUOUS;
804
805 return XADC_CONF1_SEQ_SIMULTANEOUS;
806 }
807
xadc_postdisable(struct iio_dev * indio_dev)808 static int xadc_postdisable(struct iio_dev *indio_dev)
809 {
810 struct xadc *xadc = iio_priv(indio_dev);
811 unsigned long scan_mask;
812 int ret;
813 int i;
814
815 scan_mask = 1; /* Run calibration as part of the sequence */
816 for (i = 0; i < indio_dev->num_channels; i++)
817 scan_mask |= BIT(indio_dev->channels[i].scan_index);
818
819 /* Enable all channels and calibration */
820 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);
821 if (ret)
822 return ret;
823
824 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);
825 if (ret)
826 return ret;
827
828 ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
829 XADC_CONF1_SEQ_CONTINUOUS);
830 if (ret)
831 return ret;
832
833 return xadc_power_adc_b(xadc, XADC_CONF1_SEQ_CONTINUOUS);
834 }
835
xadc_preenable(struct iio_dev * indio_dev)836 static int xadc_preenable(struct iio_dev *indio_dev)
837 {
838 struct xadc *xadc = iio_priv(indio_dev);
839 unsigned long scan_mask;
840 int seq_mode;
841 int ret;
842
843 ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
844 XADC_CONF1_SEQ_DEFAULT);
845 if (ret)
846 goto err;
847
848 scan_mask = *indio_dev->active_scan_mask;
849 seq_mode = xadc_get_seq_mode(xadc, scan_mask);
850
851 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);
852 if (ret)
853 goto err;
854
855 /*
856 * In simultaneous mode the upper and lower aux channels are samples at
857 * the same time. In this mode the upper 8 bits in the sequencer
858 * register are don't care and the lower 8 bits control two channels
859 * each. As such we must set the bit if either the channel in the lower
860 * group or the upper group is enabled.
861 */
862 if (seq_mode == XADC_CONF1_SEQ_SIMULTANEOUS)
863 scan_mask = ((scan_mask >> 8) | scan_mask) & 0xff0000;
864
865 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);
866 if (ret)
867 goto err;
868
869 ret = xadc_power_adc_b(xadc, seq_mode);
870 if (ret)
871 goto err;
872
873 ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
874 seq_mode);
875 if (ret)
876 goto err;
877
878 return 0;
879 err:
880 xadc_postdisable(indio_dev);
881 return ret;
882 }
883
884 static const struct iio_buffer_setup_ops xadc_buffer_ops = {
885 .preenable = &xadc_preenable,
886 .postdisable = &xadc_postdisable,
887 };
888
xadc_read_samplerate(struct xadc * xadc)889 static int xadc_read_samplerate(struct xadc *xadc)
890 {
891 unsigned int div;
892 uint16_t val16;
893 int ret;
894
895 ret = xadc_read_adc_reg(xadc, XADC_REG_CONF2, &val16);
896 if (ret)
897 return ret;
898
899 div = (val16 & XADC_CONF2_DIV_MASK) >> XADC_CONF2_DIV_OFFSET;
900 if (div < 2)
901 div = 2;
902
903 return xadc_get_dclk_rate(xadc) / div / 26;
904 }
905
xadc_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)906 static int xadc_read_raw(struct iio_dev *indio_dev,
907 struct iio_chan_spec const *chan, int *val, int *val2, long info)
908 {
909 struct xadc *xadc = iio_priv(indio_dev);
910 unsigned int bits = chan->scan_type.realbits;
911 uint16_t val16;
912 int ret;
913
914 switch (info) {
915 case IIO_CHAN_INFO_RAW:
916 if (iio_buffer_enabled(indio_dev))
917 return -EBUSY;
918 ret = xadc_read_adc_reg(xadc, chan->address, &val16);
919 if (ret < 0)
920 return ret;
921
922 val16 >>= chan->scan_type.shift;
923 if (chan->scan_type.sign == 'u')
924 *val = val16;
925 else
926 *val = sign_extend32(val16, bits - 1);
927
928 return IIO_VAL_INT;
929 case IIO_CHAN_INFO_SCALE:
930 switch (chan->type) {
931 case IIO_VOLTAGE:
932 /* V = (val * 3.0) / 2**bits */
933 switch (chan->address) {
934 case XADC_REG_VCCINT:
935 case XADC_REG_VCCAUX:
936 case XADC_REG_VREFP:
937 case XADC_REG_VREFN:
938 case XADC_REG_VCCBRAM:
939 case XADC_REG_VCCPINT:
940 case XADC_REG_VCCPAUX:
941 case XADC_REG_VCCO_DDR:
942 *val = 3000;
943 break;
944 default:
945 *val = 1000;
946 break;
947 }
948 *val2 = bits;
949 return IIO_VAL_FRACTIONAL_LOG2;
950 case IIO_TEMP:
951 /* Temp in C = (val * 503.975) / 2**bits - 273.15 */
952 *val = 503975;
953 *val2 = bits;
954 return IIO_VAL_FRACTIONAL_LOG2;
955 default:
956 return -EINVAL;
957 }
958 case IIO_CHAN_INFO_OFFSET:
959 /* Only the temperature channel has an offset */
960 *val = -((273150 << bits) / 503975);
961 return IIO_VAL_INT;
962 case IIO_CHAN_INFO_SAMP_FREQ:
963 ret = xadc_read_samplerate(xadc);
964 if (ret < 0)
965 return ret;
966
967 *val = ret;
968 return IIO_VAL_INT;
969 default:
970 return -EINVAL;
971 }
972 }
973
xadc_write_samplerate(struct xadc * xadc,int val)974 static int xadc_write_samplerate(struct xadc *xadc, int val)
975 {
976 unsigned long clk_rate = xadc_get_dclk_rate(xadc);
977 unsigned int div;
978
979 if (!clk_rate)
980 return -EINVAL;
981
982 if (val <= 0)
983 return -EINVAL;
984
985 /* Max. 150 kSPS */
986 if (val > XADC_MAX_SAMPLERATE)
987 val = XADC_MAX_SAMPLERATE;
988
989 val *= 26;
990
991 /* Min 1MHz */
992 if (val < 1000000)
993 val = 1000000;
994
995 /*
996 * We want to round down, but only if we do not exceed the 150 kSPS
997 * limit.
998 */
999 div = clk_rate / val;
1000 if (clk_rate / div / 26 > XADC_MAX_SAMPLERATE)
1001 div++;
1002 if (div < 2)
1003 div = 2;
1004 else if (div > 0xff)
1005 div = 0xff;
1006
1007 return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_DIV_MASK,
1008 div << XADC_CONF2_DIV_OFFSET);
1009 }
1010
xadc_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)1011 static int xadc_write_raw(struct iio_dev *indio_dev,
1012 struct iio_chan_spec const *chan, int val, int val2, long info)
1013 {
1014 struct xadc *xadc = iio_priv(indio_dev);
1015
1016 if (info != IIO_CHAN_INFO_SAMP_FREQ)
1017 return -EINVAL;
1018
1019 return xadc_write_samplerate(xadc, val);
1020 }
1021
1022 static const struct iio_event_spec xadc_temp_events[] = {
1023 {
1024 .type = IIO_EV_TYPE_THRESH,
1025 .dir = IIO_EV_DIR_RISING,
1026 .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
1027 BIT(IIO_EV_INFO_VALUE) |
1028 BIT(IIO_EV_INFO_HYSTERESIS),
1029 },
1030 };
1031
1032 /* Separate values for upper and lower thresholds, but only a shared enabled */
1033 static const struct iio_event_spec xadc_voltage_events[] = {
1034 {
1035 .type = IIO_EV_TYPE_THRESH,
1036 .dir = IIO_EV_DIR_RISING,
1037 .mask_separate = BIT(IIO_EV_INFO_VALUE),
1038 }, {
1039 .type = IIO_EV_TYPE_THRESH,
1040 .dir = IIO_EV_DIR_FALLING,
1041 .mask_separate = BIT(IIO_EV_INFO_VALUE),
1042 }, {
1043 .type = IIO_EV_TYPE_THRESH,
1044 .dir = IIO_EV_DIR_EITHER,
1045 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1046 },
1047 };
1048
1049 #define XADC_CHAN_TEMP(_chan, _scan_index, _addr, _bits) { \
1050 .type = IIO_TEMP, \
1051 .indexed = 1, \
1052 .channel = (_chan), \
1053 .address = (_addr), \
1054 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1055 BIT(IIO_CHAN_INFO_SCALE) | \
1056 BIT(IIO_CHAN_INFO_OFFSET), \
1057 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1058 .event_spec = xadc_temp_events, \
1059 .num_event_specs = ARRAY_SIZE(xadc_temp_events), \
1060 .scan_index = (_scan_index), \
1061 .scan_type = { \
1062 .sign = 'u', \
1063 .realbits = (_bits), \
1064 .storagebits = 16, \
1065 .shift = 16 - (_bits), \
1066 .endianness = IIO_CPU, \
1067 }, \
1068 }
1069
1070 #define XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, _bits, _ext, _alarm) { \
1071 .type = IIO_VOLTAGE, \
1072 .indexed = 1, \
1073 .channel = (_chan), \
1074 .address = (_addr), \
1075 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1076 BIT(IIO_CHAN_INFO_SCALE), \
1077 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1078 .event_spec = (_alarm) ? xadc_voltage_events : NULL, \
1079 .num_event_specs = (_alarm) ? ARRAY_SIZE(xadc_voltage_events) : 0, \
1080 .scan_index = (_scan_index), \
1081 .scan_type = { \
1082 .sign = ((_addr) == XADC_REG_VREFN) ? 's' : 'u', \
1083 .realbits = (_bits), \
1084 .storagebits = 16, \
1085 .shift = 16 - (_bits), \
1086 .endianness = IIO_CPU, \
1087 }, \
1088 .extend_name = _ext, \
1089 }
1090
1091 /* 7 Series */
1092 #define XADC_7S_CHAN_TEMP(_chan, _scan_index, _addr) \
1093 XADC_CHAN_TEMP(_chan, _scan_index, _addr, 12)
1094 #define XADC_7S_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) \
1095 XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, 12, _ext, _alarm)
1096
1097 static const struct iio_chan_spec xadc_7s_channels[] = {
1098 XADC_7S_CHAN_TEMP(0, 8, XADC_REG_TEMP),
1099 XADC_7S_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true),
1100 XADC_7S_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true),
1101 XADC_7S_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true),
1102 XADC_7S_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpint", true),
1103 XADC_7S_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpaux", true),
1104 XADC_7S_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccoddr", true),
1105 XADC_7S_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false),
1106 XADC_7S_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false),
1107 XADC_7S_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false),
1108 XADC_7S_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false),
1109 XADC_7S_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false),
1110 XADC_7S_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false),
1111 XADC_7S_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false),
1112 XADC_7S_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false),
1113 XADC_7S_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false),
1114 XADC_7S_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false),
1115 XADC_7S_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false),
1116 XADC_7S_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false),
1117 XADC_7S_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false),
1118 XADC_7S_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false),
1119 XADC_7S_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false),
1120 XADC_7S_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false),
1121 XADC_7S_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false),
1122 XADC_7S_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false),
1123 XADC_7S_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false),
1124 };
1125
1126 /* UltraScale */
1127 #define XADC_US_CHAN_TEMP(_chan, _scan_index, _addr) \
1128 XADC_CHAN_TEMP(_chan, _scan_index, _addr, 10)
1129 #define XADC_US_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) \
1130 XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, 10, _ext, _alarm)
1131
1132 static const struct iio_chan_spec xadc_us_channels[] = {
1133 XADC_US_CHAN_TEMP(0, 8, XADC_REG_TEMP),
1134 XADC_US_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true),
1135 XADC_US_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true),
1136 XADC_US_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true),
1137 XADC_US_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpsintlp", true),
1138 XADC_US_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpsintfp", true),
1139 XADC_US_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccpsaux", true),
1140 XADC_US_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false),
1141 XADC_US_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false),
1142 XADC_US_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false),
1143 XADC_US_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false),
1144 XADC_US_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false),
1145 XADC_US_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false),
1146 XADC_US_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false),
1147 XADC_US_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false),
1148 XADC_US_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false),
1149 XADC_US_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false),
1150 XADC_US_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false),
1151 XADC_US_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false),
1152 XADC_US_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false),
1153 XADC_US_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false),
1154 XADC_US_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false),
1155 XADC_US_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false),
1156 XADC_US_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false),
1157 XADC_US_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false),
1158 XADC_US_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false),
1159 };
1160
1161 static const struct iio_info xadc_info = {
1162 .read_raw = &xadc_read_raw,
1163 .write_raw = &xadc_write_raw,
1164 .read_event_config = &xadc_read_event_config,
1165 .write_event_config = &xadc_write_event_config,
1166 .read_event_value = &xadc_read_event_value,
1167 .write_event_value = &xadc_write_event_value,
1168 .update_scan_mode = &xadc_update_scan_mode,
1169 };
1170
1171 static const struct of_device_id xadc_of_match_table[] = {
1172 {
1173 .compatible = "xlnx,zynq-xadc-1.00.a",
1174 .data = &xadc_zynq_ops
1175 }, {
1176 .compatible = "xlnx,axi-xadc-1.00.a",
1177 .data = &xadc_7s_axi_ops
1178 }, {
1179 .compatible = "xlnx,system-management-wiz-1.3",
1180 .data = &xadc_us_axi_ops
1181 },
1182 { },
1183 };
1184 MODULE_DEVICE_TABLE(of, xadc_of_match_table);
1185
xadc_parse_dt(struct iio_dev * indio_dev,unsigned int * conf,int irq)1186 static int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, int irq)
1187 {
1188 struct device *dev = indio_dev->dev.parent;
1189 struct xadc *xadc = iio_priv(indio_dev);
1190 const struct iio_chan_spec *channel_templates;
1191 struct iio_chan_spec *channels, *chan;
1192 struct fwnode_handle *chan_node, *child;
1193 unsigned int max_channels;
1194 unsigned int num_channels;
1195 const char *external_mux;
1196 u32 ext_mux_chan;
1197 u32 reg;
1198 int ret;
1199 int i;
1200
1201 *conf = 0;
1202
1203 ret = device_property_read_string(dev, "xlnx,external-mux", &external_mux);
1204 if (ret < 0 || strcasecmp(external_mux, "none") == 0)
1205 xadc->external_mux_mode = XADC_EXTERNAL_MUX_NONE;
1206 else if (strcasecmp(external_mux, "single") == 0)
1207 xadc->external_mux_mode = XADC_EXTERNAL_MUX_SINGLE;
1208 else if (strcasecmp(external_mux, "dual") == 0)
1209 xadc->external_mux_mode = XADC_EXTERNAL_MUX_DUAL;
1210 else
1211 return -EINVAL;
1212
1213 if (xadc->external_mux_mode != XADC_EXTERNAL_MUX_NONE) {
1214 ret = device_property_read_u32(dev, "xlnx,external-mux-channel", &ext_mux_chan);
1215 if (ret < 0)
1216 return ret;
1217
1218 if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_SINGLE) {
1219 if (ext_mux_chan == 0)
1220 ext_mux_chan = XADC_REG_VPVN;
1221 else if (ext_mux_chan <= 16)
1222 ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1);
1223 else
1224 return -EINVAL;
1225 } else {
1226 if (ext_mux_chan > 0 && ext_mux_chan <= 8)
1227 ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1);
1228 else
1229 return -EINVAL;
1230 }
1231
1232 *conf |= XADC_CONF0_MUX | XADC_CONF0_CHAN(ext_mux_chan);
1233 }
1234 if (xadc->ops->type == XADC_TYPE_S7) {
1235 channel_templates = xadc_7s_channels;
1236 max_channels = ARRAY_SIZE(xadc_7s_channels);
1237 } else {
1238 channel_templates = xadc_us_channels;
1239 max_channels = ARRAY_SIZE(xadc_us_channels);
1240 }
1241 channels = devm_kmemdup(dev, channel_templates,
1242 sizeof(channels[0]) * max_channels, GFP_KERNEL);
1243 if (!channels)
1244 return -ENOMEM;
1245
1246 num_channels = 9;
1247 chan = &channels[9];
1248
1249 chan_node = device_get_named_child_node(dev, "xlnx,channels");
1250 fwnode_for_each_child_node(chan_node, child) {
1251 if (num_channels >= max_channels) {
1252 fwnode_handle_put(child);
1253 break;
1254 }
1255
1256 ret = fwnode_property_read_u32(child, "reg", ®);
1257 if (ret || reg > 16)
1258 continue;
1259
1260 if (fwnode_property_read_bool(child, "xlnx,bipolar"))
1261 chan->scan_type.sign = 's';
1262
1263 if (reg == 0) {
1264 chan->scan_index = 11;
1265 chan->address = XADC_REG_VPVN;
1266 } else {
1267 chan->scan_index = 15 + reg;
1268 chan->address = XADC_REG_VAUX(reg - 1);
1269 }
1270 num_channels++;
1271 chan++;
1272 }
1273 fwnode_handle_put(chan_node);
1274
1275 /* No IRQ => no events */
1276 if (irq <= 0) {
1277 for (i = 0; i < num_channels; i++) {
1278 channels[i].event_spec = NULL;
1279 channels[i].num_event_specs = 0;
1280 }
1281 }
1282
1283 indio_dev->num_channels = num_channels;
1284 indio_dev->channels = devm_krealloc(dev, channels,
1285 sizeof(*channels) * num_channels,
1286 GFP_KERNEL);
1287 /* If we can't resize the channels array, just use the original */
1288 if (!indio_dev->channels)
1289 indio_dev->channels = channels;
1290
1291 return 0;
1292 }
1293
1294 static const char * const xadc_type_names[] = {
1295 [XADC_TYPE_S7] = "xadc",
1296 [XADC_TYPE_US] = "xilinx-system-monitor",
1297 };
1298
xadc_cancel_delayed_work(void * data)1299 static void xadc_cancel_delayed_work(void *data)
1300 {
1301 struct delayed_work *work = data;
1302
1303 cancel_delayed_work_sync(work);
1304 }
1305
xadc_probe(struct platform_device * pdev)1306 static int xadc_probe(struct platform_device *pdev)
1307 {
1308 struct device *dev = &pdev->dev;
1309 const struct xadc_ops *ops;
1310 struct iio_dev *indio_dev;
1311 unsigned int bipolar_mask;
1312 unsigned int conf0;
1313 struct xadc *xadc;
1314 int ret;
1315 int irq;
1316 int i;
1317
1318 ops = device_get_match_data(dev);
1319 if (!ops)
1320 return -EINVAL;
1321
1322 irq = platform_get_irq_optional(pdev, 0);
1323 if (irq < 0 &&
1324 (irq != -ENXIO || !(ops->flags & XADC_FLAGS_IRQ_OPTIONAL)))
1325 return irq;
1326
1327 indio_dev = devm_iio_device_alloc(dev, sizeof(*xadc));
1328 if (!indio_dev)
1329 return -ENOMEM;
1330
1331 xadc = iio_priv(indio_dev);
1332 xadc->ops = ops;
1333 init_completion(&xadc->completion);
1334 mutex_init(&xadc->mutex);
1335 spin_lock_init(&xadc->lock);
1336 INIT_DELAYED_WORK(&xadc->zynq_unmask_work, xadc_zynq_unmask_worker);
1337
1338 xadc->base = devm_platform_ioremap_resource(pdev, 0);
1339 if (IS_ERR(xadc->base))
1340 return PTR_ERR(xadc->base);
1341
1342 indio_dev->name = xadc_type_names[xadc->ops->type];
1343 indio_dev->modes = INDIO_DIRECT_MODE;
1344 indio_dev->info = &xadc_info;
1345
1346 ret = xadc_parse_dt(indio_dev, &conf0, irq);
1347 if (ret)
1348 return ret;
1349
1350 if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
1351 ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
1352 &iio_pollfunc_store_time,
1353 &xadc_trigger_handler,
1354 &xadc_buffer_ops);
1355 if (ret)
1356 return ret;
1357
1358 if (irq > 0) {
1359 xadc->convst_trigger = xadc_alloc_trigger(indio_dev, "convst");
1360 if (IS_ERR(xadc->convst_trigger))
1361 return PTR_ERR(xadc->convst_trigger);
1362
1363 xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev,
1364 "samplerate");
1365 if (IS_ERR(xadc->samplerate_trigger))
1366 return PTR_ERR(xadc->samplerate_trigger);
1367 }
1368 }
1369
1370 xadc->clk = devm_clk_get_enabled(dev, NULL);
1371 if (IS_ERR(xadc->clk))
1372 return PTR_ERR(xadc->clk);
1373
1374 /*
1375 * Make sure not to exceed the maximum samplerate since otherwise the
1376 * resulting interrupt storm will soft-lock the system.
1377 */
1378 if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
1379 ret = xadc_read_samplerate(xadc);
1380 if (ret < 0)
1381 return ret;
1382
1383 if (ret > XADC_MAX_SAMPLERATE) {
1384 ret = xadc_write_samplerate(xadc, XADC_MAX_SAMPLERATE);
1385 if (ret < 0)
1386 return ret;
1387 }
1388 }
1389
1390 if (irq > 0) {
1391 ret = devm_request_irq(dev, irq, xadc->ops->interrupt_handler,
1392 0, dev_name(dev), indio_dev);
1393 if (ret)
1394 return ret;
1395
1396 ret = devm_add_action_or_reset(dev, xadc_cancel_delayed_work,
1397 &xadc->zynq_unmask_work);
1398 if (ret)
1399 return ret;
1400 }
1401
1402 ret = xadc->ops->setup(pdev, indio_dev, irq);
1403 if (ret)
1404 return ret;
1405
1406 for (i = 0; i < 16; i++)
1407 xadc_read_adc_reg(xadc, XADC_REG_THRESHOLD(i),
1408 &xadc->threshold[i]);
1409
1410 ret = xadc_write_adc_reg(xadc, XADC_REG_CONF0, conf0);
1411 if (ret)
1412 return ret;
1413
1414 bipolar_mask = 0;
1415 for (i = 0; i < indio_dev->num_channels; i++) {
1416 if (indio_dev->channels[i].scan_type.sign == 's')
1417 bipolar_mask |= BIT(indio_dev->channels[i].scan_index);
1418 }
1419
1420 ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(0), bipolar_mask);
1421 if (ret)
1422 return ret;
1423
1424 ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(1),
1425 bipolar_mask >> 16);
1426 if (ret)
1427 return ret;
1428
1429 /* Disable all alarms */
1430 ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_ALARM_MASK,
1431 XADC_CONF1_ALARM_MASK);
1432 if (ret)
1433 return ret;
1434
1435 /* Set thresholds to min/max */
1436 for (i = 0; i < 16; i++) {
1437 /*
1438 * Set max voltage threshold and both temperature thresholds to
1439 * 0xffff, min voltage threshold to 0.
1440 */
1441 if (i % 8 < 4 || i == 7)
1442 xadc->threshold[i] = 0xffff;
1443 else
1444 xadc->threshold[i] = 0;
1445 ret = xadc_write_adc_reg(xadc, XADC_REG_THRESHOLD(i),
1446 xadc->threshold[i]);
1447 if (ret)
1448 return ret;
1449 }
1450
1451 /* Go to non-buffered mode */
1452 xadc_postdisable(indio_dev);
1453
1454 return devm_iio_device_register(dev, indio_dev);
1455 }
1456
1457 static struct platform_driver xadc_driver = {
1458 .probe = xadc_probe,
1459 .driver = {
1460 .name = "xadc",
1461 .of_match_table = xadc_of_match_table,
1462 },
1463 };
1464 module_platform_driver(xadc_driver);
1465
1466 MODULE_LICENSE("GPL v2");
1467 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1468 MODULE_DESCRIPTION("Xilinx XADC IIO driver");
1469