1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Renesas R-Car MIPI CSI-2 Receiver
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8 #include <linux/delay.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_device.h>
14 #include <linux/of_graph.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/reset.h>
18 #include <linux/sys_soc.h>
19
20 #include <media/mipi-csi2.h>
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-device.h>
23 #include <media/v4l2-fwnode.h>
24 #include <media/v4l2-mc.h>
25 #include <media/v4l2-subdev.h>
26
27 struct rcar_csi2;
28
29 /* Register offsets and bits */
30
31 /* Control Timing Select */
32 #define TREF_REG 0x00
33 #define TREF_TREF BIT(0)
34
35 /* Software Reset */
36 #define SRST_REG 0x04
37 #define SRST_SRST BIT(0)
38
39 /* PHY Operation Control */
40 #define PHYCNT_REG 0x08
41 #define PHYCNT_SHUTDOWNZ BIT(17)
42 #define PHYCNT_RSTZ BIT(16)
43 #define PHYCNT_ENABLECLK BIT(4)
44 #define PHYCNT_ENABLE_3 BIT(3)
45 #define PHYCNT_ENABLE_2 BIT(2)
46 #define PHYCNT_ENABLE_1 BIT(1)
47 #define PHYCNT_ENABLE_0 BIT(0)
48
49 /* Checksum Control */
50 #define CHKSUM_REG 0x0c
51 #define CHKSUM_ECC_EN BIT(1)
52 #define CHKSUM_CRC_EN BIT(0)
53
54 /*
55 * Channel Data Type Select
56 * VCDT[0-15]: Channel 0 VCDT[16-31]: Channel 1
57 * VCDT2[0-15]: Channel 2 VCDT2[16-31]: Channel 3
58 */
59 #define VCDT_REG 0x10
60 #define VCDT2_REG 0x14
61 #define VCDT_VCDTN_EN BIT(15)
62 #define VCDT_SEL_VC(n) (((n) & 0x3) << 8)
63 #define VCDT_SEL_DTN_ON BIT(6)
64 #define VCDT_SEL_DT(n) (((n) & 0x3f) << 0)
65
66 /* Frame Data Type Select */
67 #define FRDT_REG 0x18
68
69 /* Field Detection Control */
70 #define FLD_REG 0x1c
71 #define FLD_FLD_NUM(n) (((n) & 0xff) << 16)
72 #define FLD_DET_SEL(n) (((n) & 0x3) << 4)
73 #define FLD_FLD_EN4 BIT(3)
74 #define FLD_FLD_EN3 BIT(2)
75 #define FLD_FLD_EN2 BIT(1)
76 #define FLD_FLD_EN BIT(0)
77
78 /* Automatic Standby Control */
79 #define ASTBY_REG 0x20
80
81 /* Long Data Type Setting 0 */
82 #define LNGDT0_REG 0x28
83
84 /* Long Data Type Setting 1 */
85 #define LNGDT1_REG 0x2c
86
87 /* Interrupt Enable */
88 #define INTEN_REG 0x30
89 #define INTEN_INT_AFIFO_OF BIT(27)
90 #define INTEN_INT_ERRSOTHS BIT(4)
91 #define INTEN_INT_ERRSOTSYNCHS BIT(3)
92
93 /* Interrupt Source Mask */
94 #define INTCLOSE_REG 0x34
95
96 /* Interrupt Status Monitor */
97 #define INTSTATE_REG 0x38
98 #define INTSTATE_INT_ULPS_START BIT(7)
99 #define INTSTATE_INT_ULPS_END BIT(6)
100
101 /* Interrupt Error Status Monitor */
102 #define INTERRSTATE_REG 0x3c
103
104 /* Short Packet Data */
105 #define SHPDAT_REG 0x40
106
107 /* Short Packet Count */
108 #define SHPCNT_REG 0x44
109
110 /* LINK Operation Control */
111 #define LINKCNT_REG 0x48
112 #define LINKCNT_MONITOR_EN BIT(31)
113 #define LINKCNT_REG_MONI_PACT_EN BIT(25)
114 #define LINKCNT_ICLK_NONSTOP BIT(24)
115
116 /* Lane Swap */
117 #define LSWAP_REG 0x4c
118 #define LSWAP_L3SEL(n) (((n) & 0x3) << 6)
119 #define LSWAP_L2SEL(n) (((n) & 0x3) << 4)
120 #define LSWAP_L1SEL(n) (((n) & 0x3) << 2)
121 #define LSWAP_L0SEL(n) (((n) & 0x3) << 0)
122
123 /* PHY Test Interface Write Register */
124 #define PHTW_REG 0x50
125 #define PHTW_DWEN BIT(24)
126 #define PHTW_TESTDIN_DATA(n) (((n & 0xff)) << 16)
127 #define PHTW_CWEN BIT(8)
128 #define PHTW_TESTDIN_CODE(n) ((n & 0xff))
129
130 #define PHYFRX_REG 0x64
131 #define PHYFRX_FORCERX_MODE_3 BIT(3)
132 #define PHYFRX_FORCERX_MODE_2 BIT(2)
133 #define PHYFRX_FORCERX_MODE_1 BIT(1)
134 #define PHYFRX_FORCERX_MODE_0 BIT(0)
135
136 struct phtw_value {
137 u16 data;
138 u16 code;
139 };
140
141 struct rcsi2_mbps_reg {
142 u16 mbps;
143 u16 reg;
144 };
145
146 static const struct rcsi2_mbps_reg phtw_mbps_v3u[] = {
147 { .mbps = 1500, .reg = 0xcc },
148 { .mbps = 1550, .reg = 0x1d },
149 { .mbps = 1600, .reg = 0x27 },
150 { .mbps = 1650, .reg = 0x30 },
151 { .mbps = 1700, .reg = 0x39 },
152 { .mbps = 1750, .reg = 0x42 },
153 { .mbps = 1800, .reg = 0x4b },
154 { .mbps = 1850, .reg = 0x55 },
155 { .mbps = 1900, .reg = 0x5e },
156 { .mbps = 1950, .reg = 0x67 },
157 { .mbps = 2000, .reg = 0x71 },
158 { .mbps = 2050, .reg = 0x79 },
159 { .mbps = 2100, .reg = 0x83 },
160 { .mbps = 2150, .reg = 0x8c },
161 { .mbps = 2200, .reg = 0x95 },
162 { .mbps = 2250, .reg = 0x9e },
163 { .mbps = 2300, .reg = 0xa7 },
164 { .mbps = 2350, .reg = 0xb0 },
165 { .mbps = 2400, .reg = 0xba },
166 { .mbps = 2450, .reg = 0xc3 },
167 { .mbps = 2500, .reg = 0xcc },
168 { /* sentinel */ },
169 };
170
171 static const struct rcsi2_mbps_reg phtw_mbps_h3_v3h_m3n[] = {
172 { .mbps = 80, .reg = 0x86 },
173 { .mbps = 90, .reg = 0x86 },
174 { .mbps = 100, .reg = 0x87 },
175 { .mbps = 110, .reg = 0x87 },
176 { .mbps = 120, .reg = 0x88 },
177 { .mbps = 130, .reg = 0x88 },
178 { .mbps = 140, .reg = 0x89 },
179 { .mbps = 150, .reg = 0x89 },
180 { .mbps = 160, .reg = 0x8a },
181 { .mbps = 170, .reg = 0x8a },
182 { .mbps = 180, .reg = 0x8b },
183 { .mbps = 190, .reg = 0x8b },
184 { .mbps = 205, .reg = 0x8c },
185 { .mbps = 220, .reg = 0x8d },
186 { .mbps = 235, .reg = 0x8e },
187 { .mbps = 250, .reg = 0x8e },
188 { /* sentinel */ },
189 };
190
191 static const struct rcsi2_mbps_reg phtw_mbps_v3m_e3[] = {
192 { .mbps = 80, .reg = 0x00 },
193 { .mbps = 90, .reg = 0x20 },
194 { .mbps = 100, .reg = 0x40 },
195 { .mbps = 110, .reg = 0x02 },
196 { .mbps = 130, .reg = 0x22 },
197 { .mbps = 140, .reg = 0x42 },
198 { .mbps = 150, .reg = 0x04 },
199 { .mbps = 170, .reg = 0x24 },
200 { .mbps = 180, .reg = 0x44 },
201 { .mbps = 200, .reg = 0x06 },
202 { .mbps = 220, .reg = 0x26 },
203 { .mbps = 240, .reg = 0x46 },
204 { .mbps = 250, .reg = 0x08 },
205 { .mbps = 270, .reg = 0x28 },
206 { .mbps = 300, .reg = 0x0a },
207 { .mbps = 330, .reg = 0x2a },
208 { .mbps = 360, .reg = 0x4a },
209 { .mbps = 400, .reg = 0x0c },
210 { .mbps = 450, .reg = 0x2c },
211 { .mbps = 500, .reg = 0x0e },
212 { .mbps = 550, .reg = 0x2e },
213 { .mbps = 600, .reg = 0x10 },
214 { .mbps = 650, .reg = 0x30 },
215 { .mbps = 700, .reg = 0x12 },
216 { .mbps = 750, .reg = 0x32 },
217 { .mbps = 800, .reg = 0x52 },
218 { .mbps = 850, .reg = 0x72 },
219 { .mbps = 900, .reg = 0x14 },
220 { .mbps = 950, .reg = 0x34 },
221 { .mbps = 1000, .reg = 0x54 },
222 { .mbps = 1050, .reg = 0x74 },
223 { .mbps = 1125, .reg = 0x16 },
224 { /* sentinel */ },
225 };
226
227 /* PHY Test Interface Clear */
228 #define PHTC_REG 0x58
229 #define PHTC_TESTCLR BIT(0)
230
231 /* PHY Frequency Control */
232 #define PHYPLL_REG 0x68
233 #define PHYPLL_HSFREQRANGE(n) ((n) << 16)
234
235 static const struct rcsi2_mbps_reg hsfreqrange_v3u[] = {
236 { .mbps = 80, .reg = 0x00 },
237 { .mbps = 90, .reg = 0x10 },
238 { .mbps = 100, .reg = 0x20 },
239 { .mbps = 110, .reg = 0x30 },
240 { .mbps = 120, .reg = 0x01 },
241 { .mbps = 130, .reg = 0x11 },
242 { .mbps = 140, .reg = 0x21 },
243 { .mbps = 150, .reg = 0x31 },
244 { .mbps = 160, .reg = 0x02 },
245 { .mbps = 170, .reg = 0x12 },
246 { .mbps = 180, .reg = 0x22 },
247 { .mbps = 190, .reg = 0x32 },
248 { .mbps = 205, .reg = 0x03 },
249 { .mbps = 220, .reg = 0x13 },
250 { .mbps = 235, .reg = 0x23 },
251 { .mbps = 250, .reg = 0x33 },
252 { .mbps = 275, .reg = 0x04 },
253 { .mbps = 300, .reg = 0x14 },
254 { .mbps = 325, .reg = 0x25 },
255 { .mbps = 350, .reg = 0x35 },
256 { .mbps = 400, .reg = 0x05 },
257 { .mbps = 450, .reg = 0x16 },
258 { .mbps = 500, .reg = 0x26 },
259 { .mbps = 550, .reg = 0x37 },
260 { .mbps = 600, .reg = 0x07 },
261 { .mbps = 650, .reg = 0x18 },
262 { .mbps = 700, .reg = 0x28 },
263 { .mbps = 750, .reg = 0x39 },
264 { .mbps = 800, .reg = 0x09 },
265 { .mbps = 850, .reg = 0x19 },
266 { .mbps = 900, .reg = 0x29 },
267 { .mbps = 950, .reg = 0x3a },
268 { .mbps = 1000, .reg = 0x0a },
269 { .mbps = 1050, .reg = 0x1a },
270 { .mbps = 1100, .reg = 0x2a },
271 { .mbps = 1150, .reg = 0x3b },
272 { .mbps = 1200, .reg = 0x0b },
273 { .mbps = 1250, .reg = 0x1b },
274 { .mbps = 1300, .reg = 0x2b },
275 { .mbps = 1350, .reg = 0x3c },
276 { .mbps = 1400, .reg = 0x0c },
277 { .mbps = 1450, .reg = 0x1c },
278 { .mbps = 1500, .reg = 0x2c },
279 { .mbps = 1550, .reg = 0x3d },
280 { .mbps = 1600, .reg = 0x0d },
281 { .mbps = 1650, .reg = 0x1d },
282 { .mbps = 1700, .reg = 0x2e },
283 { .mbps = 1750, .reg = 0x3e },
284 { .mbps = 1800, .reg = 0x0e },
285 { .mbps = 1850, .reg = 0x1e },
286 { .mbps = 1900, .reg = 0x2f },
287 { .mbps = 1950, .reg = 0x3f },
288 { .mbps = 2000, .reg = 0x0f },
289 { .mbps = 2050, .reg = 0x40 },
290 { .mbps = 2100, .reg = 0x41 },
291 { .mbps = 2150, .reg = 0x42 },
292 { .mbps = 2200, .reg = 0x43 },
293 { .mbps = 2300, .reg = 0x45 },
294 { .mbps = 2350, .reg = 0x46 },
295 { .mbps = 2400, .reg = 0x47 },
296 { .mbps = 2450, .reg = 0x48 },
297 { .mbps = 2500, .reg = 0x49 },
298 { /* sentinel */ },
299 };
300
301 static const struct rcsi2_mbps_reg hsfreqrange_h3_v3h_m3n[] = {
302 { .mbps = 80, .reg = 0x00 },
303 { .mbps = 90, .reg = 0x10 },
304 { .mbps = 100, .reg = 0x20 },
305 { .mbps = 110, .reg = 0x30 },
306 { .mbps = 120, .reg = 0x01 },
307 { .mbps = 130, .reg = 0x11 },
308 { .mbps = 140, .reg = 0x21 },
309 { .mbps = 150, .reg = 0x31 },
310 { .mbps = 160, .reg = 0x02 },
311 { .mbps = 170, .reg = 0x12 },
312 { .mbps = 180, .reg = 0x22 },
313 { .mbps = 190, .reg = 0x32 },
314 { .mbps = 205, .reg = 0x03 },
315 { .mbps = 220, .reg = 0x13 },
316 { .mbps = 235, .reg = 0x23 },
317 { .mbps = 250, .reg = 0x33 },
318 { .mbps = 275, .reg = 0x04 },
319 { .mbps = 300, .reg = 0x14 },
320 { .mbps = 325, .reg = 0x25 },
321 { .mbps = 350, .reg = 0x35 },
322 { .mbps = 400, .reg = 0x05 },
323 { .mbps = 450, .reg = 0x16 },
324 { .mbps = 500, .reg = 0x26 },
325 { .mbps = 550, .reg = 0x37 },
326 { .mbps = 600, .reg = 0x07 },
327 { .mbps = 650, .reg = 0x18 },
328 { .mbps = 700, .reg = 0x28 },
329 { .mbps = 750, .reg = 0x39 },
330 { .mbps = 800, .reg = 0x09 },
331 { .mbps = 850, .reg = 0x19 },
332 { .mbps = 900, .reg = 0x29 },
333 { .mbps = 950, .reg = 0x3a },
334 { .mbps = 1000, .reg = 0x0a },
335 { .mbps = 1050, .reg = 0x1a },
336 { .mbps = 1100, .reg = 0x2a },
337 { .mbps = 1150, .reg = 0x3b },
338 { .mbps = 1200, .reg = 0x0b },
339 { .mbps = 1250, .reg = 0x1b },
340 { .mbps = 1300, .reg = 0x2b },
341 { .mbps = 1350, .reg = 0x3c },
342 { .mbps = 1400, .reg = 0x0c },
343 { .mbps = 1450, .reg = 0x1c },
344 { .mbps = 1500, .reg = 0x2c },
345 { /* sentinel */ },
346 };
347
348 static const struct rcsi2_mbps_reg hsfreqrange_m3w_h3es1[] = {
349 { .mbps = 80, .reg = 0x00 },
350 { .mbps = 90, .reg = 0x10 },
351 { .mbps = 100, .reg = 0x20 },
352 { .mbps = 110, .reg = 0x30 },
353 { .mbps = 120, .reg = 0x01 },
354 { .mbps = 130, .reg = 0x11 },
355 { .mbps = 140, .reg = 0x21 },
356 { .mbps = 150, .reg = 0x31 },
357 { .mbps = 160, .reg = 0x02 },
358 { .mbps = 170, .reg = 0x12 },
359 { .mbps = 180, .reg = 0x22 },
360 { .mbps = 190, .reg = 0x32 },
361 { .mbps = 205, .reg = 0x03 },
362 { .mbps = 220, .reg = 0x13 },
363 { .mbps = 235, .reg = 0x23 },
364 { .mbps = 250, .reg = 0x33 },
365 { .mbps = 275, .reg = 0x04 },
366 { .mbps = 300, .reg = 0x14 },
367 { .mbps = 325, .reg = 0x05 },
368 { .mbps = 350, .reg = 0x15 },
369 { .mbps = 400, .reg = 0x25 },
370 { .mbps = 450, .reg = 0x06 },
371 { .mbps = 500, .reg = 0x16 },
372 { .mbps = 550, .reg = 0x07 },
373 { .mbps = 600, .reg = 0x17 },
374 { .mbps = 650, .reg = 0x08 },
375 { .mbps = 700, .reg = 0x18 },
376 { .mbps = 750, .reg = 0x09 },
377 { .mbps = 800, .reg = 0x19 },
378 { .mbps = 850, .reg = 0x29 },
379 { .mbps = 900, .reg = 0x39 },
380 { .mbps = 950, .reg = 0x0a },
381 { .mbps = 1000, .reg = 0x1a },
382 { .mbps = 1050, .reg = 0x2a },
383 { .mbps = 1100, .reg = 0x3a },
384 { .mbps = 1150, .reg = 0x0b },
385 { .mbps = 1200, .reg = 0x1b },
386 { .mbps = 1250, .reg = 0x2b },
387 { .mbps = 1300, .reg = 0x3b },
388 { .mbps = 1350, .reg = 0x0c },
389 { .mbps = 1400, .reg = 0x1c },
390 { .mbps = 1450, .reg = 0x2c },
391 { .mbps = 1500, .reg = 0x3c },
392 { /* sentinel */ },
393 };
394
395 /* PHY ESC Error Monitor */
396 #define PHEERM_REG 0x74
397
398 /* PHY Clock Lane Monitor */
399 #define PHCLM_REG 0x78
400 #define PHCLM_STOPSTATECKL BIT(0)
401
402 /* PHY Data Lane Monitor */
403 #define PHDLM_REG 0x7c
404
405 /* CSI0CLK Frequency Configuration Preset Register */
406 #define CSI0CLKFCPR_REG 0x260
407 #define CSI0CLKFREQRANGE(n) ((n & 0x3f) << 16)
408
409 struct rcar_csi2_format {
410 u32 code;
411 unsigned int datatype;
412 unsigned int bpp;
413 };
414
415 static const struct rcar_csi2_format rcar_csi2_formats[] = {
416 {
417 .code = MEDIA_BUS_FMT_RGB888_1X24,
418 .datatype = MIPI_CSI2_DT_RGB888,
419 .bpp = 24,
420 }, {
421 .code = MEDIA_BUS_FMT_UYVY8_1X16,
422 .datatype = MIPI_CSI2_DT_YUV422_8B,
423 .bpp = 16,
424 }, {
425 .code = MEDIA_BUS_FMT_YUYV8_1X16,
426 .datatype = MIPI_CSI2_DT_YUV422_8B,
427 .bpp = 16,
428 }, {
429 .code = MEDIA_BUS_FMT_UYVY8_2X8,
430 .datatype = MIPI_CSI2_DT_YUV422_8B,
431 .bpp = 16,
432 }, {
433 .code = MEDIA_BUS_FMT_YUYV10_2X10,
434 .datatype = MIPI_CSI2_DT_YUV422_8B,
435 .bpp = 20,
436 }, {
437 .code = MEDIA_BUS_FMT_Y10_1X10,
438 .datatype = MIPI_CSI2_DT_RAW10,
439 .bpp = 10,
440 }, {
441 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
442 .datatype = MIPI_CSI2_DT_RAW8,
443 .bpp = 8,
444 }, {
445 .code = MEDIA_BUS_FMT_SGBRG8_1X8,
446 .datatype = MIPI_CSI2_DT_RAW8,
447 .bpp = 8,
448 }, {
449 .code = MEDIA_BUS_FMT_SGRBG8_1X8,
450 .datatype = MIPI_CSI2_DT_RAW8,
451 .bpp = 8,
452 }, {
453 .code = MEDIA_BUS_FMT_SRGGB8_1X8,
454 .datatype = MIPI_CSI2_DT_RAW8,
455 .bpp = 8,
456 }, {
457 .code = MEDIA_BUS_FMT_Y8_1X8,
458 .datatype = MIPI_CSI2_DT_RAW8,
459 .bpp = 8,
460 },
461 };
462
rcsi2_code_to_fmt(unsigned int code)463 static const struct rcar_csi2_format *rcsi2_code_to_fmt(unsigned int code)
464 {
465 unsigned int i;
466
467 for (i = 0; i < ARRAY_SIZE(rcar_csi2_formats); i++)
468 if (rcar_csi2_formats[i].code == code)
469 return &rcar_csi2_formats[i];
470
471 return NULL;
472 }
473
474 enum rcar_csi2_pads {
475 RCAR_CSI2_SINK,
476 RCAR_CSI2_SOURCE_VC0,
477 RCAR_CSI2_SOURCE_VC1,
478 RCAR_CSI2_SOURCE_VC2,
479 RCAR_CSI2_SOURCE_VC3,
480 NR_OF_RCAR_CSI2_PAD,
481 };
482
483 struct rcar_csi2_info {
484 int (*init_phtw)(struct rcar_csi2 *priv, unsigned int mbps);
485 int (*phy_post_init)(struct rcar_csi2 *priv);
486 const struct rcsi2_mbps_reg *hsfreqrange;
487 unsigned int csi0clkfreqrange;
488 unsigned int num_channels;
489 bool clear_ulps;
490 bool use_isp;
491 };
492
493 struct rcar_csi2 {
494 struct device *dev;
495 void __iomem *base;
496 const struct rcar_csi2_info *info;
497 struct reset_control *rstc;
498
499 struct v4l2_subdev subdev;
500 struct media_pad pads[NR_OF_RCAR_CSI2_PAD];
501
502 struct v4l2_async_notifier notifier;
503 struct v4l2_subdev *remote;
504 unsigned int remote_pad;
505
506 int channel_vc[4];
507
508 struct mutex lock; /* Protects mf and stream_count. */
509 struct v4l2_mbus_framefmt mf;
510 int stream_count;
511
512 unsigned short lanes;
513 unsigned char lane_swap[4];
514 };
515
sd_to_csi2(struct v4l2_subdev * sd)516 static inline struct rcar_csi2 *sd_to_csi2(struct v4l2_subdev *sd)
517 {
518 return container_of(sd, struct rcar_csi2, subdev);
519 }
520
notifier_to_csi2(struct v4l2_async_notifier * n)521 static inline struct rcar_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n)
522 {
523 return container_of(n, struct rcar_csi2, notifier);
524 }
525
rcsi2_read(struct rcar_csi2 * priv,unsigned int reg)526 static u32 rcsi2_read(struct rcar_csi2 *priv, unsigned int reg)
527 {
528 return ioread32(priv->base + reg);
529 }
530
rcsi2_write(struct rcar_csi2 * priv,unsigned int reg,u32 data)531 static void rcsi2_write(struct rcar_csi2 *priv, unsigned int reg, u32 data)
532 {
533 iowrite32(data, priv->base + reg);
534 }
535
rcsi2_enter_standby(struct rcar_csi2 * priv)536 static void rcsi2_enter_standby(struct rcar_csi2 *priv)
537 {
538 rcsi2_write(priv, PHYCNT_REG, 0);
539 rcsi2_write(priv, PHTC_REG, PHTC_TESTCLR);
540 reset_control_assert(priv->rstc);
541 usleep_range(100, 150);
542 pm_runtime_put(priv->dev);
543 }
544
rcsi2_exit_standby(struct rcar_csi2 * priv)545 static int rcsi2_exit_standby(struct rcar_csi2 *priv)
546 {
547 int ret;
548
549 ret = pm_runtime_resume_and_get(priv->dev);
550 if (ret < 0)
551 return ret;
552
553 reset_control_deassert(priv->rstc);
554
555 return 0;
556 }
557
rcsi2_wait_phy_start(struct rcar_csi2 * priv,unsigned int lanes)558 static int rcsi2_wait_phy_start(struct rcar_csi2 *priv,
559 unsigned int lanes)
560 {
561 unsigned int timeout;
562
563 /* Wait for the clock and data lanes to enter LP-11 state. */
564 for (timeout = 0; timeout <= 20; timeout++) {
565 const u32 lane_mask = (1 << lanes) - 1;
566
567 if ((rcsi2_read(priv, PHCLM_REG) & PHCLM_STOPSTATECKL) &&
568 (rcsi2_read(priv, PHDLM_REG) & lane_mask) == lane_mask)
569 return 0;
570
571 usleep_range(1000, 2000);
572 }
573
574 dev_err(priv->dev, "Timeout waiting for LP-11 state\n");
575
576 return -ETIMEDOUT;
577 }
578
rcsi2_set_phypll(struct rcar_csi2 * priv,unsigned int mbps)579 static int rcsi2_set_phypll(struct rcar_csi2 *priv, unsigned int mbps)
580 {
581 const struct rcsi2_mbps_reg *hsfreq;
582 const struct rcsi2_mbps_reg *hsfreq_prev = NULL;
583
584 if (mbps < priv->info->hsfreqrange->mbps)
585 dev_warn(priv->dev, "%u Mbps less than min PHY speed %u Mbps",
586 mbps, priv->info->hsfreqrange->mbps);
587
588 for (hsfreq = priv->info->hsfreqrange; hsfreq->mbps != 0; hsfreq++) {
589 if (hsfreq->mbps >= mbps)
590 break;
591 hsfreq_prev = hsfreq;
592 }
593
594 if (!hsfreq->mbps) {
595 dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps);
596 return -ERANGE;
597 }
598
599 if (hsfreq_prev &&
600 ((mbps - hsfreq_prev->mbps) <= (hsfreq->mbps - mbps)))
601 hsfreq = hsfreq_prev;
602
603 rcsi2_write(priv, PHYPLL_REG, PHYPLL_HSFREQRANGE(hsfreq->reg));
604
605 return 0;
606 }
607
rcsi2_calc_mbps(struct rcar_csi2 * priv,unsigned int bpp,unsigned int lanes)608 static int rcsi2_calc_mbps(struct rcar_csi2 *priv, unsigned int bpp,
609 unsigned int lanes)
610 {
611 struct v4l2_subdev *source;
612 struct v4l2_ctrl *ctrl;
613 u64 mbps;
614
615 if (!priv->remote)
616 return -ENODEV;
617
618 source = priv->remote;
619
620 /* Read the pixel rate control from remote. */
621 ctrl = v4l2_ctrl_find(source->ctrl_handler, V4L2_CID_PIXEL_RATE);
622 if (!ctrl) {
623 dev_err(priv->dev, "no pixel rate control in subdev %s\n",
624 source->name);
625 return -EINVAL;
626 }
627
628 /*
629 * Calculate the phypll in mbps.
630 * link_freq = (pixel_rate * bits_per_sample) / (2 * nr_of_lanes)
631 * bps = link_freq * 2
632 */
633 mbps = v4l2_ctrl_g_ctrl_int64(ctrl) * bpp;
634 do_div(mbps, lanes * 1000000);
635
636 return mbps;
637 }
638
rcsi2_get_active_lanes(struct rcar_csi2 * priv,unsigned int * lanes)639 static int rcsi2_get_active_lanes(struct rcar_csi2 *priv,
640 unsigned int *lanes)
641 {
642 struct v4l2_mbus_config mbus_config = { 0 };
643 int ret;
644
645 *lanes = priv->lanes;
646
647 ret = v4l2_subdev_call(priv->remote, pad, get_mbus_config,
648 priv->remote_pad, &mbus_config);
649 if (ret == -ENOIOCTLCMD) {
650 dev_dbg(priv->dev, "No remote mbus configuration available\n");
651 return 0;
652 }
653
654 if (ret) {
655 dev_err(priv->dev, "Failed to get remote mbus configuration\n");
656 return ret;
657 }
658
659 if (mbus_config.type != V4L2_MBUS_CSI2_DPHY) {
660 dev_err(priv->dev, "Unsupported media bus type %u\n",
661 mbus_config.type);
662 return -EINVAL;
663 }
664
665 if (mbus_config.bus.mipi_csi2.num_data_lanes > priv->lanes) {
666 dev_err(priv->dev,
667 "Unsupported mbus config: too many data lanes %u\n",
668 mbus_config.bus.mipi_csi2.num_data_lanes);
669 return -EINVAL;
670 }
671
672 *lanes = mbus_config.bus.mipi_csi2.num_data_lanes;
673
674 return 0;
675 }
676
rcsi2_start_receiver(struct rcar_csi2 * priv)677 static int rcsi2_start_receiver(struct rcar_csi2 *priv)
678 {
679 const struct rcar_csi2_format *format;
680 u32 phycnt, vcdt = 0, vcdt2 = 0, fld = 0;
681 unsigned int lanes;
682 unsigned int i;
683 int mbps, ret;
684
685 dev_dbg(priv->dev, "Input size (%ux%u%c)\n",
686 priv->mf.width, priv->mf.height,
687 priv->mf.field == V4L2_FIELD_NONE ? 'p' : 'i');
688
689 /* Code is validated in set_fmt. */
690 format = rcsi2_code_to_fmt(priv->mf.code);
691 if (!format)
692 return -EINVAL;
693
694 /*
695 * Enable all supported CSI-2 channels with virtual channel and
696 * data type matching.
697 *
698 * NOTE: It's not possible to get individual datatype for each
699 * source virtual channel. Once this is possible in V4L2
700 * it should be used here.
701 */
702 for (i = 0; i < priv->info->num_channels; i++) {
703 u32 vcdt_part;
704
705 if (priv->channel_vc[i] < 0)
706 continue;
707
708 vcdt_part = VCDT_SEL_VC(priv->channel_vc[i]) | VCDT_VCDTN_EN |
709 VCDT_SEL_DTN_ON | VCDT_SEL_DT(format->datatype);
710
711 /* Store in correct reg and offset. */
712 if (i < 2)
713 vcdt |= vcdt_part << ((i % 2) * 16);
714 else
715 vcdt2 |= vcdt_part << ((i % 2) * 16);
716 }
717
718 if (priv->mf.field == V4L2_FIELD_ALTERNATE) {
719 fld = FLD_DET_SEL(1) | FLD_FLD_EN4 | FLD_FLD_EN3 | FLD_FLD_EN2
720 | FLD_FLD_EN;
721
722 if (priv->mf.height == 240)
723 fld |= FLD_FLD_NUM(0);
724 else
725 fld |= FLD_FLD_NUM(1);
726 }
727
728 /*
729 * Get the number of active data lanes inspecting the remote mbus
730 * configuration.
731 */
732 ret = rcsi2_get_active_lanes(priv, &lanes);
733 if (ret)
734 return ret;
735
736 phycnt = PHYCNT_ENABLECLK;
737 phycnt |= (1 << lanes) - 1;
738
739 mbps = rcsi2_calc_mbps(priv, format->bpp, lanes);
740 if (mbps < 0)
741 return mbps;
742
743 /* Enable interrupts. */
744 rcsi2_write(priv, INTEN_REG, INTEN_INT_AFIFO_OF | INTEN_INT_ERRSOTHS
745 | INTEN_INT_ERRSOTSYNCHS);
746
747 /* Init */
748 rcsi2_write(priv, TREF_REG, TREF_TREF);
749 rcsi2_write(priv, PHTC_REG, 0);
750
751 /* Configure */
752 if (!priv->info->use_isp) {
753 rcsi2_write(priv, VCDT_REG, vcdt);
754 if (vcdt2)
755 rcsi2_write(priv, VCDT2_REG, vcdt2);
756 }
757
758 /* Lanes are zero indexed. */
759 rcsi2_write(priv, LSWAP_REG,
760 LSWAP_L0SEL(priv->lane_swap[0] - 1) |
761 LSWAP_L1SEL(priv->lane_swap[1] - 1) |
762 LSWAP_L2SEL(priv->lane_swap[2] - 1) |
763 LSWAP_L3SEL(priv->lane_swap[3] - 1));
764
765 /* Start */
766 if (priv->info->init_phtw) {
767 ret = priv->info->init_phtw(priv, mbps);
768 if (ret)
769 return ret;
770 }
771
772 if (priv->info->hsfreqrange) {
773 ret = rcsi2_set_phypll(priv, mbps);
774 if (ret)
775 return ret;
776 }
777
778 if (priv->info->csi0clkfreqrange)
779 rcsi2_write(priv, CSI0CLKFCPR_REG,
780 CSI0CLKFREQRANGE(priv->info->csi0clkfreqrange));
781
782 if (priv->info->use_isp)
783 rcsi2_write(priv, PHYFRX_REG,
784 PHYFRX_FORCERX_MODE_3 | PHYFRX_FORCERX_MODE_2 |
785 PHYFRX_FORCERX_MODE_1 | PHYFRX_FORCERX_MODE_0);
786
787 rcsi2_write(priv, PHYCNT_REG, phycnt);
788 rcsi2_write(priv, LINKCNT_REG, LINKCNT_MONITOR_EN |
789 LINKCNT_REG_MONI_PACT_EN | LINKCNT_ICLK_NONSTOP);
790 rcsi2_write(priv, FLD_REG, fld);
791 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ);
792 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ | PHYCNT_RSTZ);
793
794 ret = rcsi2_wait_phy_start(priv, lanes);
795 if (ret)
796 return ret;
797
798 if (priv->info->use_isp)
799 rcsi2_write(priv, PHYFRX_REG, 0);
800
801 /* Run post PHY start initialization, if needed. */
802 if (priv->info->phy_post_init) {
803 ret = priv->info->phy_post_init(priv);
804 if (ret)
805 return ret;
806 }
807
808 /* Clear Ultra Low Power interrupt. */
809 if (priv->info->clear_ulps)
810 rcsi2_write(priv, INTSTATE_REG,
811 INTSTATE_INT_ULPS_START |
812 INTSTATE_INT_ULPS_END);
813 return 0;
814 }
815
rcsi2_start(struct rcar_csi2 * priv)816 static int rcsi2_start(struct rcar_csi2 *priv)
817 {
818 int ret;
819
820 ret = rcsi2_exit_standby(priv);
821 if (ret < 0)
822 return ret;
823
824 ret = rcsi2_start_receiver(priv);
825 if (ret) {
826 rcsi2_enter_standby(priv);
827 return ret;
828 }
829
830 ret = v4l2_subdev_call(priv->remote, video, s_stream, 1);
831 if (ret) {
832 rcsi2_enter_standby(priv);
833 return ret;
834 }
835
836 return 0;
837 }
838
rcsi2_stop(struct rcar_csi2 * priv)839 static void rcsi2_stop(struct rcar_csi2 *priv)
840 {
841 rcsi2_enter_standby(priv);
842 v4l2_subdev_call(priv->remote, video, s_stream, 0);
843 }
844
rcsi2_s_stream(struct v4l2_subdev * sd,int enable)845 static int rcsi2_s_stream(struct v4l2_subdev *sd, int enable)
846 {
847 struct rcar_csi2 *priv = sd_to_csi2(sd);
848 int ret = 0;
849
850 mutex_lock(&priv->lock);
851
852 if (!priv->remote) {
853 ret = -ENODEV;
854 goto out;
855 }
856
857 if (enable && priv->stream_count == 0) {
858 ret = rcsi2_start(priv);
859 if (ret)
860 goto out;
861 } else if (!enable && priv->stream_count == 1) {
862 rcsi2_stop(priv);
863 }
864
865 priv->stream_count += enable ? 1 : -1;
866 out:
867 mutex_unlock(&priv->lock);
868
869 return ret;
870 }
871
rcsi2_set_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)872 static int rcsi2_set_pad_format(struct v4l2_subdev *sd,
873 struct v4l2_subdev_state *sd_state,
874 struct v4l2_subdev_format *format)
875 {
876 struct rcar_csi2 *priv = sd_to_csi2(sd);
877 struct v4l2_mbus_framefmt *framefmt;
878
879 mutex_lock(&priv->lock);
880
881 if (!rcsi2_code_to_fmt(format->format.code))
882 format->format.code = rcar_csi2_formats[0].code;
883
884 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
885 priv->mf = format->format;
886 } else {
887 framefmt = v4l2_subdev_get_try_format(sd, sd_state, 0);
888 *framefmt = format->format;
889 }
890
891 mutex_unlock(&priv->lock);
892
893 return 0;
894 }
895
rcsi2_get_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)896 static int rcsi2_get_pad_format(struct v4l2_subdev *sd,
897 struct v4l2_subdev_state *sd_state,
898 struct v4l2_subdev_format *format)
899 {
900 struct rcar_csi2 *priv = sd_to_csi2(sd);
901
902 mutex_lock(&priv->lock);
903
904 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
905 format->format = priv->mf;
906 else
907 format->format = *v4l2_subdev_get_try_format(sd, sd_state, 0);
908
909 mutex_unlock(&priv->lock);
910
911 return 0;
912 }
913
914 static const struct v4l2_subdev_video_ops rcar_csi2_video_ops = {
915 .s_stream = rcsi2_s_stream,
916 };
917
918 static const struct v4l2_subdev_pad_ops rcar_csi2_pad_ops = {
919 .set_fmt = rcsi2_set_pad_format,
920 .get_fmt = rcsi2_get_pad_format,
921 };
922
923 static const struct v4l2_subdev_ops rcar_csi2_subdev_ops = {
924 .video = &rcar_csi2_video_ops,
925 .pad = &rcar_csi2_pad_ops,
926 };
927
rcsi2_irq(int irq,void * data)928 static irqreturn_t rcsi2_irq(int irq, void *data)
929 {
930 struct rcar_csi2 *priv = data;
931 u32 status, err_status;
932
933 status = rcsi2_read(priv, INTSTATE_REG);
934 err_status = rcsi2_read(priv, INTERRSTATE_REG);
935
936 if (!status)
937 return IRQ_HANDLED;
938
939 rcsi2_write(priv, INTSTATE_REG, status);
940
941 if (!err_status)
942 return IRQ_HANDLED;
943
944 rcsi2_write(priv, INTERRSTATE_REG, err_status);
945
946 dev_info(priv->dev, "Transfer error, restarting CSI-2 receiver\n");
947
948 return IRQ_WAKE_THREAD;
949 }
950
rcsi2_irq_thread(int irq,void * data)951 static irqreturn_t rcsi2_irq_thread(int irq, void *data)
952 {
953 struct rcar_csi2 *priv = data;
954
955 mutex_lock(&priv->lock);
956 rcsi2_stop(priv);
957 usleep_range(1000, 2000);
958 if (rcsi2_start(priv))
959 dev_warn(priv->dev, "Failed to restart CSI-2 receiver\n");
960 mutex_unlock(&priv->lock);
961
962 return IRQ_HANDLED;
963 }
964
965 /* -----------------------------------------------------------------------------
966 * Async handling and registration of subdevices and links.
967 */
968
rcsi2_notify_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_subdev * asd)969 static int rcsi2_notify_bound(struct v4l2_async_notifier *notifier,
970 struct v4l2_subdev *subdev,
971 struct v4l2_async_subdev *asd)
972 {
973 struct rcar_csi2 *priv = notifier_to_csi2(notifier);
974 int pad;
975
976 pad = media_entity_get_fwnode_pad(&subdev->entity, asd->match.fwnode,
977 MEDIA_PAD_FL_SOURCE);
978 if (pad < 0) {
979 dev_err(priv->dev, "Failed to find pad for %s\n", subdev->name);
980 return pad;
981 }
982
983 priv->remote = subdev;
984 priv->remote_pad = pad;
985
986 dev_dbg(priv->dev, "Bound %s pad: %d\n", subdev->name, pad);
987
988 return media_create_pad_link(&subdev->entity, pad,
989 &priv->subdev.entity, 0,
990 MEDIA_LNK_FL_ENABLED |
991 MEDIA_LNK_FL_IMMUTABLE);
992 }
993
rcsi2_notify_unbind(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_subdev * asd)994 static void rcsi2_notify_unbind(struct v4l2_async_notifier *notifier,
995 struct v4l2_subdev *subdev,
996 struct v4l2_async_subdev *asd)
997 {
998 struct rcar_csi2 *priv = notifier_to_csi2(notifier);
999
1000 priv->remote = NULL;
1001
1002 dev_dbg(priv->dev, "Unbind %s\n", subdev->name);
1003 }
1004
1005 static const struct v4l2_async_notifier_operations rcar_csi2_notify_ops = {
1006 .bound = rcsi2_notify_bound,
1007 .unbind = rcsi2_notify_unbind,
1008 };
1009
rcsi2_parse_v4l2(struct rcar_csi2 * priv,struct v4l2_fwnode_endpoint * vep)1010 static int rcsi2_parse_v4l2(struct rcar_csi2 *priv,
1011 struct v4l2_fwnode_endpoint *vep)
1012 {
1013 unsigned int i;
1014
1015 /* Only port 0 endpoint 0 is valid. */
1016 if (vep->base.port || vep->base.id)
1017 return -ENOTCONN;
1018
1019 if (vep->bus_type != V4L2_MBUS_CSI2_DPHY) {
1020 dev_err(priv->dev, "Unsupported bus: %u\n", vep->bus_type);
1021 return -EINVAL;
1022 }
1023
1024 priv->lanes = vep->bus.mipi_csi2.num_data_lanes;
1025 if (priv->lanes != 1 && priv->lanes != 2 && priv->lanes != 4) {
1026 dev_err(priv->dev, "Unsupported number of data-lanes: %u\n",
1027 priv->lanes);
1028 return -EINVAL;
1029 }
1030
1031 for (i = 0; i < ARRAY_SIZE(priv->lane_swap); i++) {
1032 priv->lane_swap[i] = i < priv->lanes ?
1033 vep->bus.mipi_csi2.data_lanes[i] : i;
1034
1035 /* Check for valid lane number. */
1036 if (priv->lane_swap[i] < 1 || priv->lane_swap[i] > 4) {
1037 dev_err(priv->dev, "data-lanes must be in 1-4 range\n");
1038 return -EINVAL;
1039 }
1040 }
1041
1042 return 0;
1043 }
1044
rcsi2_parse_dt(struct rcar_csi2 * priv)1045 static int rcsi2_parse_dt(struct rcar_csi2 *priv)
1046 {
1047 struct v4l2_async_subdev *asd;
1048 struct fwnode_handle *fwnode;
1049 struct fwnode_handle *ep;
1050 struct v4l2_fwnode_endpoint v4l2_ep = {
1051 .bus_type = V4L2_MBUS_CSI2_DPHY
1052 };
1053 int ret;
1054
1055 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(priv->dev), 0, 0, 0);
1056 if (!ep) {
1057 dev_err(priv->dev, "Not connected to subdevice\n");
1058 return -EINVAL;
1059 }
1060
1061 ret = v4l2_fwnode_endpoint_parse(ep, &v4l2_ep);
1062 if (ret) {
1063 dev_err(priv->dev, "Could not parse v4l2 endpoint\n");
1064 fwnode_handle_put(ep);
1065 return -EINVAL;
1066 }
1067
1068 ret = rcsi2_parse_v4l2(priv, &v4l2_ep);
1069 if (ret) {
1070 fwnode_handle_put(ep);
1071 return ret;
1072 }
1073
1074 fwnode = fwnode_graph_get_remote_endpoint(ep);
1075 fwnode_handle_put(ep);
1076
1077 dev_dbg(priv->dev, "Found '%pOF'\n", to_of_node(fwnode));
1078
1079 v4l2_async_nf_init(&priv->notifier);
1080 priv->notifier.ops = &rcar_csi2_notify_ops;
1081
1082 asd = v4l2_async_nf_add_fwnode(&priv->notifier, fwnode,
1083 struct v4l2_async_subdev);
1084 fwnode_handle_put(fwnode);
1085 if (IS_ERR(asd))
1086 return PTR_ERR(asd);
1087
1088 ret = v4l2_async_subdev_nf_register(&priv->subdev, &priv->notifier);
1089 if (ret)
1090 v4l2_async_nf_cleanup(&priv->notifier);
1091
1092 return ret;
1093 }
1094
1095 /* -----------------------------------------------------------------------------
1096 * PHTW initialization sequences.
1097 *
1098 * NOTE: Magic values are from the datasheet and lack documentation.
1099 */
1100
rcsi2_phtw_write(struct rcar_csi2 * priv,u16 data,u16 code)1101 static int rcsi2_phtw_write(struct rcar_csi2 *priv, u16 data, u16 code)
1102 {
1103 unsigned int timeout;
1104
1105 rcsi2_write(priv, PHTW_REG,
1106 PHTW_DWEN | PHTW_TESTDIN_DATA(data) |
1107 PHTW_CWEN | PHTW_TESTDIN_CODE(code));
1108
1109 /* Wait for DWEN and CWEN to be cleared by hardware. */
1110 for (timeout = 0; timeout <= 20; timeout++) {
1111 if (!(rcsi2_read(priv, PHTW_REG) & (PHTW_DWEN | PHTW_CWEN)))
1112 return 0;
1113
1114 usleep_range(1000, 2000);
1115 }
1116
1117 dev_err(priv->dev, "Timeout waiting for PHTW_DWEN and/or PHTW_CWEN\n");
1118
1119 return -ETIMEDOUT;
1120 }
1121
rcsi2_phtw_write_array(struct rcar_csi2 * priv,const struct phtw_value * values)1122 static int rcsi2_phtw_write_array(struct rcar_csi2 *priv,
1123 const struct phtw_value *values)
1124 {
1125 const struct phtw_value *value;
1126 int ret;
1127
1128 for (value = values; value->data || value->code; value++) {
1129 ret = rcsi2_phtw_write(priv, value->data, value->code);
1130 if (ret)
1131 return ret;
1132 }
1133
1134 return 0;
1135 }
1136
rcsi2_phtw_write_mbps(struct rcar_csi2 * priv,unsigned int mbps,const struct rcsi2_mbps_reg * values,u16 code)1137 static int rcsi2_phtw_write_mbps(struct rcar_csi2 *priv, unsigned int mbps,
1138 const struct rcsi2_mbps_reg *values, u16 code)
1139 {
1140 const struct rcsi2_mbps_reg *value;
1141 const struct rcsi2_mbps_reg *prev_value = NULL;
1142
1143 for (value = values; value->mbps; value++) {
1144 if (value->mbps >= mbps)
1145 break;
1146 prev_value = value;
1147 }
1148
1149 if (prev_value &&
1150 ((mbps - prev_value->mbps) <= (value->mbps - mbps)))
1151 value = prev_value;
1152
1153 if (!value->mbps) {
1154 dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps);
1155 return -ERANGE;
1156 }
1157
1158 return rcsi2_phtw_write(priv, value->reg, code);
1159 }
1160
__rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 * priv,unsigned int mbps)1161 static int __rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv,
1162 unsigned int mbps)
1163 {
1164 static const struct phtw_value step1[] = {
1165 { .data = 0xcc, .code = 0xe2 },
1166 { .data = 0x01, .code = 0xe3 },
1167 { .data = 0x11, .code = 0xe4 },
1168 { .data = 0x01, .code = 0xe5 },
1169 { .data = 0x10, .code = 0x04 },
1170 { /* sentinel */ },
1171 };
1172
1173 static const struct phtw_value step2[] = {
1174 { .data = 0x38, .code = 0x08 },
1175 { .data = 0x01, .code = 0x00 },
1176 { .data = 0x4b, .code = 0xac },
1177 { .data = 0x03, .code = 0x00 },
1178 { .data = 0x80, .code = 0x07 },
1179 { /* sentinel */ },
1180 };
1181
1182 int ret;
1183
1184 ret = rcsi2_phtw_write_array(priv, step1);
1185 if (ret)
1186 return ret;
1187
1188 if (mbps != 0 && mbps <= 250) {
1189 ret = rcsi2_phtw_write(priv, 0x39, 0x05);
1190 if (ret)
1191 return ret;
1192
1193 ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_h3_v3h_m3n,
1194 0xf1);
1195 if (ret)
1196 return ret;
1197 }
1198
1199 return rcsi2_phtw_write_array(priv, step2);
1200 }
1201
rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 * priv,unsigned int mbps)1202 static int rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, unsigned int mbps)
1203 {
1204 return __rcsi2_init_phtw_h3_v3h_m3n(priv, mbps);
1205 }
1206
rcsi2_init_phtw_h3es2(struct rcar_csi2 * priv,unsigned int mbps)1207 static int rcsi2_init_phtw_h3es2(struct rcar_csi2 *priv, unsigned int mbps)
1208 {
1209 return __rcsi2_init_phtw_h3_v3h_m3n(priv, 0);
1210 }
1211
rcsi2_init_phtw_v3m_e3(struct rcar_csi2 * priv,unsigned int mbps)1212 static int rcsi2_init_phtw_v3m_e3(struct rcar_csi2 *priv, unsigned int mbps)
1213 {
1214 return rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3m_e3, 0x44);
1215 }
1216
rcsi2_phy_post_init_v3m_e3(struct rcar_csi2 * priv)1217 static int rcsi2_phy_post_init_v3m_e3(struct rcar_csi2 *priv)
1218 {
1219 static const struct phtw_value step1[] = {
1220 { .data = 0xee, .code = 0x34 },
1221 { .data = 0xee, .code = 0x44 },
1222 { .data = 0xee, .code = 0x54 },
1223 { .data = 0xee, .code = 0x84 },
1224 { .data = 0xee, .code = 0x94 },
1225 { /* sentinel */ },
1226 };
1227
1228 return rcsi2_phtw_write_array(priv, step1);
1229 }
1230
rcsi2_init_phtw_v3u(struct rcar_csi2 * priv,unsigned int mbps)1231 static int rcsi2_init_phtw_v3u(struct rcar_csi2 *priv,
1232 unsigned int mbps)
1233 {
1234 /* In case of 1500Mbps or less */
1235 static const struct phtw_value step1[] = {
1236 { .data = 0xcc, .code = 0xe2 },
1237 { /* sentinel */ },
1238 };
1239
1240 static const struct phtw_value step2[] = {
1241 { .data = 0x01, .code = 0xe3 },
1242 { .data = 0x11, .code = 0xe4 },
1243 { .data = 0x01, .code = 0xe5 },
1244 { /* sentinel */ },
1245 };
1246
1247 /* In case of 1500Mbps or less */
1248 static const struct phtw_value step3[] = {
1249 { .data = 0x38, .code = 0x08 },
1250 { /* sentinel */ },
1251 };
1252
1253 static const struct phtw_value step4[] = {
1254 { .data = 0x01, .code = 0x00 },
1255 { .data = 0x4b, .code = 0xac },
1256 { .data = 0x03, .code = 0x00 },
1257 { .data = 0x80, .code = 0x07 },
1258 { /* sentinel */ },
1259 };
1260
1261 int ret;
1262
1263 if (mbps != 0 && mbps <= 1500)
1264 ret = rcsi2_phtw_write_array(priv, step1);
1265 else
1266 ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3u, 0xe2);
1267 if (ret)
1268 return ret;
1269
1270 ret = rcsi2_phtw_write_array(priv, step2);
1271 if (ret)
1272 return ret;
1273
1274 if (mbps != 0 && mbps <= 1500) {
1275 ret = rcsi2_phtw_write_array(priv, step3);
1276 if (ret)
1277 return ret;
1278 }
1279
1280 ret = rcsi2_phtw_write_array(priv, step4);
1281 if (ret)
1282 return ret;
1283
1284 return ret;
1285 }
1286
1287 /* -----------------------------------------------------------------------------
1288 * Platform Device Driver.
1289 */
1290
rcsi2_link_setup(struct media_entity * entity,const struct media_pad * local,const struct media_pad * remote,u32 flags)1291 static int rcsi2_link_setup(struct media_entity *entity,
1292 const struct media_pad *local,
1293 const struct media_pad *remote, u32 flags)
1294 {
1295 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
1296 struct rcar_csi2 *priv = sd_to_csi2(sd);
1297 struct video_device *vdev;
1298 int channel, vc;
1299 u32 id;
1300
1301 if (!is_media_entity_v4l2_video_device(remote->entity)) {
1302 dev_err(priv->dev, "Remote is not a video device\n");
1303 return -EINVAL;
1304 }
1305
1306 vdev = media_entity_to_video_device(remote->entity);
1307
1308 if (of_property_read_u32(vdev->dev_parent->of_node, "renesas,id", &id)) {
1309 dev_err(priv->dev, "No renesas,id, can't configure routing\n");
1310 return -EINVAL;
1311 }
1312
1313 channel = id % 4;
1314
1315 if (flags & MEDIA_LNK_FL_ENABLED) {
1316 if (media_pad_remote_pad_first(local)) {
1317 dev_dbg(priv->dev,
1318 "Each VC can only be routed to one output channel\n");
1319 return -EINVAL;
1320 }
1321
1322 vc = local->index - 1;
1323
1324 dev_dbg(priv->dev, "Route VC%d to VIN%u on output channel %d\n",
1325 vc, id, channel);
1326 } else {
1327 vc = -1;
1328 }
1329
1330 priv->channel_vc[channel] = vc;
1331
1332 return 0;
1333 }
1334
1335 static const struct media_entity_operations rcar_csi2_entity_ops = {
1336 .link_setup = rcsi2_link_setup,
1337 .link_validate = v4l2_subdev_link_validate,
1338 };
1339
rcsi2_probe_resources(struct rcar_csi2 * priv,struct platform_device * pdev)1340 static int rcsi2_probe_resources(struct rcar_csi2 *priv,
1341 struct platform_device *pdev)
1342 {
1343 int irq, ret;
1344
1345 priv->base = devm_platform_ioremap_resource(pdev, 0);
1346 if (IS_ERR(priv->base))
1347 return PTR_ERR(priv->base);
1348
1349 irq = platform_get_irq(pdev, 0);
1350 if (irq < 0)
1351 return irq;
1352
1353 ret = devm_request_threaded_irq(&pdev->dev, irq, rcsi2_irq,
1354 rcsi2_irq_thread, IRQF_SHARED,
1355 KBUILD_MODNAME, priv);
1356 if (ret)
1357 return ret;
1358
1359 priv->rstc = devm_reset_control_get(&pdev->dev, NULL);
1360
1361 return PTR_ERR_OR_ZERO(priv->rstc);
1362 }
1363
1364 static const struct rcar_csi2_info rcar_csi2_info_r8a7795 = {
1365 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
1366 .hsfreqrange = hsfreqrange_h3_v3h_m3n,
1367 .csi0clkfreqrange = 0x20,
1368 .num_channels = 4,
1369 .clear_ulps = true,
1370 };
1371
1372 static const struct rcar_csi2_info rcar_csi2_info_r8a7795es1 = {
1373 .hsfreqrange = hsfreqrange_m3w_h3es1,
1374 .num_channels = 4,
1375 };
1376
1377 static const struct rcar_csi2_info rcar_csi2_info_r8a7795es2 = {
1378 .init_phtw = rcsi2_init_phtw_h3es2,
1379 .hsfreqrange = hsfreqrange_h3_v3h_m3n,
1380 .csi0clkfreqrange = 0x20,
1381 .num_channels = 4,
1382 .clear_ulps = true,
1383 };
1384
1385 static const struct rcar_csi2_info rcar_csi2_info_r8a7796 = {
1386 .hsfreqrange = hsfreqrange_m3w_h3es1,
1387 .num_channels = 4,
1388 };
1389
1390 static const struct rcar_csi2_info rcar_csi2_info_r8a77961 = {
1391 .hsfreqrange = hsfreqrange_m3w_h3es1,
1392 .num_channels = 4,
1393 };
1394
1395 static const struct rcar_csi2_info rcar_csi2_info_r8a77965 = {
1396 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
1397 .hsfreqrange = hsfreqrange_h3_v3h_m3n,
1398 .csi0clkfreqrange = 0x20,
1399 .num_channels = 4,
1400 .clear_ulps = true,
1401 };
1402
1403 static const struct rcar_csi2_info rcar_csi2_info_r8a77970 = {
1404 .init_phtw = rcsi2_init_phtw_v3m_e3,
1405 .phy_post_init = rcsi2_phy_post_init_v3m_e3,
1406 .num_channels = 4,
1407 };
1408
1409 static const struct rcar_csi2_info rcar_csi2_info_r8a77980 = {
1410 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
1411 .hsfreqrange = hsfreqrange_h3_v3h_m3n,
1412 .csi0clkfreqrange = 0x20,
1413 .clear_ulps = true,
1414 };
1415
1416 static const struct rcar_csi2_info rcar_csi2_info_r8a77990 = {
1417 .init_phtw = rcsi2_init_phtw_v3m_e3,
1418 .phy_post_init = rcsi2_phy_post_init_v3m_e3,
1419 .num_channels = 2,
1420 };
1421
1422 static const struct rcar_csi2_info rcar_csi2_info_r8a779a0 = {
1423 .init_phtw = rcsi2_init_phtw_v3u,
1424 .hsfreqrange = hsfreqrange_v3u,
1425 .csi0clkfreqrange = 0x20,
1426 .clear_ulps = true,
1427 .use_isp = true,
1428 };
1429
1430 static const struct of_device_id rcar_csi2_of_table[] = {
1431 {
1432 .compatible = "renesas,r8a774a1-csi2",
1433 .data = &rcar_csi2_info_r8a7796,
1434 },
1435 {
1436 .compatible = "renesas,r8a774b1-csi2",
1437 .data = &rcar_csi2_info_r8a77965,
1438 },
1439 {
1440 .compatible = "renesas,r8a774c0-csi2",
1441 .data = &rcar_csi2_info_r8a77990,
1442 },
1443 {
1444 .compatible = "renesas,r8a774e1-csi2",
1445 .data = &rcar_csi2_info_r8a7795,
1446 },
1447 {
1448 .compatible = "renesas,r8a7795-csi2",
1449 .data = &rcar_csi2_info_r8a7795,
1450 },
1451 {
1452 .compatible = "renesas,r8a7796-csi2",
1453 .data = &rcar_csi2_info_r8a7796,
1454 },
1455 {
1456 .compatible = "renesas,r8a77961-csi2",
1457 .data = &rcar_csi2_info_r8a77961,
1458 },
1459 {
1460 .compatible = "renesas,r8a77965-csi2",
1461 .data = &rcar_csi2_info_r8a77965,
1462 },
1463 {
1464 .compatible = "renesas,r8a77970-csi2",
1465 .data = &rcar_csi2_info_r8a77970,
1466 },
1467 {
1468 .compatible = "renesas,r8a77980-csi2",
1469 .data = &rcar_csi2_info_r8a77980,
1470 },
1471 {
1472 .compatible = "renesas,r8a77990-csi2",
1473 .data = &rcar_csi2_info_r8a77990,
1474 },
1475 {
1476 .compatible = "renesas,r8a779a0-csi2",
1477 .data = &rcar_csi2_info_r8a779a0,
1478 },
1479 { /* sentinel */ },
1480 };
1481 MODULE_DEVICE_TABLE(of, rcar_csi2_of_table);
1482
1483 static const struct soc_device_attribute r8a7795[] = {
1484 {
1485 .soc_id = "r8a7795", .revision = "ES1.*",
1486 .data = &rcar_csi2_info_r8a7795es1,
1487 },
1488 {
1489 .soc_id = "r8a7795", .revision = "ES2.*",
1490 .data = &rcar_csi2_info_r8a7795es2,
1491 },
1492 { /* sentinel */ }
1493 };
1494
rcsi2_probe(struct platform_device * pdev)1495 static int rcsi2_probe(struct platform_device *pdev)
1496 {
1497 const struct soc_device_attribute *attr;
1498 struct rcar_csi2 *priv;
1499 unsigned int i, num_pads;
1500 int ret;
1501
1502 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1503 if (!priv)
1504 return -ENOMEM;
1505
1506 priv->info = of_device_get_match_data(&pdev->dev);
1507
1508 /*
1509 * The different ES versions of r8a7795 (H3) behave differently but
1510 * share the same compatible string.
1511 */
1512 attr = soc_device_match(r8a7795);
1513 if (attr)
1514 priv->info = attr->data;
1515
1516 priv->dev = &pdev->dev;
1517
1518 mutex_init(&priv->lock);
1519 priv->stream_count = 0;
1520
1521 ret = rcsi2_probe_resources(priv, pdev);
1522 if (ret) {
1523 dev_err(priv->dev, "Failed to get resources\n");
1524 goto error_mutex;
1525 }
1526
1527 platform_set_drvdata(pdev, priv);
1528
1529 ret = rcsi2_parse_dt(priv);
1530 if (ret)
1531 goto error_mutex;
1532
1533 priv->subdev.owner = THIS_MODULE;
1534 priv->subdev.dev = &pdev->dev;
1535 v4l2_subdev_init(&priv->subdev, &rcar_csi2_subdev_ops);
1536 v4l2_set_subdevdata(&priv->subdev, &pdev->dev);
1537 snprintf(priv->subdev.name, V4L2_SUBDEV_NAME_SIZE, "%s %s",
1538 KBUILD_MODNAME, dev_name(&pdev->dev));
1539 priv->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
1540
1541 priv->subdev.entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
1542 priv->subdev.entity.ops = &rcar_csi2_entity_ops;
1543
1544 num_pads = priv->info->use_isp ? 2 : NR_OF_RCAR_CSI2_PAD;
1545
1546 priv->pads[RCAR_CSI2_SINK].flags = MEDIA_PAD_FL_SINK;
1547 for (i = RCAR_CSI2_SOURCE_VC0; i < num_pads; i++)
1548 priv->pads[i].flags = MEDIA_PAD_FL_SOURCE;
1549
1550 ret = media_entity_pads_init(&priv->subdev.entity, num_pads,
1551 priv->pads);
1552 if (ret)
1553 goto error_async;
1554
1555 for (i = 0; i < ARRAY_SIZE(priv->channel_vc); i++)
1556 priv->channel_vc[i] = -1;
1557
1558 pm_runtime_enable(&pdev->dev);
1559
1560 ret = v4l2_async_register_subdev(&priv->subdev);
1561 if (ret < 0)
1562 goto error_async;
1563
1564 dev_info(priv->dev, "%d lanes found\n", priv->lanes);
1565
1566 return 0;
1567
1568 error_async:
1569 v4l2_async_nf_unregister(&priv->notifier);
1570 v4l2_async_nf_cleanup(&priv->notifier);
1571 error_mutex:
1572 mutex_destroy(&priv->lock);
1573
1574 return ret;
1575 }
1576
rcsi2_remove(struct platform_device * pdev)1577 static int rcsi2_remove(struct platform_device *pdev)
1578 {
1579 struct rcar_csi2 *priv = platform_get_drvdata(pdev);
1580
1581 v4l2_async_nf_unregister(&priv->notifier);
1582 v4l2_async_nf_cleanup(&priv->notifier);
1583 v4l2_async_unregister_subdev(&priv->subdev);
1584
1585 pm_runtime_disable(&pdev->dev);
1586
1587 mutex_destroy(&priv->lock);
1588
1589 return 0;
1590 }
1591
1592 static struct platform_driver rcar_csi2_pdrv = {
1593 .remove = rcsi2_remove,
1594 .probe = rcsi2_probe,
1595 .driver = {
1596 .name = "rcar-csi2",
1597 .suppress_bind_attrs = true,
1598 .of_match_table = rcar_csi2_of_table,
1599 },
1600 };
1601
1602 module_platform_driver(rcar_csi2_pdrv);
1603
1604 MODULE_AUTHOR("Niklas Söderlund <niklas.soderlund@ragnatech.se>");
1605 MODULE_DESCRIPTION("Renesas R-Car MIPI CSI-2 receiver driver");
1606 MODULE_LICENSE("GPL");
1607