1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
4 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
5 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
6 * Copyright (C) 2023 EMS Dr. Thomas Wuensche
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/interrupt.h>
12 #include <linux/netdevice.h>
13 #include <linux/delay.h>
14 #include <linux/slab.h>
15 #include <linux/pci.h>
16 #include <linux/can/dev.h>
17 #include <linux/io.h>
18
19 #include "sja1000.h"
20
21 #define DRV_NAME "ems_pci"
22
23 MODULE_AUTHOR("Sebastian Haas <support@ems-wuensche.com>");
24 MODULE_AUTHOR("Gerhard Uttenthaler <uttenthaler@ems-wuensche.com>");
25 MODULE_DESCRIPTION("Socket-CAN driver for EMS CPC-PCI/PCIe/104P CAN cards");
26 MODULE_LICENSE("GPL v2");
27
28 #define EMS_PCI_V1_MAX_CHAN 2
29 #define EMS_PCI_V2_MAX_CHAN 4
30 #define EMS_PCI_V3_MAX_CHAN 4
31 #define EMS_PCI_MAX_CHAN EMS_PCI_V2_MAX_CHAN
32
33 struct ems_pci_card {
34 int version;
35 int channels;
36
37 struct pci_dev *pci_dev;
38 struct net_device *net_dev[EMS_PCI_MAX_CHAN];
39
40 void __iomem *conf_addr;
41 void __iomem *base_addr;
42 };
43
44 #define EMS_PCI_CAN_CLOCK (16000000 / 2)
45
46 /* Register definitions and descriptions are from LinCAN 0.3.3.
47 *
48 * PSB4610 PITA-2 bridge control registers
49 */
50 #define PITA2_ICR 0x00 /* Interrupt Control Register */
51 #define PITA2_ICR_INT0 0x00000002 /* [RC] INT0 Active/Clear */
52 #define PITA2_ICR_INT0_EN 0x00020000 /* [RW] Enable INT0 */
53
54 #define PITA2_MISC 0x1c /* Miscellaneous Register */
55 #define PITA2_MISC_CONFIG 0x04000000 /* Multiplexed parallel interface */
56
57 /* Register definitions for the PLX 9030
58 */
59 #define PLX_ICSR 0x4c /* Interrupt Control/Status register */
60 #define PLX_ICSR_LINTI1_ENA 0x0001 /* LINTi1 Enable */
61 #define PLX_ICSR_PCIINT_ENA 0x0040 /* PCI Interrupt Enable */
62 #define PLX_ICSR_LINTI1_CLR 0x0400 /* Local Edge Triggerable Interrupt Clear */
63 #define PLX_ICSR_ENA_CLR (PLX_ICSR_LINTI1_ENA | PLX_ICSR_PCIINT_ENA | \
64 PLX_ICSR_LINTI1_CLR)
65
66 /* Register definitions for the ASIX99100
67 */
68 #define ASIX_LINTSR 0x28 /* Interrupt Control/Status register */
69 #define ASIX_LINTSR_INT0AC BIT(0) /* Writing 1 enables or clears interrupt */
70
71 #define ASIX_LIEMR 0x24 /* Local Interrupt Enable / Miscellaneous Register */
72 #define ASIX_LIEMR_L0EINTEN BIT(16) /* Local INT0 input assertion enable */
73 #define ASIX_LIEMR_LRST BIT(14) /* Local Reset assert */
74
75 /* The board configuration is probably following:
76 * RX1 is connected to ground.
77 * TX1 is not connected.
78 * CLKO is not connected.
79 * Setting the OCR register to 0xDA is a good idea.
80 * This means normal output mode, push-pull and the correct polarity.
81 */
82 #define EMS_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)
83
84 /* In the CDR register, you should set CBP to 1.
85 * You will probably also want to set the clock divider value to 7
86 * (meaning direct oscillator output) because the second SJA1000 chip
87 * is driven by the first one CLKOUT output.
88 */
89 #define EMS_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK)
90
91 #define EMS_PCI_V1_BASE_BAR 1
92 #define EMS_PCI_V1_CONF_BAR 0
93 #define EMS_PCI_V1_CONF_SIZE 4096 /* size of PITA control area */
94 #define EMS_PCI_V1_CAN_BASE_OFFSET 0x400 /* offset where the controllers start */
95 #define EMS_PCI_V1_CAN_CTRL_SIZE 0x200 /* memory size for each controller */
96
97 #define EMS_PCI_V2_BASE_BAR 2
98 #define EMS_PCI_V2_CONF_BAR 0
99 #define EMS_PCI_V2_CONF_SIZE 128 /* size of PLX control area */
100 #define EMS_PCI_V2_CAN_BASE_OFFSET 0x400 /* offset where the controllers start */
101 #define EMS_PCI_V2_CAN_CTRL_SIZE 0x200 /* memory size for each controller */
102
103 #define EMS_PCI_V3_BASE_BAR 0
104 #define EMS_PCI_V3_CONF_BAR 5
105 #define EMS_PCI_V3_CONF_SIZE 128 /* size of ASIX control area */
106 #define EMS_PCI_V3_CAN_BASE_OFFSET 0x00 /* offset where the controllers starts */
107 #define EMS_PCI_V3_CAN_CTRL_SIZE 0x100 /* memory size for each controller */
108
109 #define EMS_PCI_BASE_SIZE 4096 /* size of controller area */
110
111 #ifndef PCI_VENDOR_ID_ASIX
112 #define PCI_VENDOR_ID_ASIX 0x125b
113 #define PCI_DEVICE_ID_ASIX_9110 0x9110
114 #define PCI_SUBVENDOR_ID_ASIX 0xa000
115 #endif
116 #define PCI_SUBDEVICE_ID_EMS 0x4010
117
118 static const struct pci_device_id ems_pci_tbl[] = {
119 /* CPC-PCI v1 */
120 {PCI_VENDOR_ID_SIEMENS, 0x2104, PCI_ANY_ID, PCI_ANY_ID,},
121 /* CPC-PCI v2 */
122 {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4000},
123 /* CPC-104P v2 */
124 {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4002},
125 /* CPC-PCIe v3 */
126 {PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_9110, PCI_SUBVENDOR_ID_ASIX, PCI_SUBDEVICE_ID_EMS},
127 {0,}
128 };
129 MODULE_DEVICE_TABLE(pci, ems_pci_tbl);
130
131 /* Helper to read internal registers from card logic (not CAN)
132 */
ems_pci_v1_readb(struct ems_pci_card * card,unsigned int port)133 static u8 ems_pci_v1_readb(struct ems_pci_card *card, unsigned int port)
134 {
135 return readb(card->base_addr + (port * 4));
136 }
137
ems_pci_v1_read_reg(const struct sja1000_priv * priv,int port)138 static u8 ems_pci_v1_read_reg(const struct sja1000_priv *priv, int port)
139 {
140 return readb(priv->reg_base + (port * 4));
141 }
142
ems_pci_v1_write_reg(const struct sja1000_priv * priv,int port,u8 val)143 static void ems_pci_v1_write_reg(const struct sja1000_priv *priv,
144 int port, u8 val)
145 {
146 writeb(val, priv->reg_base + (port * 4));
147 }
148
ems_pci_v1_post_irq(const struct sja1000_priv * priv)149 static void ems_pci_v1_post_irq(const struct sja1000_priv *priv)
150 {
151 struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;
152
153 /* reset int flag of pita */
154 writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
155 card->conf_addr + PITA2_ICR);
156 }
157
ems_pci_v2_read_reg(const struct sja1000_priv * priv,int port)158 static u8 ems_pci_v2_read_reg(const struct sja1000_priv *priv, int port)
159 {
160 return readb(priv->reg_base + port);
161 }
162
ems_pci_v2_write_reg(const struct sja1000_priv * priv,int port,u8 val)163 static void ems_pci_v2_write_reg(const struct sja1000_priv *priv,
164 int port, u8 val)
165 {
166 writeb(val, priv->reg_base + port);
167 }
168
ems_pci_v2_post_irq(const struct sja1000_priv * priv)169 static void ems_pci_v2_post_irq(const struct sja1000_priv *priv)
170 {
171 struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;
172
173 writel(PLX_ICSR_ENA_CLR, card->conf_addr + PLX_ICSR);
174 }
175
ems_pci_v3_read_reg(const struct sja1000_priv * priv,int port)176 static u8 ems_pci_v3_read_reg(const struct sja1000_priv *priv, int port)
177 {
178 return readb(priv->reg_base + port);
179 }
180
ems_pci_v3_write_reg(const struct sja1000_priv * priv,int port,u8 val)181 static void ems_pci_v3_write_reg(const struct sja1000_priv *priv,
182 int port, u8 val)
183 {
184 writeb(val, priv->reg_base + port);
185 }
186
ems_pci_v3_post_irq(const struct sja1000_priv * priv)187 static void ems_pci_v3_post_irq(const struct sja1000_priv *priv)
188 {
189 struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;
190
191 writel(ASIX_LINTSR_INT0AC, card->conf_addr + ASIX_LINTSR);
192 }
193
194 /* Check if a CAN controller is present at the specified location
195 * by trying to set 'em into the PeliCAN mode
196 */
ems_pci_check_chan(const struct sja1000_priv * priv)197 static inline int ems_pci_check_chan(const struct sja1000_priv *priv)
198 {
199 unsigned char res;
200
201 /* Make sure SJA1000 is in reset mode */
202 priv->write_reg(priv, SJA1000_MOD, 1);
203
204 priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN);
205
206 /* read reset-values */
207 res = priv->read_reg(priv, SJA1000_CDR);
208
209 if (res == CDR_PELICAN)
210 return 1;
211
212 return 0;
213 }
214
ems_pci_del_card(struct pci_dev * pdev)215 static void ems_pci_del_card(struct pci_dev *pdev)
216 {
217 struct ems_pci_card *card = pci_get_drvdata(pdev);
218 struct net_device *dev;
219 int i = 0;
220
221 for (i = 0; i < card->channels; i++) {
222 dev = card->net_dev[i];
223
224 if (!dev)
225 continue;
226
227 dev_info(&pdev->dev, "Removing %s.\n", dev->name);
228 unregister_sja1000dev(dev);
229 free_sja1000dev(dev);
230 }
231
232 if (card->base_addr)
233 pci_iounmap(card->pci_dev, card->base_addr);
234
235 if (card->conf_addr)
236 pci_iounmap(card->pci_dev, card->conf_addr);
237
238 kfree(card);
239
240 pci_disable_device(pdev);
241 }
242
ems_pci_card_reset(struct ems_pci_card * card)243 static void ems_pci_card_reset(struct ems_pci_card *card)
244 {
245 /* Request board reset */
246 writeb(0, card->base_addr);
247 }
248
249 /* Probe PCI device for EMS CAN signature and register each available
250 * CAN channel to SJA1000 Socket-CAN subsystem.
251 */
ems_pci_add_card(struct pci_dev * pdev,const struct pci_device_id * ent)252 static int ems_pci_add_card(struct pci_dev *pdev,
253 const struct pci_device_id *ent)
254 {
255 struct sja1000_priv *priv;
256 struct net_device *dev;
257 struct ems_pci_card *card;
258 int max_chan, conf_size, base_bar, conf_bar;
259 int err, i;
260
261 /* Enabling PCI device */
262 if (pci_enable_device(pdev) < 0) {
263 dev_err(&pdev->dev, "Enabling PCI device failed\n");
264 return -ENODEV;
265 }
266
267 /* Allocating card structures to hold addresses, ... */
268 card = kzalloc(sizeof(*card), GFP_KERNEL);
269 if (!card) {
270 pci_disable_device(pdev);
271 return -ENOMEM;
272 }
273
274 pci_set_drvdata(pdev, card);
275
276 card->pci_dev = pdev;
277
278 card->channels = 0;
279
280 if (pdev->vendor == PCI_VENDOR_ID_ASIX) {
281 card->version = 3; /* CPC-PCI v3 */
282 max_chan = EMS_PCI_V3_MAX_CHAN;
283 base_bar = EMS_PCI_V3_BASE_BAR;
284 conf_bar = EMS_PCI_V3_CONF_BAR;
285 conf_size = EMS_PCI_V3_CONF_SIZE;
286 } else if (pdev->vendor == PCI_VENDOR_ID_PLX) {
287 card->version = 2; /* CPC-PCI v2 */
288 max_chan = EMS_PCI_V2_MAX_CHAN;
289 base_bar = EMS_PCI_V2_BASE_BAR;
290 conf_bar = EMS_PCI_V2_CONF_BAR;
291 conf_size = EMS_PCI_V2_CONF_SIZE;
292 } else {
293 card->version = 1; /* CPC-PCI v1 */
294 max_chan = EMS_PCI_V1_MAX_CHAN;
295 base_bar = EMS_PCI_V1_BASE_BAR;
296 conf_bar = EMS_PCI_V1_CONF_BAR;
297 conf_size = EMS_PCI_V1_CONF_SIZE;
298 }
299
300 /* Remap configuration space and controller memory area */
301 card->conf_addr = pci_iomap(pdev, conf_bar, conf_size);
302 if (!card->conf_addr) {
303 err = -ENOMEM;
304 goto failure_cleanup;
305 }
306
307 card->base_addr = pci_iomap(pdev, base_bar, EMS_PCI_BASE_SIZE);
308 if (!card->base_addr) {
309 err = -ENOMEM;
310 goto failure_cleanup;
311 }
312
313 if (card->version == 1) {
314 /* Configure PITA-2 parallel interface (enable MUX) */
315 writel(PITA2_MISC_CONFIG, card->conf_addr + PITA2_MISC);
316
317 /* Check for unique EMS CAN signature */
318 if (ems_pci_v1_readb(card, 0) != 0x55 ||
319 ems_pci_v1_readb(card, 1) != 0xAA ||
320 ems_pci_v1_readb(card, 2) != 0x01 ||
321 ems_pci_v1_readb(card, 3) != 0xCB ||
322 ems_pci_v1_readb(card, 4) != 0x11) {
323 dev_err(&pdev->dev,
324 "Not EMS Dr. Thomas Wuensche interface\n");
325 err = -ENODEV;
326 goto failure_cleanup;
327 }
328 }
329
330 if (card->version == 3) {
331 /* ASIX chip asserts local reset to CAN controllers
332 * after bootup until it is deasserted
333 */
334 writel(readl(card->conf_addr + ASIX_LIEMR) & ~ASIX_LIEMR_LRST,
335 card->conf_addr + ASIX_LIEMR);
336 }
337
338 ems_pci_card_reset(card);
339
340 /* Detect available channels */
341 for (i = 0; i < max_chan; i++) {
342 dev = alloc_sja1000dev(0);
343 if (!dev) {
344 err = -ENOMEM;
345 goto failure_cleanup;
346 }
347
348 card->net_dev[i] = dev;
349 priv = netdev_priv(dev);
350 priv->priv = card;
351 priv->irq_flags = IRQF_SHARED;
352
353 dev->irq = pdev->irq;
354
355 if (card->version == 1) {
356 priv->read_reg = ems_pci_v1_read_reg;
357 priv->write_reg = ems_pci_v1_write_reg;
358 priv->post_irq = ems_pci_v1_post_irq;
359 priv->reg_base = card->base_addr + EMS_PCI_V1_CAN_BASE_OFFSET
360 + (i * EMS_PCI_V1_CAN_CTRL_SIZE);
361 } else if (card->version == 2) {
362 priv->read_reg = ems_pci_v2_read_reg;
363 priv->write_reg = ems_pci_v2_write_reg;
364 priv->post_irq = ems_pci_v2_post_irq;
365 priv->reg_base = card->base_addr + EMS_PCI_V2_CAN_BASE_OFFSET
366 + (i * EMS_PCI_V2_CAN_CTRL_SIZE);
367 } else {
368 priv->read_reg = ems_pci_v3_read_reg;
369 priv->write_reg = ems_pci_v3_write_reg;
370 priv->post_irq = ems_pci_v3_post_irq;
371 priv->reg_base = card->base_addr + EMS_PCI_V3_CAN_BASE_OFFSET
372 + (i * EMS_PCI_V3_CAN_CTRL_SIZE);
373 }
374
375 /* Check if channel is present */
376 if (ems_pci_check_chan(priv)) {
377 priv->can.clock.freq = EMS_PCI_CAN_CLOCK;
378 priv->ocr = EMS_PCI_OCR;
379 priv->cdr = EMS_PCI_CDR;
380
381 SET_NETDEV_DEV(dev, &pdev->dev);
382 dev->dev_id = i;
383
384 if (card->version == 1) {
385 /* reset int flag of pita */
386 writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
387 card->conf_addr + PITA2_ICR);
388 } else if (card->version == 2) {
389 /* enable IRQ in PLX 9030 */
390 writel(PLX_ICSR_ENA_CLR,
391 card->conf_addr + PLX_ICSR);
392 } else {
393 /* Enable IRQ in AX99100 */
394 writel(ASIX_LINTSR_INT0AC, card->conf_addr + ASIX_LINTSR);
395 /* Enable local INT0 input enable */
396 writel(readl(card->conf_addr + ASIX_LIEMR) | ASIX_LIEMR_L0EINTEN,
397 card->conf_addr + ASIX_LIEMR);
398 }
399
400 /* Register SJA1000 device */
401 err = register_sja1000dev(dev);
402 if (err) {
403 dev_err(&pdev->dev,
404 "Registering device failed: %pe\n",
405 ERR_PTR(err));
406 free_sja1000dev(dev);
407 goto failure_cleanup;
408 }
409
410 card->channels++;
411
412 dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d\n",
413 i + 1, priv->reg_base, dev->irq);
414 } else {
415 free_sja1000dev(dev);
416 }
417 }
418
419 return 0;
420
421 failure_cleanup:
422 dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err);
423
424 ems_pci_del_card(pdev);
425
426 return err;
427 }
428
429 static struct pci_driver ems_pci_driver = {
430 .name = DRV_NAME,
431 .id_table = ems_pci_tbl,
432 .probe = ems_pci_add_card,
433 .remove = ems_pci_del_card,
434 };
435
436 module_pci_driver(ems_pci_driver);
437