1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Microchip switch driver main logic
4 *
5 * Copyright (C) 2017-2019 Microchip Technology Inc.
6 */
7
8 #include <linux/delay.h>
9 #include <linux/dsa/ksz_common.h>
10 #include <linux/export.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/platform_data/microchip-ksz.h>
15 #include <linux/phy.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_bridge.h>
18 #include <linux/if_vlan.h>
19 #include <linux/irq.h>
20 #include <linux/irqdomain.h>
21 #include <linux/of_mdio.h>
22 #include <linux/of_device.h>
23 #include <linux/of_net.h>
24 #include <linux/micrel_phy.h>
25 #include <net/dsa.h>
26 #include <net/pkt_cls.h>
27 #include <net/switchdev.h>
28
29 #include "ksz_common.h"
30 #include "ksz_ptp.h"
31 #include "ksz8.h"
32 #include "ksz9477.h"
33 #include "lan937x.h"
34
35 #define KSZ_CBS_ENABLE ((MTI_SCHEDULE_STRICT_PRIO << MTI_SCHEDULE_MODE_S) | \
36 (MTI_SHAPING_SRP << MTI_SHAPING_S))
37 #define KSZ_CBS_DISABLE ((MTI_SCHEDULE_WRR << MTI_SCHEDULE_MODE_S) |\
38 (MTI_SHAPING_OFF << MTI_SHAPING_S))
39 #define MIB_COUNTER_NUM 0x20
40
41 struct ksz_stats_raw {
42 u64 rx_hi;
43 u64 rx_undersize;
44 u64 rx_fragments;
45 u64 rx_oversize;
46 u64 rx_jabbers;
47 u64 rx_symbol_err;
48 u64 rx_crc_err;
49 u64 rx_align_err;
50 u64 rx_mac_ctrl;
51 u64 rx_pause;
52 u64 rx_bcast;
53 u64 rx_mcast;
54 u64 rx_ucast;
55 u64 rx_64_or_less;
56 u64 rx_65_127;
57 u64 rx_128_255;
58 u64 rx_256_511;
59 u64 rx_512_1023;
60 u64 rx_1024_1522;
61 u64 rx_1523_2000;
62 u64 rx_2001;
63 u64 tx_hi;
64 u64 tx_late_col;
65 u64 tx_pause;
66 u64 tx_bcast;
67 u64 tx_mcast;
68 u64 tx_ucast;
69 u64 tx_deferred;
70 u64 tx_total_col;
71 u64 tx_exc_col;
72 u64 tx_single_col;
73 u64 tx_mult_col;
74 u64 rx_total;
75 u64 tx_total;
76 u64 rx_discards;
77 u64 tx_discards;
78 };
79
80 struct ksz88xx_stats_raw {
81 u64 rx;
82 u64 rx_hi;
83 u64 rx_undersize;
84 u64 rx_fragments;
85 u64 rx_oversize;
86 u64 rx_jabbers;
87 u64 rx_symbol_err;
88 u64 rx_crc_err;
89 u64 rx_align_err;
90 u64 rx_mac_ctrl;
91 u64 rx_pause;
92 u64 rx_bcast;
93 u64 rx_mcast;
94 u64 rx_ucast;
95 u64 rx_64_or_less;
96 u64 rx_65_127;
97 u64 rx_128_255;
98 u64 rx_256_511;
99 u64 rx_512_1023;
100 u64 rx_1024_1522;
101 u64 tx;
102 u64 tx_hi;
103 u64 tx_late_col;
104 u64 tx_pause;
105 u64 tx_bcast;
106 u64 tx_mcast;
107 u64 tx_ucast;
108 u64 tx_deferred;
109 u64 tx_total_col;
110 u64 tx_exc_col;
111 u64 tx_single_col;
112 u64 tx_mult_col;
113 u64 rx_discards;
114 u64 tx_discards;
115 };
116
117 static const struct ksz_mib_names ksz88xx_mib_names[] = {
118 { 0x00, "rx" },
119 { 0x01, "rx_hi" },
120 { 0x02, "rx_undersize" },
121 { 0x03, "rx_fragments" },
122 { 0x04, "rx_oversize" },
123 { 0x05, "rx_jabbers" },
124 { 0x06, "rx_symbol_err" },
125 { 0x07, "rx_crc_err" },
126 { 0x08, "rx_align_err" },
127 { 0x09, "rx_mac_ctrl" },
128 { 0x0a, "rx_pause" },
129 { 0x0b, "rx_bcast" },
130 { 0x0c, "rx_mcast" },
131 { 0x0d, "rx_ucast" },
132 { 0x0e, "rx_64_or_less" },
133 { 0x0f, "rx_65_127" },
134 { 0x10, "rx_128_255" },
135 { 0x11, "rx_256_511" },
136 { 0x12, "rx_512_1023" },
137 { 0x13, "rx_1024_1522" },
138 { 0x14, "tx" },
139 { 0x15, "tx_hi" },
140 { 0x16, "tx_late_col" },
141 { 0x17, "tx_pause" },
142 { 0x18, "tx_bcast" },
143 { 0x19, "tx_mcast" },
144 { 0x1a, "tx_ucast" },
145 { 0x1b, "tx_deferred" },
146 { 0x1c, "tx_total_col" },
147 { 0x1d, "tx_exc_col" },
148 { 0x1e, "tx_single_col" },
149 { 0x1f, "tx_mult_col" },
150 { 0x100, "rx_discards" },
151 { 0x101, "tx_discards" },
152 };
153
154 static const struct ksz_mib_names ksz9477_mib_names[] = {
155 { 0x00, "rx_hi" },
156 { 0x01, "rx_undersize" },
157 { 0x02, "rx_fragments" },
158 { 0x03, "rx_oversize" },
159 { 0x04, "rx_jabbers" },
160 { 0x05, "rx_symbol_err" },
161 { 0x06, "rx_crc_err" },
162 { 0x07, "rx_align_err" },
163 { 0x08, "rx_mac_ctrl" },
164 { 0x09, "rx_pause" },
165 { 0x0A, "rx_bcast" },
166 { 0x0B, "rx_mcast" },
167 { 0x0C, "rx_ucast" },
168 { 0x0D, "rx_64_or_less" },
169 { 0x0E, "rx_65_127" },
170 { 0x0F, "rx_128_255" },
171 { 0x10, "rx_256_511" },
172 { 0x11, "rx_512_1023" },
173 { 0x12, "rx_1024_1522" },
174 { 0x13, "rx_1523_2000" },
175 { 0x14, "rx_2001" },
176 { 0x15, "tx_hi" },
177 { 0x16, "tx_late_col" },
178 { 0x17, "tx_pause" },
179 { 0x18, "tx_bcast" },
180 { 0x19, "tx_mcast" },
181 { 0x1A, "tx_ucast" },
182 { 0x1B, "tx_deferred" },
183 { 0x1C, "tx_total_col" },
184 { 0x1D, "tx_exc_col" },
185 { 0x1E, "tx_single_col" },
186 { 0x1F, "tx_mult_col" },
187 { 0x80, "rx_total" },
188 { 0x81, "tx_total" },
189 { 0x82, "rx_discards" },
190 { 0x83, "tx_discards" },
191 };
192
193 static const struct ksz_dev_ops ksz8_dev_ops = {
194 .setup = ksz8_setup,
195 .get_port_addr = ksz8_get_port_addr,
196 .cfg_port_member = ksz8_cfg_port_member,
197 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
198 .port_setup = ksz8_port_setup,
199 .r_phy = ksz8_r_phy,
200 .w_phy = ksz8_w_phy,
201 .r_mib_cnt = ksz8_r_mib_cnt,
202 .r_mib_pkt = ksz8_r_mib_pkt,
203 .r_mib_stat64 = ksz88xx_r_mib_stats64,
204 .freeze_mib = ksz8_freeze_mib,
205 .port_init_cnt = ksz8_port_init_cnt,
206 .fdb_dump = ksz8_fdb_dump,
207 .mdb_add = ksz8_mdb_add,
208 .mdb_del = ksz8_mdb_del,
209 .vlan_filtering = ksz8_port_vlan_filtering,
210 .vlan_add = ksz8_port_vlan_add,
211 .vlan_del = ksz8_port_vlan_del,
212 .mirror_add = ksz8_port_mirror_add,
213 .mirror_del = ksz8_port_mirror_del,
214 .get_caps = ksz8_get_caps,
215 .config_cpu_port = ksz8_config_cpu_port,
216 .enable_stp_addr = ksz8_enable_stp_addr,
217 .reset = ksz8_reset_switch,
218 .init = ksz8_switch_init,
219 .exit = ksz8_switch_exit,
220 .change_mtu = ksz8_change_mtu,
221 };
222
223 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port,
224 unsigned int mode,
225 phy_interface_t interface,
226 struct phy_device *phydev, int speed,
227 int duplex, bool tx_pause,
228 bool rx_pause);
229
230 static const struct ksz_dev_ops ksz9477_dev_ops = {
231 .setup = ksz9477_setup,
232 .get_port_addr = ksz9477_get_port_addr,
233 .cfg_port_member = ksz9477_cfg_port_member,
234 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
235 .port_setup = ksz9477_port_setup,
236 .set_ageing_time = ksz9477_set_ageing_time,
237 .r_phy = ksz9477_r_phy,
238 .w_phy = ksz9477_w_phy,
239 .r_mib_cnt = ksz9477_r_mib_cnt,
240 .r_mib_pkt = ksz9477_r_mib_pkt,
241 .r_mib_stat64 = ksz_r_mib_stats64,
242 .freeze_mib = ksz9477_freeze_mib,
243 .port_init_cnt = ksz9477_port_init_cnt,
244 .vlan_filtering = ksz9477_port_vlan_filtering,
245 .vlan_add = ksz9477_port_vlan_add,
246 .vlan_del = ksz9477_port_vlan_del,
247 .mirror_add = ksz9477_port_mirror_add,
248 .mirror_del = ksz9477_port_mirror_del,
249 .get_caps = ksz9477_get_caps,
250 .fdb_dump = ksz9477_fdb_dump,
251 .fdb_add = ksz9477_fdb_add,
252 .fdb_del = ksz9477_fdb_del,
253 .mdb_add = ksz9477_mdb_add,
254 .mdb_del = ksz9477_mdb_del,
255 .change_mtu = ksz9477_change_mtu,
256 .phylink_mac_link_up = ksz9477_phylink_mac_link_up,
257 .config_cpu_port = ksz9477_config_cpu_port,
258 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc,
259 .enable_stp_addr = ksz9477_enable_stp_addr,
260 .reset = ksz9477_reset_switch,
261 .init = ksz9477_switch_init,
262 .exit = ksz9477_switch_exit,
263 };
264
265 static const struct ksz_dev_ops lan937x_dev_ops = {
266 .setup = lan937x_setup,
267 .teardown = lan937x_teardown,
268 .get_port_addr = ksz9477_get_port_addr,
269 .cfg_port_member = ksz9477_cfg_port_member,
270 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
271 .port_setup = lan937x_port_setup,
272 .set_ageing_time = lan937x_set_ageing_time,
273 .r_phy = lan937x_r_phy,
274 .w_phy = lan937x_w_phy,
275 .r_mib_cnt = ksz9477_r_mib_cnt,
276 .r_mib_pkt = ksz9477_r_mib_pkt,
277 .r_mib_stat64 = ksz_r_mib_stats64,
278 .freeze_mib = ksz9477_freeze_mib,
279 .port_init_cnt = ksz9477_port_init_cnt,
280 .vlan_filtering = ksz9477_port_vlan_filtering,
281 .vlan_add = ksz9477_port_vlan_add,
282 .vlan_del = ksz9477_port_vlan_del,
283 .mirror_add = ksz9477_port_mirror_add,
284 .mirror_del = ksz9477_port_mirror_del,
285 .get_caps = lan937x_phylink_get_caps,
286 .setup_rgmii_delay = lan937x_setup_rgmii_delay,
287 .fdb_dump = ksz9477_fdb_dump,
288 .fdb_add = ksz9477_fdb_add,
289 .fdb_del = ksz9477_fdb_del,
290 .mdb_add = ksz9477_mdb_add,
291 .mdb_del = ksz9477_mdb_del,
292 .change_mtu = lan937x_change_mtu,
293 .phylink_mac_link_up = ksz9477_phylink_mac_link_up,
294 .config_cpu_port = lan937x_config_cpu_port,
295 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc,
296 .enable_stp_addr = ksz9477_enable_stp_addr,
297 .reset = lan937x_reset_switch,
298 .init = lan937x_switch_init,
299 .exit = lan937x_switch_exit,
300 };
301
302 static const u16 ksz8795_regs[] = {
303 [REG_IND_CTRL_0] = 0x6E,
304 [REG_IND_DATA_8] = 0x70,
305 [REG_IND_DATA_CHECK] = 0x72,
306 [REG_IND_DATA_HI] = 0x71,
307 [REG_IND_DATA_LO] = 0x75,
308 [REG_IND_MIB_CHECK] = 0x74,
309 [REG_IND_BYTE] = 0xA0,
310 [P_FORCE_CTRL] = 0x0C,
311 [P_LINK_STATUS] = 0x0E,
312 [P_LOCAL_CTRL] = 0x07,
313 [P_NEG_RESTART_CTRL] = 0x0D,
314 [P_REMOTE_STATUS] = 0x08,
315 [P_SPEED_STATUS] = 0x09,
316 [S_TAIL_TAG_CTRL] = 0x0C,
317 [P_STP_CTRL] = 0x02,
318 [S_START_CTRL] = 0x01,
319 [S_BROADCAST_CTRL] = 0x06,
320 [S_MULTICAST_CTRL] = 0x04,
321 [P_XMII_CTRL_0] = 0x06,
322 [P_XMII_CTRL_1] = 0x56,
323 };
324
325 static const u32 ksz8795_masks[] = {
326 [PORT_802_1P_REMAPPING] = BIT(7),
327 [SW_TAIL_TAG_ENABLE] = BIT(1),
328 [MIB_COUNTER_OVERFLOW] = BIT(6),
329 [MIB_COUNTER_VALID] = BIT(5),
330 [VLAN_TABLE_FID] = GENMASK(6, 0),
331 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
332 [VLAN_TABLE_VALID] = BIT(12),
333 [STATIC_MAC_TABLE_VALID] = BIT(21),
334 [STATIC_MAC_TABLE_USE_FID] = BIT(23),
335 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
336 [STATIC_MAC_TABLE_OVERRIDE] = BIT(26),
337 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(24, 20),
338 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),
339 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(8),
340 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
341 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
342 [DYNAMIC_MAC_TABLE_FID] = GENMASK(26, 20),
343 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
344 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),
345 [P_MII_TX_FLOW_CTRL] = BIT(5),
346 [P_MII_RX_FLOW_CTRL] = BIT(5),
347 };
348
349 static const u8 ksz8795_xmii_ctrl0[] = {
350 [P_MII_100MBIT] = 0,
351 [P_MII_10MBIT] = 1,
352 [P_MII_FULL_DUPLEX] = 0,
353 [P_MII_HALF_DUPLEX] = 1,
354 };
355
356 static const u8 ksz8795_xmii_ctrl1[] = {
357 [P_RGMII_SEL] = 3,
358 [P_GMII_SEL] = 2,
359 [P_RMII_SEL] = 1,
360 [P_MII_SEL] = 0,
361 [P_GMII_1GBIT] = 1,
362 [P_GMII_NOT_1GBIT] = 0,
363 };
364
365 static const u8 ksz8795_shifts[] = {
366 [VLAN_TABLE_MEMBERSHIP_S] = 7,
367 [VLAN_TABLE] = 16,
368 [STATIC_MAC_FWD_PORTS] = 16,
369 [STATIC_MAC_FID] = 24,
370 [DYNAMIC_MAC_ENTRIES_H] = 3,
371 [DYNAMIC_MAC_ENTRIES] = 29,
372 [DYNAMIC_MAC_FID] = 16,
373 [DYNAMIC_MAC_TIMESTAMP] = 27,
374 [DYNAMIC_MAC_SRC_PORT] = 24,
375 };
376
377 static const u16 ksz8863_regs[] = {
378 [REG_IND_CTRL_0] = 0x79,
379 [REG_IND_DATA_8] = 0x7B,
380 [REG_IND_DATA_CHECK] = 0x7B,
381 [REG_IND_DATA_HI] = 0x7C,
382 [REG_IND_DATA_LO] = 0x80,
383 [REG_IND_MIB_CHECK] = 0x80,
384 [P_FORCE_CTRL] = 0x0C,
385 [P_LINK_STATUS] = 0x0E,
386 [P_LOCAL_CTRL] = 0x0C,
387 [P_NEG_RESTART_CTRL] = 0x0D,
388 [P_REMOTE_STATUS] = 0x0E,
389 [P_SPEED_STATUS] = 0x0F,
390 [S_TAIL_TAG_CTRL] = 0x03,
391 [P_STP_CTRL] = 0x02,
392 [S_START_CTRL] = 0x01,
393 [S_BROADCAST_CTRL] = 0x06,
394 [S_MULTICAST_CTRL] = 0x04,
395 };
396
397 static const u32 ksz8863_masks[] = {
398 [PORT_802_1P_REMAPPING] = BIT(3),
399 [SW_TAIL_TAG_ENABLE] = BIT(6),
400 [MIB_COUNTER_OVERFLOW] = BIT(7),
401 [MIB_COUNTER_VALID] = BIT(6),
402 [VLAN_TABLE_FID] = GENMASK(15, 12),
403 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),
404 [VLAN_TABLE_VALID] = BIT(19),
405 [STATIC_MAC_TABLE_VALID] = BIT(19),
406 [STATIC_MAC_TABLE_USE_FID] = BIT(21),
407 [STATIC_MAC_TABLE_FID] = GENMASK(29, 26),
408 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20),
409 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16),
410 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(5, 0),
411 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7),
412 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
413 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 28),
414 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16),
415 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20),
416 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22),
417 };
418
419 static u8 ksz8863_shifts[] = {
420 [VLAN_TABLE_MEMBERSHIP_S] = 16,
421 [STATIC_MAC_FWD_PORTS] = 16,
422 [STATIC_MAC_FID] = 22,
423 [DYNAMIC_MAC_ENTRIES_H] = 3,
424 [DYNAMIC_MAC_ENTRIES] = 24,
425 [DYNAMIC_MAC_FID] = 16,
426 [DYNAMIC_MAC_TIMESTAMP] = 24,
427 [DYNAMIC_MAC_SRC_PORT] = 20,
428 };
429
430 static const u16 ksz9477_regs[] = {
431 [P_STP_CTRL] = 0x0B04,
432 [S_START_CTRL] = 0x0300,
433 [S_BROADCAST_CTRL] = 0x0332,
434 [S_MULTICAST_CTRL] = 0x0331,
435 [P_XMII_CTRL_0] = 0x0300,
436 [P_XMII_CTRL_1] = 0x0301,
437 };
438
439 static const u32 ksz9477_masks[] = {
440 [ALU_STAT_WRITE] = 0,
441 [ALU_STAT_READ] = 1,
442 [P_MII_TX_FLOW_CTRL] = BIT(5),
443 [P_MII_RX_FLOW_CTRL] = BIT(3),
444 };
445
446 static const u8 ksz9477_shifts[] = {
447 [ALU_STAT_INDEX] = 16,
448 };
449
450 static const u8 ksz9477_xmii_ctrl0[] = {
451 [P_MII_100MBIT] = 1,
452 [P_MII_10MBIT] = 0,
453 [P_MII_FULL_DUPLEX] = 1,
454 [P_MII_HALF_DUPLEX] = 0,
455 };
456
457 static const u8 ksz9477_xmii_ctrl1[] = {
458 [P_RGMII_SEL] = 0,
459 [P_RMII_SEL] = 1,
460 [P_GMII_SEL] = 2,
461 [P_MII_SEL] = 3,
462 [P_GMII_1GBIT] = 0,
463 [P_GMII_NOT_1GBIT] = 1,
464 };
465
466 static const u32 lan937x_masks[] = {
467 [ALU_STAT_WRITE] = 1,
468 [ALU_STAT_READ] = 2,
469 [P_MII_TX_FLOW_CTRL] = BIT(5),
470 [P_MII_RX_FLOW_CTRL] = BIT(3),
471 };
472
473 static const u8 lan937x_shifts[] = {
474 [ALU_STAT_INDEX] = 8,
475 };
476
477 static const struct regmap_range ksz8563_valid_regs[] = {
478 regmap_reg_range(0x0000, 0x0003),
479 regmap_reg_range(0x0006, 0x0006),
480 regmap_reg_range(0x000f, 0x001f),
481 regmap_reg_range(0x0100, 0x0100),
482 regmap_reg_range(0x0104, 0x0107),
483 regmap_reg_range(0x010d, 0x010d),
484 regmap_reg_range(0x0110, 0x0113),
485 regmap_reg_range(0x0120, 0x012b),
486 regmap_reg_range(0x0201, 0x0201),
487 regmap_reg_range(0x0210, 0x0213),
488 regmap_reg_range(0x0300, 0x0300),
489 regmap_reg_range(0x0302, 0x031b),
490 regmap_reg_range(0x0320, 0x032b),
491 regmap_reg_range(0x0330, 0x0336),
492 regmap_reg_range(0x0338, 0x033e),
493 regmap_reg_range(0x0340, 0x035f),
494 regmap_reg_range(0x0370, 0x0370),
495 regmap_reg_range(0x0378, 0x0378),
496 regmap_reg_range(0x037c, 0x037d),
497 regmap_reg_range(0x0390, 0x0393),
498 regmap_reg_range(0x0400, 0x040e),
499 regmap_reg_range(0x0410, 0x042f),
500 regmap_reg_range(0x0500, 0x0519),
501 regmap_reg_range(0x0520, 0x054b),
502 regmap_reg_range(0x0550, 0x05b3),
503
504 /* port 1 */
505 regmap_reg_range(0x1000, 0x1001),
506 regmap_reg_range(0x1004, 0x100b),
507 regmap_reg_range(0x1013, 0x1013),
508 regmap_reg_range(0x1017, 0x1017),
509 regmap_reg_range(0x101b, 0x101b),
510 regmap_reg_range(0x101f, 0x1021),
511 regmap_reg_range(0x1030, 0x1030),
512 regmap_reg_range(0x1100, 0x1111),
513 regmap_reg_range(0x111a, 0x111d),
514 regmap_reg_range(0x1122, 0x1127),
515 regmap_reg_range(0x112a, 0x112b),
516 regmap_reg_range(0x1136, 0x1139),
517 regmap_reg_range(0x113e, 0x113f),
518 regmap_reg_range(0x1400, 0x1401),
519 regmap_reg_range(0x1403, 0x1403),
520 regmap_reg_range(0x1410, 0x1417),
521 regmap_reg_range(0x1420, 0x1423),
522 regmap_reg_range(0x1500, 0x1507),
523 regmap_reg_range(0x1600, 0x1612),
524 regmap_reg_range(0x1800, 0x180f),
525 regmap_reg_range(0x1900, 0x1907),
526 regmap_reg_range(0x1914, 0x191b),
527 regmap_reg_range(0x1a00, 0x1a03),
528 regmap_reg_range(0x1a04, 0x1a08),
529 regmap_reg_range(0x1b00, 0x1b01),
530 regmap_reg_range(0x1b04, 0x1b04),
531 regmap_reg_range(0x1c00, 0x1c05),
532 regmap_reg_range(0x1c08, 0x1c1b),
533
534 /* port 2 */
535 regmap_reg_range(0x2000, 0x2001),
536 regmap_reg_range(0x2004, 0x200b),
537 regmap_reg_range(0x2013, 0x2013),
538 regmap_reg_range(0x2017, 0x2017),
539 regmap_reg_range(0x201b, 0x201b),
540 regmap_reg_range(0x201f, 0x2021),
541 regmap_reg_range(0x2030, 0x2030),
542 regmap_reg_range(0x2100, 0x2111),
543 regmap_reg_range(0x211a, 0x211d),
544 regmap_reg_range(0x2122, 0x2127),
545 regmap_reg_range(0x212a, 0x212b),
546 regmap_reg_range(0x2136, 0x2139),
547 regmap_reg_range(0x213e, 0x213f),
548 regmap_reg_range(0x2400, 0x2401),
549 regmap_reg_range(0x2403, 0x2403),
550 regmap_reg_range(0x2410, 0x2417),
551 regmap_reg_range(0x2420, 0x2423),
552 regmap_reg_range(0x2500, 0x2507),
553 regmap_reg_range(0x2600, 0x2612),
554 regmap_reg_range(0x2800, 0x280f),
555 regmap_reg_range(0x2900, 0x2907),
556 regmap_reg_range(0x2914, 0x291b),
557 regmap_reg_range(0x2a00, 0x2a03),
558 regmap_reg_range(0x2a04, 0x2a08),
559 regmap_reg_range(0x2b00, 0x2b01),
560 regmap_reg_range(0x2b04, 0x2b04),
561 regmap_reg_range(0x2c00, 0x2c05),
562 regmap_reg_range(0x2c08, 0x2c1b),
563
564 /* port 3 */
565 regmap_reg_range(0x3000, 0x3001),
566 regmap_reg_range(0x3004, 0x300b),
567 regmap_reg_range(0x3013, 0x3013),
568 regmap_reg_range(0x3017, 0x3017),
569 regmap_reg_range(0x301b, 0x301b),
570 regmap_reg_range(0x301f, 0x3021),
571 regmap_reg_range(0x3030, 0x3030),
572 regmap_reg_range(0x3300, 0x3301),
573 regmap_reg_range(0x3303, 0x3303),
574 regmap_reg_range(0x3400, 0x3401),
575 regmap_reg_range(0x3403, 0x3403),
576 regmap_reg_range(0x3410, 0x3417),
577 regmap_reg_range(0x3420, 0x3423),
578 regmap_reg_range(0x3500, 0x3507),
579 regmap_reg_range(0x3600, 0x3612),
580 regmap_reg_range(0x3800, 0x380f),
581 regmap_reg_range(0x3900, 0x3907),
582 regmap_reg_range(0x3914, 0x391b),
583 regmap_reg_range(0x3a00, 0x3a03),
584 regmap_reg_range(0x3a04, 0x3a08),
585 regmap_reg_range(0x3b00, 0x3b01),
586 regmap_reg_range(0x3b04, 0x3b04),
587 regmap_reg_range(0x3c00, 0x3c05),
588 regmap_reg_range(0x3c08, 0x3c1b),
589 };
590
591 static const struct regmap_access_table ksz8563_register_set = {
592 .yes_ranges = ksz8563_valid_regs,
593 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs),
594 };
595
596 static const struct regmap_range ksz9477_valid_regs[] = {
597 regmap_reg_range(0x0000, 0x0003),
598 regmap_reg_range(0x0006, 0x0006),
599 regmap_reg_range(0x0010, 0x001f),
600 regmap_reg_range(0x0100, 0x0100),
601 regmap_reg_range(0x0103, 0x0107),
602 regmap_reg_range(0x010d, 0x010d),
603 regmap_reg_range(0x0110, 0x0113),
604 regmap_reg_range(0x0120, 0x012b),
605 regmap_reg_range(0x0201, 0x0201),
606 regmap_reg_range(0x0210, 0x0213),
607 regmap_reg_range(0x0300, 0x0300),
608 regmap_reg_range(0x0302, 0x031b),
609 regmap_reg_range(0x0320, 0x032b),
610 regmap_reg_range(0x0330, 0x0336),
611 regmap_reg_range(0x0338, 0x033b),
612 regmap_reg_range(0x033e, 0x033e),
613 regmap_reg_range(0x0340, 0x035f),
614 regmap_reg_range(0x0370, 0x0370),
615 regmap_reg_range(0x0378, 0x0378),
616 regmap_reg_range(0x037c, 0x037d),
617 regmap_reg_range(0x0390, 0x0393),
618 regmap_reg_range(0x0400, 0x040e),
619 regmap_reg_range(0x0410, 0x042f),
620 regmap_reg_range(0x0444, 0x044b),
621 regmap_reg_range(0x0450, 0x046f),
622 regmap_reg_range(0x0500, 0x0519),
623 regmap_reg_range(0x0520, 0x054b),
624 regmap_reg_range(0x0550, 0x05b3),
625 regmap_reg_range(0x0604, 0x060b),
626 regmap_reg_range(0x0610, 0x0612),
627 regmap_reg_range(0x0614, 0x062c),
628 regmap_reg_range(0x0640, 0x0645),
629 regmap_reg_range(0x0648, 0x064d),
630
631 /* port 1 */
632 regmap_reg_range(0x1000, 0x1001),
633 regmap_reg_range(0x1013, 0x1013),
634 regmap_reg_range(0x1017, 0x1017),
635 regmap_reg_range(0x101b, 0x101b),
636 regmap_reg_range(0x101f, 0x1020),
637 regmap_reg_range(0x1030, 0x1030),
638 regmap_reg_range(0x1100, 0x1115),
639 regmap_reg_range(0x111a, 0x111f),
640 regmap_reg_range(0x1122, 0x1127),
641 regmap_reg_range(0x112a, 0x112b),
642 regmap_reg_range(0x1136, 0x1139),
643 regmap_reg_range(0x113e, 0x113f),
644 regmap_reg_range(0x1400, 0x1401),
645 regmap_reg_range(0x1403, 0x1403),
646 regmap_reg_range(0x1410, 0x1417),
647 regmap_reg_range(0x1420, 0x1423),
648 regmap_reg_range(0x1500, 0x1507),
649 regmap_reg_range(0x1600, 0x1613),
650 regmap_reg_range(0x1800, 0x180f),
651 regmap_reg_range(0x1820, 0x1827),
652 regmap_reg_range(0x1830, 0x1837),
653 regmap_reg_range(0x1840, 0x184b),
654 regmap_reg_range(0x1900, 0x1907),
655 regmap_reg_range(0x1914, 0x191b),
656 regmap_reg_range(0x1920, 0x1920),
657 regmap_reg_range(0x1923, 0x1927),
658 regmap_reg_range(0x1a00, 0x1a03),
659 regmap_reg_range(0x1a04, 0x1a07),
660 regmap_reg_range(0x1b00, 0x1b01),
661 regmap_reg_range(0x1b04, 0x1b04),
662 regmap_reg_range(0x1c00, 0x1c05),
663 regmap_reg_range(0x1c08, 0x1c1b),
664
665 /* port 2 */
666 regmap_reg_range(0x2000, 0x2001),
667 regmap_reg_range(0x2013, 0x2013),
668 regmap_reg_range(0x2017, 0x2017),
669 regmap_reg_range(0x201b, 0x201b),
670 regmap_reg_range(0x201f, 0x2020),
671 regmap_reg_range(0x2030, 0x2030),
672 regmap_reg_range(0x2100, 0x2115),
673 regmap_reg_range(0x211a, 0x211f),
674 regmap_reg_range(0x2122, 0x2127),
675 regmap_reg_range(0x212a, 0x212b),
676 regmap_reg_range(0x2136, 0x2139),
677 regmap_reg_range(0x213e, 0x213f),
678 regmap_reg_range(0x2400, 0x2401),
679 regmap_reg_range(0x2403, 0x2403),
680 regmap_reg_range(0x2410, 0x2417),
681 regmap_reg_range(0x2420, 0x2423),
682 regmap_reg_range(0x2500, 0x2507),
683 regmap_reg_range(0x2600, 0x2613),
684 regmap_reg_range(0x2800, 0x280f),
685 regmap_reg_range(0x2820, 0x2827),
686 regmap_reg_range(0x2830, 0x2837),
687 regmap_reg_range(0x2840, 0x284b),
688 regmap_reg_range(0x2900, 0x2907),
689 regmap_reg_range(0x2914, 0x291b),
690 regmap_reg_range(0x2920, 0x2920),
691 regmap_reg_range(0x2923, 0x2927),
692 regmap_reg_range(0x2a00, 0x2a03),
693 regmap_reg_range(0x2a04, 0x2a07),
694 regmap_reg_range(0x2b00, 0x2b01),
695 regmap_reg_range(0x2b04, 0x2b04),
696 regmap_reg_range(0x2c00, 0x2c05),
697 regmap_reg_range(0x2c08, 0x2c1b),
698
699 /* port 3 */
700 regmap_reg_range(0x3000, 0x3001),
701 regmap_reg_range(0x3013, 0x3013),
702 regmap_reg_range(0x3017, 0x3017),
703 regmap_reg_range(0x301b, 0x301b),
704 regmap_reg_range(0x301f, 0x3020),
705 regmap_reg_range(0x3030, 0x3030),
706 regmap_reg_range(0x3100, 0x3115),
707 regmap_reg_range(0x311a, 0x311f),
708 regmap_reg_range(0x3122, 0x3127),
709 regmap_reg_range(0x312a, 0x312b),
710 regmap_reg_range(0x3136, 0x3139),
711 regmap_reg_range(0x313e, 0x313f),
712 regmap_reg_range(0x3400, 0x3401),
713 regmap_reg_range(0x3403, 0x3403),
714 regmap_reg_range(0x3410, 0x3417),
715 regmap_reg_range(0x3420, 0x3423),
716 regmap_reg_range(0x3500, 0x3507),
717 regmap_reg_range(0x3600, 0x3613),
718 regmap_reg_range(0x3800, 0x380f),
719 regmap_reg_range(0x3820, 0x3827),
720 regmap_reg_range(0x3830, 0x3837),
721 regmap_reg_range(0x3840, 0x384b),
722 regmap_reg_range(0x3900, 0x3907),
723 regmap_reg_range(0x3914, 0x391b),
724 regmap_reg_range(0x3920, 0x3920),
725 regmap_reg_range(0x3923, 0x3927),
726 regmap_reg_range(0x3a00, 0x3a03),
727 regmap_reg_range(0x3a04, 0x3a07),
728 regmap_reg_range(0x3b00, 0x3b01),
729 regmap_reg_range(0x3b04, 0x3b04),
730 regmap_reg_range(0x3c00, 0x3c05),
731 regmap_reg_range(0x3c08, 0x3c1b),
732
733 /* port 4 */
734 regmap_reg_range(0x4000, 0x4001),
735 regmap_reg_range(0x4013, 0x4013),
736 regmap_reg_range(0x4017, 0x4017),
737 regmap_reg_range(0x401b, 0x401b),
738 regmap_reg_range(0x401f, 0x4020),
739 regmap_reg_range(0x4030, 0x4030),
740 regmap_reg_range(0x4100, 0x4115),
741 regmap_reg_range(0x411a, 0x411f),
742 regmap_reg_range(0x4122, 0x4127),
743 regmap_reg_range(0x412a, 0x412b),
744 regmap_reg_range(0x4136, 0x4139),
745 regmap_reg_range(0x413e, 0x413f),
746 regmap_reg_range(0x4400, 0x4401),
747 regmap_reg_range(0x4403, 0x4403),
748 regmap_reg_range(0x4410, 0x4417),
749 regmap_reg_range(0x4420, 0x4423),
750 regmap_reg_range(0x4500, 0x4507),
751 regmap_reg_range(0x4600, 0x4613),
752 regmap_reg_range(0x4800, 0x480f),
753 regmap_reg_range(0x4820, 0x4827),
754 regmap_reg_range(0x4830, 0x4837),
755 regmap_reg_range(0x4840, 0x484b),
756 regmap_reg_range(0x4900, 0x4907),
757 regmap_reg_range(0x4914, 0x491b),
758 regmap_reg_range(0x4920, 0x4920),
759 regmap_reg_range(0x4923, 0x4927),
760 regmap_reg_range(0x4a00, 0x4a03),
761 regmap_reg_range(0x4a04, 0x4a07),
762 regmap_reg_range(0x4b00, 0x4b01),
763 regmap_reg_range(0x4b04, 0x4b04),
764 regmap_reg_range(0x4c00, 0x4c05),
765 regmap_reg_range(0x4c08, 0x4c1b),
766
767 /* port 5 */
768 regmap_reg_range(0x5000, 0x5001),
769 regmap_reg_range(0x5013, 0x5013),
770 regmap_reg_range(0x5017, 0x5017),
771 regmap_reg_range(0x501b, 0x501b),
772 regmap_reg_range(0x501f, 0x5020),
773 regmap_reg_range(0x5030, 0x5030),
774 regmap_reg_range(0x5100, 0x5115),
775 regmap_reg_range(0x511a, 0x511f),
776 regmap_reg_range(0x5122, 0x5127),
777 regmap_reg_range(0x512a, 0x512b),
778 regmap_reg_range(0x5136, 0x5139),
779 regmap_reg_range(0x513e, 0x513f),
780 regmap_reg_range(0x5400, 0x5401),
781 regmap_reg_range(0x5403, 0x5403),
782 regmap_reg_range(0x5410, 0x5417),
783 regmap_reg_range(0x5420, 0x5423),
784 regmap_reg_range(0x5500, 0x5507),
785 regmap_reg_range(0x5600, 0x5613),
786 regmap_reg_range(0x5800, 0x580f),
787 regmap_reg_range(0x5820, 0x5827),
788 regmap_reg_range(0x5830, 0x5837),
789 regmap_reg_range(0x5840, 0x584b),
790 regmap_reg_range(0x5900, 0x5907),
791 regmap_reg_range(0x5914, 0x591b),
792 regmap_reg_range(0x5920, 0x5920),
793 regmap_reg_range(0x5923, 0x5927),
794 regmap_reg_range(0x5a00, 0x5a03),
795 regmap_reg_range(0x5a04, 0x5a07),
796 regmap_reg_range(0x5b00, 0x5b01),
797 regmap_reg_range(0x5b04, 0x5b04),
798 regmap_reg_range(0x5c00, 0x5c05),
799 regmap_reg_range(0x5c08, 0x5c1b),
800
801 /* port 6 */
802 regmap_reg_range(0x6000, 0x6001),
803 regmap_reg_range(0x6013, 0x6013),
804 regmap_reg_range(0x6017, 0x6017),
805 regmap_reg_range(0x601b, 0x601b),
806 regmap_reg_range(0x601f, 0x6020),
807 regmap_reg_range(0x6030, 0x6030),
808 regmap_reg_range(0x6300, 0x6301),
809 regmap_reg_range(0x6400, 0x6401),
810 regmap_reg_range(0x6403, 0x6403),
811 regmap_reg_range(0x6410, 0x6417),
812 regmap_reg_range(0x6420, 0x6423),
813 regmap_reg_range(0x6500, 0x6507),
814 regmap_reg_range(0x6600, 0x6613),
815 regmap_reg_range(0x6800, 0x680f),
816 regmap_reg_range(0x6820, 0x6827),
817 regmap_reg_range(0x6830, 0x6837),
818 regmap_reg_range(0x6840, 0x684b),
819 regmap_reg_range(0x6900, 0x6907),
820 regmap_reg_range(0x6914, 0x691b),
821 regmap_reg_range(0x6920, 0x6920),
822 regmap_reg_range(0x6923, 0x6927),
823 regmap_reg_range(0x6a00, 0x6a03),
824 regmap_reg_range(0x6a04, 0x6a07),
825 regmap_reg_range(0x6b00, 0x6b01),
826 regmap_reg_range(0x6b04, 0x6b04),
827 regmap_reg_range(0x6c00, 0x6c05),
828 regmap_reg_range(0x6c08, 0x6c1b),
829
830 /* port 7 */
831 regmap_reg_range(0x7000, 0x7001),
832 regmap_reg_range(0x7013, 0x7013),
833 regmap_reg_range(0x7017, 0x7017),
834 regmap_reg_range(0x701b, 0x701b),
835 regmap_reg_range(0x701f, 0x7020),
836 regmap_reg_range(0x7030, 0x7030),
837 regmap_reg_range(0x7200, 0x7203),
838 regmap_reg_range(0x7206, 0x7207),
839 regmap_reg_range(0x7300, 0x7301),
840 regmap_reg_range(0x7400, 0x7401),
841 regmap_reg_range(0x7403, 0x7403),
842 regmap_reg_range(0x7410, 0x7417),
843 regmap_reg_range(0x7420, 0x7423),
844 regmap_reg_range(0x7500, 0x7507),
845 regmap_reg_range(0x7600, 0x7613),
846 regmap_reg_range(0x7800, 0x780f),
847 regmap_reg_range(0x7820, 0x7827),
848 regmap_reg_range(0x7830, 0x7837),
849 regmap_reg_range(0x7840, 0x784b),
850 regmap_reg_range(0x7900, 0x7907),
851 regmap_reg_range(0x7914, 0x791b),
852 regmap_reg_range(0x7920, 0x7920),
853 regmap_reg_range(0x7923, 0x7927),
854 regmap_reg_range(0x7a00, 0x7a03),
855 regmap_reg_range(0x7a04, 0x7a07),
856 regmap_reg_range(0x7b00, 0x7b01),
857 regmap_reg_range(0x7b04, 0x7b04),
858 regmap_reg_range(0x7c00, 0x7c05),
859 regmap_reg_range(0x7c08, 0x7c1b),
860 };
861
862 static const struct regmap_access_table ksz9477_register_set = {
863 .yes_ranges = ksz9477_valid_regs,
864 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs),
865 };
866
867 static const struct regmap_range ksz9896_valid_regs[] = {
868 regmap_reg_range(0x0000, 0x0003),
869 regmap_reg_range(0x0006, 0x0006),
870 regmap_reg_range(0x0010, 0x001f),
871 regmap_reg_range(0x0100, 0x0100),
872 regmap_reg_range(0x0103, 0x0107),
873 regmap_reg_range(0x010d, 0x010d),
874 regmap_reg_range(0x0110, 0x0113),
875 regmap_reg_range(0x0120, 0x0127),
876 regmap_reg_range(0x0201, 0x0201),
877 regmap_reg_range(0x0210, 0x0213),
878 regmap_reg_range(0x0300, 0x0300),
879 regmap_reg_range(0x0302, 0x030b),
880 regmap_reg_range(0x0310, 0x031b),
881 regmap_reg_range(0x0320, 0x032b),
882 regmap_reg_range(0x0330, 0x0336),
883 regmap_reg_range(0x0338, 0x033b),
884 regmap_reg_range(0x033e, 0x033e),
885 regmap_reg_range(0x0340, 0x035f),
886 regmap_reg_range(0x0370, 0x0370),
887 regmap_reg_range(0x0378, 0x0378),
888 regmap_reg_range(0x037c, 0x037d),
889 regmap_reg_range(0x0390, 0x0393),
890 regmap_reg_range(0x0400, 0x040e),
891 regmap_reg_range(0x0410, 0x042f),
892
893 /* port 1 */
894 regmap_reg_range(0x1000, 0x1001),
895 regmap_reg_range(0x1013, 0x1013),
896 regmap_reg_range(0x1017, 0x1017),
897 regmap_reg_range(0x101b, 0x101b),
898 regmap_reg_range(0x101f, 0x1020),
899 regmap_reg_range(0x1030, 0x1030),
900 regmap_reg_range(0x1100, 0x1115),
901 regmap_reg_range(0x111a, 0x111f),
902 regmap_reg_range(0x1122, 0x1127),
903 regmap_reg_range(0x112a, 0x112b),
904 regmap_reg_range(0x1136, 0x1139),
905 regmap_reg_range(0x113e, 0x113f),
906 regmap_reg_range(0x1400, 0x1401),
907 regmap_reg_range(0x1403, 0x1403),
908 regmap_reg_range(0x1410, 0x1417),
909 regmap_reg_range(0x1420, 0x1423),
910 regmap_reg_range(0x1500, 0x1507),
911 regmap_reg_range(0x1600, 0x1612),
912 regmap_reg_range(0x1800, 0x180f),
913 regmap_reg_range(0x1820, 0x1827),
914 regmap_reg_range(0x1830, 0x1837),
915 regmap_reg_range(0x1840, 0x184b),
916 regmap_reg_range(0x1900, 0x1907),
917 regmap_reg_range(0x1914, 0x1915),
918 regmap_reg_range(0x1a00, 0x1a03),
919 regmap_reg_range(0x1a04, 0x1a07),
920 regmap_reg_range(0x1b00, 0x1b01),
921 regmap_reg_range(0x1b04, 0x1b04),
922
923 /* port 2 */
924 regmap_reg_range(0x2000, 0x2001),
925 regmap_reg_range(0x2013, 0x2013),
926 regmap_reg_range(0x2017, 0x2017),
927 regmap_reg_range(0x201b, 0x201b),
928 regmap_reg_range(0x201f, 0x2020),
929 regmap_reg_range(0x2030, 0x2030),
930 regmap_reg_range(0x2100, 0x2115),
931 regmap_reg_range(0x211a, 0x211f),
932 regmap_reg_range(0x2122, 0x2127),
933 regmap_reg_range(0x212a, 0x212b),
934 regmap_reg_range(0x2136, 0x2139),
935 regmap_reg_range(0x213e, 0x213f),
936 regmap_reg_range(0x2400, 0x2401),
937 regmap_reg_range(0x2403, 0x2403),
938 regmap_reg_range(0x2410, 0x2417),
939 regmap_reg_range(0x2420, 0x2423),
940 regmap_reg_range(0x2500, 0x2507),
941 regmap_reg_range(0x2600, 0x2612),
942 regmap_reg_range(0x2800, 0x280f),
943 regmap_reg_range(0x2820, 0x2827),
944 regmap_reg_range(0x2830, 0x2837),
945 regmap_reg_range(0x2840, 0x284b),
946 regmap_reg_range(0x2900, 0x2907),
947 regmap_reg_range(0x2914, 0x2915),
948 regmap_reg_range(0x2a00, 0x2a03),
949 regmap_reg_range(0x2a04, 0x2a07),
950 regmap_reg_range(0x2b00, 0x2b01),
951 regmap_reg_range(0x2b04, 0x2b04),
952
953 /* port 3 */
954 regmap_reg_range(0x3000, 0x3001),
955 regmap_reg_range(0x3013, 0x3013),
956 regmap_reg_range(0x3017, 0x3017),
957 regmap_reg_range(0x301b, 0x301b),
958 regmap_reg_range(0x301f, 0x3020),
959 regmap_reg_range(0x3030, 0x3030),
960 regmap_reg_range(0x3100, 0x3115),
961 regmap_reg_range(0x311a, 0x311f),
962 regmap_reg_range(0x3122, 0x3127),
963 regmap_reg_range(0x312a, 0x312b),
964 regmap_reg_range(0x3136, 0x3139),
965 regmap_reg_range(0x313e, 0x313f),
966 regmap_reg_range(0x3400, 0x3401),
967 regmap_reg_range(0x3403, 0x3403),
968 regmap_reg_range(0x3410, 0x3417),
969 regmap_reg_range(0x3420, 0x3423),
970 regmap_reg_range(0x3500, 0x3507),
971 regmap_reg_range(0x3600, 0x3612),
972 regmap_reg_range(0x3800, 0x380f),
973 regmap_reg_range(0x3820, 0x3827),
974 regmap_reg_range(0x3830, 0x3837),
975 regmap_reg_range(0x3840, 0x384b),
976 regmap_reg_range(0x3900, 0x3907),
977 regmap_reg_range(0x3914, 0x3915),
978 regmap_reg_range(0x3a00, 0x3a03),
979 regmap_reg_range(0x3a04, 0x3a07),
980 regmap_reg_range(0x3b00, 0x3b01),
981 regmap_reg_range(0x3b04, 0x3b04),
982
983 /* port 4 */
984 regmap_reg_range(0x4000, 0x4001),
985 regmap_reg_range(0x4013, 0x4013),
986 regmap_reg_range(0x4017, 0x4017),
987 regmap_reg_range(0x401b, 0x401b),
988 regmap_reg_range(0x401f, 0x4020),
989 regmap_reg_range(0x4030, 0x4030),
990 regmap_reg_range(0x4100, 0x4115),
991 regmap_reg_range(0x411a, 0x411f),
992 regmap_reg_range(0x4122, 0x4127),
993 regmap_reg_range(0x412a, 0x412b),
994 regmap_reg_range(0x4136, 0x4139),
995 regmap_reg_range(0x413e, 0x413f),
996 regmap_reg_range(0x4400, 0x4401),
997 regmap_reg_range(0x4403, 0x4403),
998 regmap_reg_range(0x4410, 0x4417),
999 regmap_reg_range(0x4420, 0x4423),
1000 regmap_reg_range(0x4500, 0x4507),
1001 regmap_reg_range(0x4600, 0x4612),
1002 regmap_reg_range(0x4800, 0x480f),
1003 regmap_reg_range(0x4820, 0x4827),
1004 regmap_reg_range(0x4830, 0x4837),
1005 regmap_reg_range(0x4840, 0x484b),
1006 regmap_reg_range(0x4900, 0x4907),
1007 regmap_reg_range(0x4914, 0x4915),
1008 regmap_reg_range(0x4a00, 0x4a03),
1009 regmap_reg_range(0x4a04, 0x4a07),
1010 regmap_reg_range(0x4b00, 0x4b01),
1011 regmap_reg_range(0x4b04, 0x4b04),
1012
1013 /* port 5 */
1014 regmap_reg_range(0x5000, 0x5001),
1015 regmap_reg_range(0x5013, 0x5013),
1016 regmap_reg_range(0x5017, 0x5017),
1017 regmap_reg_range(0x501b, 0x501b),
1018 regmap_reg_range(0x501f, 0x5020),
1019 regmap_reg_range(0x5030, 0x5030),
1020 regmap_reg_range(0x5100, 0x5115),
1021 regmap_reg_range(0x511a, 0x511f),
1022 regmap_reg_range(0x5122, 0x5127),
1023 regmap_reg_range(0x512a, 0x512b),
1024 regmap_reg_range(0x5136, 0x5139),
1025 regmap_reg_range(0x513e, 0x513f),
1026 regmap_reg_range(0x5400, 0x5401),
1027 regmap_reg_range(0x5403, 0x5403),
1028 regmap_reg_range(0x5410, 0x5417),
1029 regmap_reg_range(0x5420, 0x5423),
1030 regmap_reg_range(0x5500, 0x5507),
1031 regmap_reg_range(0x5600, 0x5612),
1032 regmap_reg_range(0x5800, 0x580f),
1033 regmap_reg_range(0x5820, 0x5827),
1034 regmap_reg_range(0x5830, 0x5837),
1035 regmap_reg_range(0x5840, 0x584b),
1036 regmap_reg_range(0x5900, 0x5907),
1037 regmap_reg_range(0x5914, 0x5915),
1038 regmap_reg_range(0x5a00, 0x5a03),
1039 regmap_reg_range(0x5a04, 0x5a07),
1040 regmap_reg_range(0x5b00, 0x5b01),
1041 regmap_reg_range(0x5b04, 0x5b04),
1042
1043 /* port 6 */
1044 regmap_reg_range(0x6000, 0x6001),
1045 regmap_reg_range(0x6013, 0x6013),
1046 regmap_reg_range(0x6017, 0x6017),
1047 regmap_reg_range(0x601b, 0x601b),
1048 regmap_reg_range(0x601f, 0x6020),
1049 regmap_reg_range(0x6030, 0x6030),
1050 regmap_reg_range(0x6100, 0x6115),
1051 regmap_reg_range(0x611a, 0x611f),
1052 regmap_reg_range(0x6122, 0x6127),
1053 regmap_reg_range(0x612a, 0x612b),
1054 regmap_reg_range(0x6136, 0x6139),
1055 regmap_reg_range(0x613e, 0x613f),
1056 regmap_reg_range(0x6300, 0x6301),
1057 regmap_reg_range(0x6400, 0x6401),
1058 regmap_reg_range(0x6403, 0x6403),
1059 regmap_reg_range(0x6410, 0x6417),
1060 regmap_reg_range(0x6420, 0x6423),
1061 regmap_reg_range(0x6500, 0x6507),
1062 regmap_reg_range(0x6600, 0x6612),
1063 regmap_reg_range(0x6800, 0x680f),
1064 regmap_reg_range(0x6820, 0x6827),
1065 regmap_reg_range(0x6830, 0x6837),
1066 regmap_reg_range(0x6840, 0x684b),
1067 regmap_reg_range(0x6900, 0x6907),
1068 regmap_reg_range(0x6914, 0x6915),
1069 regmap_reg_range(0x6a00, 0x6a03),
1070 regmap_reg_range(0x6a04, 0x6a07),
1071 regmap_reg_range(0x6b00, 0x6b01),
1072 regmap_reg_range(0x6b04, 0x6b04),
1073 };
1074
1075 static const struct regmap_access_table ksz9896_register_set = {
1076 .yes_ranges = ksz9896_valid_regs,
1077 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs),
1078 };
1079
1080 const struct ksz_chip_data ksz_switch_chips[] = {
1081 [KSZ8563] = {
1082 .chip_id = KSZ8563_CHIP_ID,
1083 .dev_name = "KSZ8563",
1084 .num_vlans = 4096,
1085 .num_alus = 4096,
1086 .num_statics = 16,
1087 .cpu_ports = 0x07, /* can be configured as cpu port */
1088 .port_cnt = 3, /* total port count */
1089 .port_nirqs = 3,
1090 .num_tx_queues = 4,
1091 .tc_cbs_supported = true,
1092 .ops = &ksz9477_dev_ops,
1093 .mib_names = ksz9477_mib_names,
1094 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1095 .reg_mib_cnt = MIB_COUNTER_NUM,
1096 .regs = ksz9477_regs,
1097 .masks = ksz9477_masks,
1098 .shifts = ksz9477_shifts,
1099 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1100 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1101 .supports_mii = {false, false, true},
1102 .supports_rmii = {false, false, true},
1103 .supports_rgmii = {false, false, true},
1104 .internal_phy = {true, true, false},
1105 .gbit_capable = {false, false, true},
1106 .wr_table = &ksz8563_register_set,
1107 .rd_table = &ksz8563_register_set,
1108 },
1109
1110 [KSZ8795] = {
1111 .chip_id = KSZ8795_CHIP_ID,
1112 .dev_name = "KSZ8795",
1113 .num_vlans = 4096,
1114 .num_alus = 0,
1115 .num_statics = 8,
1116 .cpu_ports = 0x10, /* can be configured as cpu port */
1117 .port_cnt = 5, /* total cpu and user ports */
1118 .num_tx_queues = 4,
1119 .ops = &ksz8_dev_ops,
1120 .ksz87xx_eee_link_erratum = true,
1121 .mib_names = ksz9477_mib_names,
1122 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1123 .reg_mib_cnt = MIB_COUNTER_NUM,
1124 .regs = ksz8795_regs,
1125 .masks = ksz8795_masks,
1126 .shifts = ksz8795_shifts,
1127 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1128 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1129 .supports_mii = {false, false, false, false, true},
1130 .supports_rmii = {false, false, false, false, true},
1131 .supports_rgmii = {false, false, false, false, true},
1132 .internal_phy = {true, true, true, true, false},
1133 },
1134
1135 [KSZ8794] = {
1136 /* WARNING
1137 * =======
1138 * KSZ8794 is similar to KSZ8795, except the port map
1139 * contains a gap between external and CPU ports, the
1140 * port map is NOT continuous. The per-port register
1141 * map is shifted accordingly too, i.e. registers at
1142 * offset 0x40 are NOT used on KSZ8794 and they ARE
1143 * used on KSZ8795 for external port 3.
1144 * external cpu
1145 * KSZ8794 0,1,2 4
1146 * KSZ8795 0,1,2,3 4
1147 * KSZ8765 0,1,2,3 4
1148 * port_cnt is configured as 5, even though it is 4
1149 */
1150 .chip_id = KSZ8794_CHIP_ID,
1151 .dev_name = "KSZ8794",
1152 .num_vlans = 4096,
1153 .num_alus = 0,
1154 .num_statics = 8,
1155 .cpu_ports = 0x10, /* can be configured as cpu port */
1156 .port_cnt = 5, /* total cpu and user ports */
1157 .num_tx_queues = 4,
1158 .ops = &ksz8_dev_ops,
1159 .ksz87xx_eee_link_erratum = true,
1160 .mib_names = ksz9477_mib_names,
1161 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1162 .reg_mib_cnt = MIB_COUNTER_NUM,
1163 .regs = ksz8795_regs,
1164 .masks = ksz8795_masks,
1165 .shifts = ksz8795_shifts,
1166 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1167 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1168 .supports_mii = {false, false, false, false, true},
1169 .supports_rmii = {false, false, false, false, true},
1170 .supports_rgmii = {false, false, false, false, true},
1171 .internal_phy = {true, true, true, false, false},
1172 },
1173
1174 [KSZ8765] = {
1175 .chip_id = KSZ8765_CHIP_ID,
1176 .dev_name = "KSZ8765",
1177 .num_vlans = 4096,
1178 .num_alus = 0,
1179 .num_statics = 8,
1180 .cpu_ports = 0x10, /* can be configured as cpu port */
1181 .port_cnt = 5, /* total cpu and user ports */
1182 .num_tx_queues = 4,
1183 .ops = &ksz8_dev_ops,
1184 .ksz87xx_eee_link_erratum = true,
1185 .mib_names = ksz9477_mib_names,
1186 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1187 .reg_mib_cnt = MIB_COUNTER_NUM,
1188 .regs = ksz8795_regs,
1189 .masks = ksz8795_masks,
1190 .shifts = ksz8795_shifts,
1191 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1192 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1193 .supports_mii = {false, false, false, false, true},
1194 .supports_rmii = {false, false, false, false, true},
1195 .supports_rgmii = {false, false, false, false, true},
1196 .internal_phy = {true, true, true, true, false},
1197 },
1198
1199 [KSZ8830] = {
1200 .chip_id = KSZ8830_CHIP_ID,
1201 .dev_name = "KSZ8863/KSZ8873",
1202 .num_vlans = 16,
1203 .num_alus = 0,
1204 .num_statics = 8,
1205 .cpu_ports = 0x4, /* can be configured as cpu port */
1206 .port_cnt = 3,
1207 .num_tx_queues = 4,
1208 .ops = &ksz8_dev_ops,
1209 .mib_names = ksz88xx_mib_names,
1210 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1211 .reg_mib_cnt = MIB_COUNTER_NUM,
1212 .regs = ksz8863_regs,
1213 .masks = ksz8863_masks,
1214 .shifts = ksz8863_shifts,
1215 .supports_mii = {false, false, true},
1216 .supports_rmii = {false, false, true},
1217 .internal_phy = {true, true, false},
1218 },
1219
1220 [KSZ9477] = {
1221 .chip_id = KSZ9477_CHIP_ID,
1222 .dev_name = "KSZ9477",
1223 .num_vlans = 4096,
1224 .num_alus = 4096,
1225 .num_statics = 16,
1226 .cpu_ports = 0x7F, /* can be configured as cpu port */
1227 .port_cnt = 7, /* total physical port count */
1228 .port_nirqs = 4,
1229 .num_tx_queues = 4,
1230 .tc_cbs_supported = true,
1231 .ops = &ksz9477_dev_ops,
1232 .phy_errata_9477 = true,
1233 .mib_names = ksz9477_mib_names,
1234 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1235 .reg_mib_cnt = MIB_COUNTER_NUM,
1236 .regs = ksz9477_regs,
1237 .masks = ksz9477_masks,
1238 .shifts = ksz9477_shifts,
1239 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1240 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1241 .supports_mii = {false, false, false, false,
1242 false, true, false},
1243 .supports_rmii = {false, false, false, false,
1244 false, true, false},
1245 .supports_rgmii = {false, false, false, false,
1246 false, true, false},
1247 .internal_phy = {true, true, true, true,
1248 true, false, false},
1249 .gbit_capable = {true, true, true, true, true, true, true},
1250 .wr_table = &ksz9477_register_set,
1251 .rd_table = &ksz9477_register_set,
1252 },
1253
1254 [KSZ9896] = {
1255 .chip_id = KSZ9896_CHIP_ID,
1256 .dev_name = "KSZ9896",
1257 .num_vlans = 4096,
1258 .num_alus = 4096,
1259 .num_statics = 16,
1260 .cpu_ports = 0x3F, /* can be configured as cpu port */
1261 .port_cnt = 6, /* total physical port count */
1262 .port_nirqs = 2,
1263 .num_tx_queues = 4,
1264 .ops = &ksz9477_dev_ops,
1265 .phy_errata_9477 = true,
1266 .mib_names = ksz9477_mib_names,
1267 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1268 .reg_mib_cnt = MIB_COUNTER_NUM,
1269 .regs = ksz9477_regs,
1270 .masks = ksz9477_masks,
1271 .shifts = ksz9477_shifts,
1272 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1273 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1274 .supports_mii = {false, false, false, false,
1275 false, true},
1276 .supports_rmii = {false, false, false, false,
1277 false, true},
1278 .supports_rgmii = {false, false, false, false,
1279 false, true},
1280 .internal_phy = {true, true, true, true,
1281 true, false},
1282 .gbit_capable = {true, true, true, true, true, true},
1283 .wr_table = &ksz9896_register_set,
1284 .rd_table = &ksz9896_register_set,
1285 },
1286
1287 [KSZ9897] = {
1288 .chip_id = KSZ9897_CHIP_ID,
1289 .dev_name = "KSZ9897",
1290 .num_vlans = 4096,
1291 .num_alus = 4096,
1292 .num_statics = 16,
1293 .cpu_ports = 0x7F, /* can be configured as cpu port */
1294 .port_cnt = 7, /* total physical port count */
1295 .port_nirqs = 2,
1296 .num_tx_queues = 4,
1297 .ops = &ksz9477_dev_ops,
1298 .phy_errata_9477 = true,
1299 .mib_names = ksz9477_mib_names,
1300 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1301 .reg_mib_cnt = MIB_COUNTER_NUM,
1302 .regs = ksz9477_regs,
1303 .masks = ksz9477_masks,
1304 .shifts = ksz9477_shifts,
1305 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1306 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1307 .supports_mii = {false, false, false, false,
1308 false, true, true},
1309 .supports_rmii = {false, false, false, false,
1310 false, true, true},
1311 .supports_rgmii = {false, false, false, false,
1312 false, true, true},
1313 .internal_phy = {true, true, true, true,
1314 true, false, false},
1315 .gbit_capable = {true, true, true, true, true, true, true},
1316 },
1317
1318 [KSZ9893] = {
1319 .chip_id = KSZ9893_CHIP_ID,
1320 .dev_name = "KSZ9893",
1321 .num_vlans = 4096,
1322 .num_alus = 4096,
1323 .num_statics = 16,
1324 .cpu_ports = 0x07, /* can be configured as cpu port */
1325 .port_cnt = 3, /* total port count */
1326 .port_nirqs = 2,
1327 .num_tx_queues = 4,
1328 .ops = &ksz9477_dev_ops,
1329 .mib_names = ksz9477_mib_names,
1330 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1331 .reg_mib_cnt = MIB_COUNTER_NUM,
1332 .regs = ksz9477_regs,
1333 .masks = ksz9477_masks,
1334 .shifts = ksz9477_shifts,
1335 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1336 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1337 .supports_mii = {false, false, true},
1338 .supports_rmii = {false, false, true},
1339 .supports_rgmii = {false, false, true},
1340 .internal_phy = {true, true, false},
1341 .gbit_capable = {true, true, true},
1342 },
1343
1344 [KSZ9563] = {
1345 .chip_id = KSZ9563_CHIP_ID,
1346 .dev_name = "KSZ9563",
1347 .num_vlans = 4096,
1348 .num_alus = 4096,
1349 .num_statics = 16,
1350 .cpu_ports = 0x07, /* can be configured as cpu port */
1351 .port_cnt = 3, /* total port count */
1352 .port_nirqs = 3,
1353 .num_tx_queues = 4,
1354 .tc_cbs_supported = true,
1355 .ops = &ksz9477_dev_ops,
1356 .mib_names = ksz9477_mib_names,
1357 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1358 .reg_mib_cnt = MIB_COUNTER_NUM,
1359 .regs = ksz9477_regs,
1360 .masks = ksz9477_masks,
1361 .shifts = ksz9477_shifts,
1362 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1363 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1364 .supports_mii = {false, false, true},
1365 .supports_rmii = {false, false, true},
1366 .supports_rgmii = {false, false, true},
1367 .internal_phy = {true, true, false},
1368 .gbit_capable = {true, true, true},
1369 },
1370
1371 [KSZ9567] = {
1372 .chip_id = KSZ9567_CHIP_ID,
1373 .dev_name = "KSZ9567",
1374 .num_vlans = 4096,
1375 .num_alus = 4096,
1376 .num_statics = 16,
1377 .cpu_ports = 0x7F, /* can be configured as cpu port */
1378 .port_cnt = 7, /* total physical port count */
1379 .port_nirqs = 3,
1380 .num_tx_queues = 4,
1381 .tc_cbs_supported = true,
1382 .ops = &ksz9477_dev_ops,
1383 .phy_errata_9477 = true,
1384 .mib_names = ksz9477_mib_names,
1385 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1386 .reg_mib_cnt = MIB_COUNTER_NUM,
1387 .regs = ksz9477_regs,
1388 .masks = ksz9477_masks,
1389 .shifts = ksz9477_shifts,
1390 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1391 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1392 .supports_mii = {false, false, false, false,
1393 false, true, true},
1394 .supports_rmii = {false, false, false, false,
1395 false, true, true},
1396 .supports_rgmii = {false, false, false, false,
1397 false, true, true},
1398 .internal_phy = {true, true, true, true,
1399 true, false, false},
1400 .gbit_capable = {true, true, true, true, true, true, true},
1401 },
1402
1403 [LAN9370] = {
1404 .chip_id = LAN9370_CHIP_ID,
1405 .dev_name = "LAN9370",
1406 .num_vlans = 4096,
1407 .num_alus = 1024,
1408 .num_statics = 256,
1409 .cpu_ports = 0x10, /* can be configured as cpu port */
1410 .port_cnt = 5, /* total physical port count */
1411 .port_nirqs = 6,
1412 .num_tx_queues = 8,
1413 .tc_cbs_supported = true,
1414 .ops = &lan937x_dev_ops,
1415 .mib_names = ksz9477_mib_names,
1416 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1417 .reg_mib_cnt = MIB_COUNTER_NUM,
1418 .regs = ksz9477_regs,
1419 .masks = lan937x_masks,
1420 .shifts = lan937x_shifts,
1421 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1422 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1423 .supports_mii = {false, false, false, false, true},
1424 .supports_rmii = {false, false, false, false, true},
1425 .supports_rgmii = {false, false, false, false, true},
1426 .internal_phy = {true, true, true, true, false},
1427 },
1428
1429 [LAN9371] = {
1430 .chip_id = LAN9371_CHIP_ID,
1431 .dev_name = "LAN9371",
1432 .num_vlans = 4096,
1433 .num_alus = 1024,
1434 .num_statics = 256,
1435 .cpu_ports = 0x30, /* can be configured as cpu port */
1436 .port_cnt = 6, /* total physical port count */
1437 .port_nirqs = 6,
1438 .num_tx_queues = 8,
1439 .tc_cbs_supported = true,
1440 .ops = &lan937x_dev_ops,
1441 .mib_names = ksz9477_mib_names,
1442 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1443 .reg_mib_cnt = MIB_COUNTER_NUM,
1444 .regs = ksz9477_regs,
1445 .masks = lan937x_masks,
1446 .shifts = lan937x_shifts,
1447 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1448 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1449 .supports_mii = {false, false, false, false, true, true},
1450 .supports_rmii = {false, false, false, false, true, true},
1451 .supports_rgmii = {false, false, false, false, true, true},
1452 .internal_phy = {true, true, true, true, false, false},
1453 },
1454
1455 [LAN9372] = {
1456 .chip_id = LAN9372_CHIP_ID,
1457 .dev_name = "LAN9372",
1458 .num_vlans = 4096,
1459 .num_alus = 1024,
1460 .num_statics = 256,
1461 .cpu_ports = 0x30, /* can be configured as cpu port */
1462 .port_cnt = 8, /* total physical port count */
1463 .port_nirqs = 6,
1464 .num_tx_queues = 8,
1465 .tc_cbs_supported = true,
1466 .ops = &lan937x_dev_ops,
1467 .mib_names = ksz9477_mib_names,
1468 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1469 .reg_mib_cnt = MIB_COUNTER_NUM,
1470 .regs = ksz9477_regs,
1471 .masks = lan937x_masks,
1472 .shifts = lan937x_shifts,
1473 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1474 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1475 .supports_mii = {false, false, false, false,
1476 true, true, false, false},
1477 .supports_rmii = {false, false, false, false,
1478 true, true, false, false},
1479 .supports_rgmii = {false, false, false, false,
1480 true, true, false, false},
1481 .internal_phy = {true, true, true, true,
1482 false, false, true, true},
1483 },
1484
1485 [LAN9373] = {
1486 .chip_id = LAN9373_CHIP_ID,
1487 .dev_name = "LAN9373",
1488 .num_vlans = 4096,
1489 .num_alus = 1024,
1490 .num_statics = 256,
1491 .cpu_ports = 0x38, /* can be configured as cpu port */
1492 .port_cnt = 5, /* total physical port count */
1493 .port_nirqs = 6,
1494 .num_tx_queues = 8,
1495 .tc_cbs_supported = true,
1496 .ops = &lan937x_dev_ops,
1497 .mib_names = ksz9477_mib_names,
1498 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1499 .reg_mib_cnt = MIB_COUNTER_NUM,
1500 .regs = ksz9477_regs,
1501 .masks = lan937x_masks,
1502 .shifts = lan937x_shifts,
1503 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1504 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1505 .supports_mii = {false, false, false, false,
1506 true, true, false, false},
1507 .supports_rmii = {false, false, false, false,
1508 true, true, false, false},
1509 .supports_rgmii = {false, false, false, false,
1510 true, true, false, false},
1511 .internal_phy = {true, true, true, false,
1512 false, false, true, true},
1513 },
1514
1515 [LAN9374] = {
1516 .chip_id = LAN9374_CHIP_ID,
1517 .dev_name = "LAN9374",
1518 .num_vlans = 4096,
1519 .num_alus = 1024,
1520 .num_statics = 256,
1521 .cpu_ports = 0x30, /* can be configured as cpu port */
1522 .port_cnt = 8, /* total physical port count */
1523 .port_nirqs = 6,
1524 .num_tx_queues = 8,
1525 .tc_cbs_supported = true,
1526 .ops = &lan937x_dev_ops,
1527 .mib_names = ksz9477_mib_names,
1528 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1529 .reg_mib_cnt = MIB_COUNTER_NUM,
1530 .regs = ksz9477_regs,
1531 .masks = lan937x_masks,
1532 .shifts = lan937x_shifts,
1533 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1534 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1535 .supports_mii = {false, false, false, false,
1536 true, true, false, false},
1537 .supports_rmii = {false, false, false, false,
1538 true, true, false, false},
1539 .supports_rgmii = {false, false, false, false,
1540 true, true, false, false},
1541 .internal_phy = {true, true, true, true,
1542 false, false, true, true},
1543 },
1544 };
1545 EXPORT_SYMBOL_GPL(ksz_switch_chips);
1546
ksz_lookup_info(unsigned int prod_num)1547 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num)
1548 {
1549 int i;
1550
1551 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) {
1552 const struct ksz_chip_data *chip = &ksz_switch_chips[i];
1553
1554 if (chip->chip_id == prod_num)
1555 return chip;
1556 }
1557
1558 return NULL;
1559 }
1560
ksz_check_device_id(struct ksz_device * dev)1561 static int ksz_check_device_id(struct ksz_device *dev)
1562 {
1563 const struct ksz_chip_data *dt_chip_data;
1564
1565 dt_chip_data = of_device_get_match_data(dev->dev);
1566
1567 /* Check for Device Tree and Chip ID */
1568 if (dt_chip_data->chip_id != dev->chip_id) {
1569 dev_err(dev->dev,
1570 "Device tree specifies chip %s but found %s, please fix it!\n",
1571 dt_chip_data->dev_name, dev->info->dev_name);
1572 return -ENODEV;
1573 }
1574
1575 return 0;
1576 }
1577
ksz_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)1578 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port,
1579 struct phylink_config *config)
1580 {
1581 struct ksz_device *dev = ds->priv;
1582
1583 config->legacy_pre_march2020 = false;
1584
1585 if (dev->info->supports_mii[port])
1586 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
1587
1588 if (dev->info->supports_rmii[port])
1589 __set_bit(PHY_INTERFACE_MODE_RMII,
1590 config->supported_interfaces);
1591
1592 if (dev->info->supports_rgmii[port])
1593 phy_interface_set_rgmii(config->supported_interfaces);
1594
1595 if (dev->info->internal_phy[port]) {
1596 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1597 config->supported_interfaces);
1598 /* Compatibility for phylib's default interface type when the
1599 * phy-mode property is absent
1600 */
1601 __set_bit(PHY_INTERFACE_MODE_GMII,
1602 config->supported_interfaces);
1603 }
1604
1605 if (dev->dev_ops->get_caps)
1606 dev->dev_ops->get_caps(dev, port, config);
1607 }
1608
ksz_r_mib_stats64(struct ksz_device * dev,int port)1609 void ksz_r_mib_stats64(struct ksz_device *dev, int port)
1610 {
1611 struct ethtool_pause_stats *pstats;
1612 struct rtnl_link_stats64 *stats;
1613 struct ksz_stats_raw *raw;
1614 struct ksz_port_mib *mib;
1615
1616 mib = &dev->ports[port].mib;
1617 stats = &mib->stats64;
1618 pstats = &mib->pause_stats;
1619 raw = (struct ksz_stats_raw *)mib->counters;
1620
1621 spin_lock(&mib->stats64_lock);
1622
1623 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
1624 raw->rx_pause;
1625 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
1626 raw->tx_pause;
1627
1628 /* HW counters are counting bytes + FCS which is not acceptable
1629 * for rtnl_link_stats64 interface
1630 */
1631 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN;
1632 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN;
1633
1634 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
1635 raw->rx_oversize;
1636
1637 stats->rx_crc_errors = raw->rx_crc_err;
1638 stats->rx_frame_errors = raw->rx_align_err;
1639 stats->rx_dropped = raw->rx_discards;
1640 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
1641 stats->rx_frame_errors + stats->rx_dropped;
1642
1643 stats->tx_window_errors = raw->tx_late_col;
1644 stats->tx_fifo_errors = raw->tx_discards;
1645 stats->tx_aborted_errors = raw->tx_exc_col;
1646 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
1647 stats->tx_aborted_errors;
1648
1649 stats->multicast = raw->rx_mcast;
1650 stats->collisions = raw->tx_total_col;
1651
1652 pstats->tx_pause_frames = raw->tx_pause;
1653 pstats->rx_pause_frames = raw->rx_pause;
1654
1655 spin_unlock(&mib->stats64_lock);
1656 }
1657
ksz88xx_r_mib_stats64(struct ksz_device * dev,int port)1658 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port)
1659 {
1660 struct ethtool_pause_stats *pstats;
1661 struct rtnl_link_stats64 *stats;
1662 struct ksz88xx_stats_raw *raw;
1663 struct ksz_port_mib *mib;
1664
1665 mib = &dev->ports[port].mib;
1666 stats = &mib->stats64;
1667 pstats = &mib->pause_stats;
1668 raw = (struct ksz88xx_stats_raw *)mib->counters;
1669
1670 spin_lock(&mib->stats64_lock);
1671
1672 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
1673 raw->rx_pause;
1674 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
1675 raw->tx_pause;
1676
1677 /* HW counters are counting bytes + FCS which is not acceptable
1678 * for rtnl_link_stats64 interface
1679 */
1680 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN;
1681 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN;
1682
1683 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
1684 raw->rx_oversize;
1685
1686 stats->rx_crc_errors = raw->rx_crc_err;
1687 stats->rx_frame_errors = raw->rx_align_err;
1688 stats->rx_dropped = raw->rx_discards;
1689 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
1690 stats->rx_frame_errors + stats->rx_dropped;
1691
1692 stats->tx_window_errors = raw->tx_late_col;
1693 stats->tx_fifo_errors = raw->tx_discards;
1694 stats->tx_aborted_errors = raw->tx_exc_col;
1695 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
1696 stats->tx_aborted_errors;
1697
1698 stats->multicast = raw->rx_mcast;
1699 stats->collisions = raw->tx_total_col;
1700
1701 pstats->tx_pause_frames = raw->tx_pause;
1702 pstats->rx_pause_frames = raw->rx_pause;
1703
1704 spin_unlock(&mib->stats64_lock);
1705 }
1706
ksz_get_stats64(struct dsa_switch * ds,int port,struct rtnl_link_stats64 * s)1707 static void ksz_get_stats64(struct dsa_switch *ds, int port,
1708 struct rtnl_link_stats64 *s)
1709 {
1710 struct ksz_device *dev = ds->priv;
1711 struct ksz_port_mib *mib;
1712
1713 mib = &dev->ports[port].mib;
1714
1715 spin_lock(&mib->stats64_lock);
1716 memcpy(s, &mib->stats64, sizeof(*s));
1717 spin_unlock(&mib->stats64_lock);
1718 }
1719
ksz_get_pause_stats(struct dsa_switch * ds,int port,struct ethtool_pause_stats * pause_stats)1720 static void ksz_get_pause_stats(struct dsa_switch *ds, int port,
1721 struct ethtool_pause_stats *pause_stats)
1722 {
1723 struct ksz_device *dev = ds->priv;
1724 struct ksz_port_mib *mib;
1725
1726 mib = &dev->ports[port].mib;
1727
1728 spin_lock(&mib->stats64_lock);
1729 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats));
1730 spin_unlock(&mib->stats64_lock);
1731 }
1732
ksz_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * buf)1733 static void ksz_get_strings(struct dsa_switch *ds, int port,
1734 u32 stringset, uint8_t *buf)
1735 {
1736 struct ksz_device *dev = ds->priv;
1737 int i;
1738
1739 if (stringset != ETH_SS_STATS)
1740 return;
1741
1742 for (i = 0; i < dev->info->mib_cnt; i++) {
1743 memcpy(buf + i * ETH_GSTRING_LEN,
1744 dev->info->mib_names[i].string, ETH_GSTRING_LEN);
1745 }
1746 }
1747
ksz_update_port_member(struct ksz_device * dev,int port)1748 static void ksz_update_port_member(struct ksz_device *dev, int port)
1749 {
1750 struct ksz_port *p = &dev->ports[port];
1751 struct dsa_switch *ds = dev->ds;
1752 u8 port_member = 0, cpu_port;
1753 const struct dsa_port *dp;
1754 int i, j;
1755
1756 if (!dsa_is_user_port(ds, port))
1757 return;
1758
1759 dp = dsa_to_port(ds, port);
1760 cpu_port = BIT(dsa_upstream_port(ds, port));
1761
1762 for (i = 0; i < ds->num_ports; i++) {
1763 const struct dsa_port *other_dp = dsa_to_port(ds, i);
1764 struct ksz_port *other_p = &dev->ports[i];
1765 u8 val = 0;
1766
1767 if (!dsa_is_user_port(ds, i))
1768 continue;
1769 if (port == i)
1770 continue;
1771 if (!dsa_port_bridge_same(dp, other_dp))
1772 continue;
1773 if (other_p->stp_state != BR_STATE_FORWARDING)
1774 continue;
1775
1776 if (p->stp_state == BR_STATE_FORWARDING) {
1777 val |= BIT(port);
1778 port_member |= BIT(i);
1779 }
1780
1781 /* Retain port [i]'s relationship to other ports than [port] */
1782 for (j = 0; j < ds->num_ports; j++) {
1783 const struct dsa_port *third_dp;
1784 struct ksz_port *third_p;
1785
1786 if (j == i)
1787 continue;
1788 if (j == port)
1789 continue;
1790 if (!dsa_is_user_port(ds, j))
1791 continue;
1792 third_p = &dev->ports[j];
1793 if (third_p->stp_state != BR_STATE_FORWARDING)
1794 continue;
1795 third_dp = dsa_to_port(ds, j);
1796 if (dsa_port_bridge_same(other_dp, third_dp))
1797 val |= BIT(j);
1798 }
1799
1800 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port);
1801 }
1802
1803 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port);
1804 }
1805
ksz_sw_mdio_read(struct mii_bus * bus,int addr,int regnum)1806 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
1807 {
1808 struct ksz_device *dev = bus->priv;
1809 u16 val;
1810 int ret;
1811
1812 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val);
1813 if (ret < 0)
1814 return ret;
1815
1816 return val;
1817 }
1818
ksz_sw_mdio_write(struct mii_bus * bus,int addr,int regnum,u16 val)1819 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
1820 u16 val)
1821 {
1822 struct ksz_device *dev = bus->priv;
1823
1824 return dev->dev_ops->w_phy(dev, addr, regnum, val);
1825 }
1826
ksz_irq_phy_setup(struct ksz_device * dev)1827 static int ksz_irq_phy_setup(struct ksz_device *dev)
1828 {
1829 struct dsa_switch *ds = dev->ds;
1830 int phy;
1831 int irq;
1832 int ret;
1833
1834 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) {
1835 if (BIT(phy) & ds->phys_mii_mask) {
1836 irq = irq_find_mapping(dev->ports[phy].pirq.domain,
1837 PORT_SRC_PHY_INT);
1838 if (irq < 0) {
1839 ret = irq;
1840 goto out;
1841 }
1842 ds->slave_mii_bus->irq[phy] = irq;
1843 }
1844 }
1845 return 0;
1846 out:
1847 while (phy--)
1848 if (BIT(phy) & ds->phys_mii_mask)
1849 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]);
1850
1851 return ret;
1852 }
1853
ksz_irq_phy_free(struct ksz_device * dev)1854 static void ksz_irq_phy_free(struct ksz_device *dev)
1855 {
1856 struct dsa_switch *ds = dev->ds;
1857 int phy;
1858
1859 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++)
1860 if (BIT(phy) & ds->phys_mii_mask)
1861 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]);
1862 }
1863
ksz_mdio_register(struct ksz_device * dev)1864 static int ksz_mdio_register(struct ksz_device *dev)
1865 {
1866 struct dsa_switch *ds = dev->ds;
1867 struct device_node *mdio_np;
1868 struct mii_bus *bus;
1869 int ret;
1870
1871 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio");
1872 if (!mdio_np)
1873 return 0;
1874
1875 bus = devm_mdiobus_alloc(ds->dev);
1876 if (!bus) {
1877 of_node_put(mdio_np);
1878 return -ENOMEM;
1879 }
1880
1881 bus->priv = dev;
1882 bus->read = ksz_sw_mdio_read;
1883 bus->write = ksz_sw_mdio_write;
1884 bus->name = "ksz slave smi";
1885 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index);
1886 bus->parent = ds->dev;
1887 bus->phy_mask = ~ds->phys_mii_mask;
1888
1889 ds->slave_mii_bus = bus;
1890
1891 if (dev->irq > 0) {
1892 ret = ksz_irq_phy_setup(dev);
1893 if (ret) {
1894 of_node_put(mdio_np);
1895 return ret;
1896 }
1897 }
1898
1899 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np);
1900 if (ret) {
1901 dev_err(ds->dev, "unable to register MDIO bus %s\n",
1902 bus->id);
1903 if (dev->irq > 0)
1904 ksz_irq_phy_free(dev);
1905 }
1906
1907 of_node_put(mdio_np);
1908
1909 return ret;
1910 }
1911
ksz_irq_mask(struct irq_data * d)1912 static void ksz_irq_mask(struct irq_data *d)
1913 {
1914 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
1915
1916 kirq->masked |= BIT(d->hwirq);
1917 }
1918
ksz_irq_unmask(struct irq_data * d)1919 static void ksz_irq_unmask(struct irq_data *d)
1920 {
1921 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
1922
1923 kirq->masked &= ~BIT(d->hwirq);
1924 }
1925
ksz_irq_bus_lock(struct irq_data * d)1926 static void ksz_irq_bus_lock(struct irq_data *d)
1927 {
1928 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
1929
1930 mutex_lock(&kirq->dev->lock_irq);
1931 }
1932
ksz_irq_bus_sync_unlock(struct irq_data * d)1933 static void ksz_irq_bus_sync_unlock(struct irq_data *d)
1934 {
1935 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
1936 struct ksz_device *dev = kirq->dev;
1937 int ret;
1938
1939 ret = ksz_write32(dev, kirq->reg_mask, kirq->masked);
1940 if (ret)
1941 dev_err(dev->dev, "failed to change IRQ mask\n");
1942
1943 mutex_unlock(&dev->lock_irq);
1944 }
1945
1946 static const struct irq_chip ksz_irq_chip = {
1947 .name = "ksz-irq",
1948 .irq_mask = ksz_irq_mask,
1949 .irq_unmask = ksz_irq_unmask,
1950 .irq_bus_lock = ksz_irq_bus_lock,
1951 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock,
1952 };
1953
ksz_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)1954 static int ksz_irq_domain_map(struct irq_domain *d,
1955 unsigned int irq, irq_hw_number_t hwirq)
1956 {
1957 irq_set_chip_data(irq, d->host_data);
1958 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq);
1959 irq_set_noprobe(irq);
1960
1961 return 0;
1962 }
1963
1964 static const struct irq_domain_ops ksz_irq_domain_ops = {
1965 .map = ksz_irq_domain_map,
1966 .xlate = irq_domain_xlate_twocell,
1967 };
1968
ksz_irq_free(struct ksz_irq * kirq)1969 static void ksz_irq_free(struct ksz_irq *kirq)
1970 {
1971 int irq, virq;
1972
1973 free_irq(kirq->irq_num, kirq);
1974
1975 for (irq = 0; irq < kirq->nirqs; irq++) {
1976 virq = irq_find_mapping(kirq->domain, irq);
1977 irq_dispose_mapping(virq);
1978 }
1979
1980 irq_domain_remove(kirq->domain);
1981 }
1982
ksz_irq_thread_fn(int irq,void * dev_id)1983 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id)
1984 {
1985 struct ksz_irq *kirq = dev_id;
1986 unsigned int nhandled = 0;
1987 struct ksz_device *dev;
1988 unsigned int sub_irq;
1989 u8 data;
1990 int ret;
1991 u8 n;
1992
1993 dev = kirq->dev;
1994
1995 /* Read interrupt status register */
1996 ret = ksz_read8(dev, kirq->reg_status, &data);
1997 if (ret)
1998 goto out;
1999
2000 for (n = 0; n < kirq->nirqs; ++n) {
2001 if (data & BIT(n)) {
2002 sub_irq = irq_find_mapping(kirq->domain, n);
2003 handle_nested_irq(sub_irq);
2004 ++nhandled;
2005 }
2006 }
2007 out:
2008 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
2009 }
2010
ksz_irq_common_setup(struct ksz_device * dev,struct ksz_irq * kirq)2011 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq)
2012 {
2013 int ret, n;
2014
2015 kirq->dev = dev;
2016 kirq->masked = ~0;
2017
2018 kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0,
2019 &ksz_irq_domain_ops, kirq);
2020 if (!kirq->domain)
2021 return -ENOMEM;
2022
2023 for (n = 0; n < kirq->nirqs; n++)
2024 irq_create_mapping(kirq->domain, n);
2025
2026 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn,
2027 IRQF_ONESHOT, kirq->name, kirq);
2028 if (ret)
2029 goto out;
2030
2031 return 0;
2032
2033 out:
2034 ksz_irq_free(kirq);
2035
2036 return ret;
2037 }
2038
ksz_girq_setup(struct ksz_device * dev)2039 static int ksz_girq_setup(struct ksz_device *dev)
2040 {
2041 struct ksz_irq *girq = &dev->girq;
2042
2043 girq->nirqs = dev->info->port_cnt;
2044 girq->reg_mask = REG_SW_PORT_INT_MASK__1;
2045 girq->reg_status = REG_SW_PORT_INT_STATUS__1;
2046 snprintf(girq->name, sizeof(girq->name), "global_port_irq");
2047
2048 girq->irq_num = dev->irq;
2049
2050 return ksz_irq_common_setup(dev, girq);
2051 }
2052
ksz_pirq_setup(struct ksz_device * dev,u8 p)2053 static int ksz_pirq_setup(struct ksz_device *dev, u8 p)
2054 {
2055 struct ksz_irq *pirq = &dev->ports[p].pirq;
2056
2057 pirq->nirqs = dev->info->port_nirqs;
2058 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK);
2059 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS);
2060 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p);
2061
2062 pirq->irq_num = irq_find_mapping(dev->girq.domain, p);
2063 if (pirq->irq_num < 0)
2064 return pirq->irq_num;
2065
2066 return ksz_irq_common_setup(dev, pirq);
2067 }
2068
ksz_setup(struct dsa_switch * ds)2069 static int ksz_setup(struct dsa_switch *ds)
2070 {
2071 struct ksz_device *dev = ds->priv;
2072 struct dsa_port *dp;
2073 struct ksz_port *p;
2074 const u16 *regs;
2075 int ret;
2076
2077 regs = dev->info->regs;
2078
2079 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
2080 dev->info->num_vlans, GFP_KERNEL);
2081 if (!dev->vlan_cache)
2082 return -ENOMEM;
2083
2084 ret = dev->dev_ops->reset(dev);
2085 if (ret) {
2086 dev_err(ds->dev, "failed to reset switch\n");
2087 return ret;
2088 }
2089
2090 /* set broadcast storm protection 10% rate */
2091 regmap_update_bits(dev->regmap[1], regs[S_BROADCAST_CTRL],
2092 BROADCAST_STORM_RATE,
2093 (BROADCAST_STORM_VALUE *
2094 BROADCAST_STORM_PROT_RATE) / 100);
2095
2096 dev->dev_ops->config_cpu_port(ds);
2097
2098 dev->dev_ops->enable_stp_addr(dev);
2099
2100 ds->num_tx_queues = dev->info->num_tx_queues;
2101
2102 regmap_update_bits(dev->regmap[0], regs[S_MULTICAST_CTRL],
2103 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE);
2104
2105 ksz_init_mib_timer(dev);
2106
2107 ds->configure_vlan_while_not_filtering = false;
2108
2109 if (dev->dev_ops->setup) {
2110 ret = dev->dev_ops->setup(ds);
2111 if (ret)
2112 return ret;
2113 }
2114
2115 /* Start with learning disabled on standalone user ports, and enabled
2116 * on the CPU port. In lack of other finer mechanisms, learning on the
2117 * CPU port will avoid flooding bridge local addresses on the network
2118 * in some cases.
2119 */
2120 p = &dev->ports[dev->cpu_port];
2121 p->learning = true;
2122
2123 if (dev->irq > 0) {
2124 ret = ksz_girq_setup(dev);
2125 if (ret)
2126 return ret;
2127
2128 dsa_switch_for_each_user_port(dp, dev->ds) {
2129 ret = ksz_pirq_setup(dev, dp->index);
2130 if (ret)
2131 goto out_girq;
2132
2133 ret = ksz_ptp_irq_setup(ds, dp->index);
2134 if (ret)
2135 goto out_pirq;
2136 }
2137 }
2138
2139 ret = ksz_ptp_clock_register(ds);
2140 if (ret) {
2141 dev_err(dev->dev, "Failed to register PTP clock: %d\n", ret);
2142 goto out_ptpirq;
2143 }
2144
2145 ret = ksz_mdio_register(dev);
2146 if (ret < 0) {
2147 dev_err(dev->dev, "failed to register the mdio");
2148 goto out_ptp_clock_unregister;
2149 }
2150
2151 /* start switch */
2152 regmap_update_bits(dev->regmap[0], regs[S_START_CTRL],
2153 SW_START, SW_START);
2154
2155 return 0;
2156
2157 out_ptp_clock_unregister:
2158 ksz_ptp_clock_unregister(ds);
2159 out_ptpirq:
2160 if (dev->irq > 0)
2161 dsa_switch_for_each_user_port(dp, dev->ds)
2162 ksz_ptp_irq_free(ds, dp->index);
2163 out_pirq:
2164 if (dev->irq > 0)
2165 dsa_switch_for_each_user_port(dp, dev->ds)
2166 ksz_irq_free(&dev->ports[dp->index].pirq);
2167 out_girq:
2168 if (dev->irq > 0)
2169 ksz_irq_free(&dev->girq);
2170
2171 return ret;
2172 }
2173
ksz_teardown(struct dsa_switch * ds)2174 static void ksz_teardown(struct dsa_switch *ds)
2175 {
2176 struct ksz_device *dev = ds->priv;
2177 struct dsa_port *dp;
2178
2179 ksz_ptp_clock_unregister(ds);
2180
2181 if (dev->irq > 0) {
2182 dsa_switch_for_each_user_port(dp, dev->ds) {
2183 ksz_ptp_irq_free(ds, dp->index);
2184
2185 ksz_irq_free(&dev->ports[dp->index].pirq);
2186 }
2187
2188 ksz_irq_free(&dev->girq);
2189 }
2190
2191 if (dev->dev_ops->teardown)
2192 dev->dev_ops->teardown(ds);
2193 }
2194
port_r_cnt(struct ksz_device * dev,int port)2195 static void port_r_cnt(struct ksz_device *dev, int port)
2196 {
2197 struct ksz_port_mib *mib = &dev->ports[port].mib;
2198 u64 *dropped;
2199
2200 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
2201 while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
2202 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
2203 &mib->counters[mib->cnt_ptr]);
2204 ++mib->cnt_ptr;
2205 }
2206
2207 /* last one in storage */
2208 dropped = &mib->counters[dev->info->mib_cnt];
2209
2210 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
2211 while (mib->cnt_ptr < dev->info->mib_cnt) {
2212 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
2213 dropped, &mib->counters[mib->cnt_ptr]);
2214 ++mib->cnt_ptr;
2215 }
2216 mib->cnt_ptr = 0;
2217 }
2218
ksz_mib_read_work(struct work_struct * work)2219 static void ksz_mib_read_work(struct work_struct *work)
2220 {
2221 struct ksz_device *dev = container_of(work, struct ksz_device,
2222 mib_read.work);
2223 struct ksz_port_mib *mib;
2224 struct ksz_port *p;
2225 int i;
2226
2227 for (i = 0; i < dev->info->port_cnt; i++) {
2228 if (dsa_is_unused_port(dev->ds, i))
2229 continue;
2230
2231 p = &dev->ports[i];
2232 mib = &p->mib;
2233 mutex_lock(&mib->cnt_mutex);
2234
2235 /* Only read MIB counters when the port is told to do.
2236 * If not, read only dropped counters when link is not up.
2237 */
2238 if (!p->read) {
2239 const struct dsa_port *dp = dsa_to_port(dev->ds, i);
2240
2241 if (!netif_carrier_ok(dp->slave))
2242 mib->cnt_ptr = dev->info->reg_mib_cnt;
2243 }
2244 port_r_cnt(dev, i);
2245 p->read = false;
2246
2247 if (dev->dev_ops->r_mib_stat64)
2248 dev->dev_ops->r_mib_stat64(dev, i);
2249
2250 mutex_unlock(&mib->cnt_mutex);
2251 }
2252
2253 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval);
2254 }
2255
ksz_init_mib_timer(struct ksz_device * dev)2256 void ksz_init_mib_timer(struct ksz_device *dev)
2257 {
2258 int i;
2259
2260 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work);
2261
2262 for (i = 0; i < dev->info->port_cnt; i++) {
2263 struct ksz_port_mib *mib = &dev->ports[i].mib;
2264
2265 dev->dev_ops->port_init_cnt(dev, i);
2266
2267 mib->cnt_ptr = 0;
2268 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64));
2269 }
2270 }
2271
ksz_phy_read16(struct dsa_switch * ds,int addr,int reg)2272 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg)
2273 {
2274 struct ksz_device *dev = ds->priv;
2275 u16 val = 0xffff;
2276 int ret;
2277
2278 ret = dev->dev_ops->r_phy(dev, addr, reg, &val);
2279 if (ret)
2280 return ret;
2281
2282 return val;
2283 }
2284
ksz_phy_write16(struct dsa_switch * ds,int addr,int reg,u16 val)2285 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
2286 {
2287 struct ksz_device *dev = ds->priv;
2288 int ret;
2289
2290 ret = dev->dev_ops->w_phy(dev, addr, reg, val);
2291 if (ret)
2292 return ret;
2293
2294 return 0;
2295 }
2296
ksz_get_phy_flags(struct dsa_switch * ds,int port)2297 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port)
2298 {
2299 struct ksz_device *dev = ds->priv;
2300
2301 if (dev->chip_id == KSZ8830_CHIP_ID) {
2302 /* Silicon Errata Sheet (DS80000830A):
2303 * Port 1 does not work with LinkMD Cable-Testing.
2304 * Port 1 does not respond to received PAUSE control frames.
2305 */
2306 if (!port)
2307 return MICREL_KSZ8_P1_ERRATA;
2308 }
2309
2310 return 0;
2311 }
2312
ksz_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)2313 static void ksz_mac_link_down(struct dsa_switch *ds, int port,
2314 unsigned int mode, phy_interface_t interface)
2315 {
2316 struct ksz_device *dev = ds->priv;
2317 struct ksz_port *p = &dev->ports[port];
2318
2319 /* Read all MIB counters when the link is going down. */
2320 p->read = true;
2321 /* timer started */
2322 if (dev->mib_read_interval)
2323 schedule_delayed_work(&dev->mib_read, 0);
2324 }
2325
ksz_sset_count(struct dsa_switch * ds,int port,int sset)2326 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset)
2327 {
2328 struct ksz_device *dev = ds->priv;
2329
2330 if (sset != ETH_SS_STATS)
2331 return 0;
2332
2333 return dev->info->mib_cnt;
2334 }
2335
ksz_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * buf)2336 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port,
2337 uint64_t *buf)
2338 {
2339 const struct dsa_port *dp = dsa_to_port(ds, port);
2340 struct ksz_device *dev = ds->priv;
2341 struct ksz_port_mib *mib;
2342
2343 mib = &dev->ports[port].mib;
2344 mutex_lock(&mib->cnt_mutex);
2345
2346 /* Only read dropped counters if no link. */
2347 if (!netif_carrier_ok(dp->slave))
2348 mib->cnt_ptr = dev->info->reg_mib_cnt;
2349 port_r_cnt(dev, port);
2350 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64));
2351 mutex_unlock(&mib->cnt_mutex);
2352 }
2353
ksz_port_bridge_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)2354 static int ksz_port_bridge_join(struct dsa_switch *ds, int port,
2355 struct dsa_bridge bridge,
2356 bool *tx_fwd_offload,
2357 struct netlink_ext_ack *extack)
2358 {
2359 /* port_stp_state_set() will be called after to put the port in
2360 * appropriate state so there is no need to do anything.
2361 */
2362
2363 return 0;
2364 }
2365
ksz_port_bridge_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)2366 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port,
2367 struct dsa_bridge bridge)
2368 {
2369 /* port_stp_state_set() will be called after to put the port in
2370 * forwarding state so there is no need to do anything.
2371 */
2372 }
2373
ksz_port_fast_age(struct dsa_switch * ds,int port)2374 static void ksz_port_fast_age(struct dsa_switch *ds, int port)
2375 {
2376 struct ksz_device *dev = ds->priv;
2377
2378 dev->dev_ops->flush_dyn_mac_table(dev, port);
2379 }
2380
ksz_set_ageing_time(struct dsa_switch * ds,unsigned int msecs)2381 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
2382 {
2383 struct ksz_device *dev = ds->priv;
2384
2385 if (!dev->dev_ops->set_ageing_time)
2386 return -EOPNOTSUPP;
2387
2388 return dev->dev_ops->set_ageing_time(dev, msecs);
2389 }
2390
ksz_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)2391 static int ksz_port_fdb_add(struct dsa_switch *ds, int port,
2392 const unsigned char *addr, u16 vid,
2393 struct dsa_db db)
2394 {
2395 struct ksz_device *dev = ds->priv;
2396
2397 if (!dev->dev_ops->fdb_add)
2398 return -EOPNOTSUPP;
2399
2400 return dev->dev_ops->fdb_add(dev, port, addr, vid, db);
2401 }
2402
ksz_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)2403 static int ksz_port_fdb_del(struct dsa_switch *ds, int port,
2404 const unsigned char *addr,
2405 u16 vid, struct dsa_db db)
2406 {
2407 struct ksz_device *dev = ds->priv;
2408
2409 if (!dev->dev_ops->fdb_del)
2410 return -EOPNOTSUPP;
2411
2412 return dev->dev_ops->fdb_del(dev, port, addr, vid, db);
2413 }
2414
ksz_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)2415 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port,
2416 dsa_fdb_dump_cb_t *cb, void *data)
2417 {
2418 struct ksz_device *dev = ds->priv;
2419
2420 if (!dev->dev_ops->fdb_dump)
2421 return -EOPNOTSUPP;
2422
2423 return dev->dev_ops->fdb_dump(dev, port, cb, data);
2424 }
2425
ksz_port_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)2426 static int ksz_port_mdb_add(struct dsa_switch *ds, int port,
2427 const struct switchdev_obj_port_mdb *mdb,
2428 struct dsa_db db)
2429 {
2430 struct ksz_device *dev = ds->priv;
2431
2432 if (!dev->dev_ops->mdb_add)
2433 return -EOPNOTSUPP;
2434
2435 return dev->dev_ops->mdb_add(dev, port, mdb, db);
2436 }
2437
ksz_port_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)2438 static int ksz_port_mdb_del(struct dsa_switch *ds, int port,
2439 const struct switchdev_obj_port_mdb *mdb,
2440 struct dsa_db db)
2441 {
2442 struct ksz_device *dev = ds->priv;
2443
2444 if (!dev->dev_ops->mdb_del)
2445 return -EOPNOTSUPP;
2446
2447 return dev->dev_ops->mdb_del(dev, port, mdb, db);
2448 }
2449
ksz_enable_port(struct dsa_switch * ds,int port,struct phy_device * phy)2450 static int ksz_enable_port(struct dsa_switch *ds, int port,
2451 struct phy_device *phy)
2452 {
2453 struct ksz_device *dev = ds->priv;
2454
2455 if (!dsa_is_user_port(ds, port))
2456 return 0;
2457
2458 /* setup slave port */
2459 dev->dev_ops->port_setup(dev, port, false);
2460
2461 /* port_stp_state_set() will be called after to enable the port so
2462 * there is no need to do anything.
2463 */
2464
2465 return 0;
2466 }
2467
ksz_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)2468 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
2469 {
2470 struct ksz_device *dev = ds->priv;
2471 struct ksz_port *p;
2472 const u16 *regs;
2473 u8 data;
2474
2475 regs = dev->info->regs;
2476
2477 ksz_pread8(dev, port, regs[P_STP_CTRL], &data);
2478 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
2479
2480 p = &dev->ports[port];
2481
2482 switch (state) {
2483 case BR_STATE_DISABLED:
2484 data |= PORT_LEARN_DISABLE;
2485 break;
2486 case BR_STATE_LISTENING:
2487 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
2488 break;
2489 case BR_STATE_LEARNING:
2490 data |= PORT_RX_ENABLE;
2491 if (!p->learning)
2492 data |= PORT_LEARN_DISABLE;
2493 break;
2494 case BR_STATE_FORWARDING:
2495 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2496 if (!p->learning)
2497 data |= PORT_LEARN_DISABLE;
2498 break;
2499 case BR_STATE_BLOCKING:
2500 data |= PORT_LEARN_DISABLE;
2501 break;
2502 default:
2503 dev_err(ds->dev, "invalid STP state: %d\n", state);
2504 return;
2505 }
2506
2507 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data);
2508
2509 p->stp_state = state;
2510
2511 ksz_update_port_member(dev, port);
2512 }
2513
ksz_port_pre_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)2514 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port,
2515 struct switchdev_brport_flags flags,
2516 struct netlink_ext_ack *extack)
2517 {
2518 if (flags.mask & ~BR_LEARNING)
2519 return -EINVAL;
2520
2521 return 0;
2522 }
2523
ksz_port_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)2524 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port,
2525 struct switchdev_brport_flags flags,
2526 struct netlink_ext_ack *extack)
2527 {
2528 struct ksz_device *dev = ds->priv;
2529 struct ksz_port *p = &dev->ports[port];
2530
2531 if (flags.mask & BR_LEARNING) {
2532 p->learning = !!(flags.val & BR_LEARNING);
2533
2534 /* Make the change take effect immediately */
2535 ksz_port_stp_state_set(ds, port, p->stp_state);
2536 }
2537
2538 return 0;
2539 }
2540
ksz_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)2541 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds,
2542 int port,
2543 enum dsa_tag_protocol mp)
2544 {
2545 struct ksz_device *dev = ds->priv;
2546 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE;
2547
2548 if (dev->chip_id == KSZ8795_CHIP_ID ||
2549 dev->chip_id == KSZ8794_CHIP_ID ||
2550 dev->chip_id == KSZ8765_CHIP_ID)
2551 proto = DSA_TAG_PROTO_KSZ8795;
2552
2553 if (dev->chip_id == KSZ8830_CHIP_ID ||
2554 dev->chip_id == KSZ8563_CHIP_ID ||
2555 dev->chip_id == KSZ9893_CHIP_ID ||
2556 dev->chip_id == KSZ9563_CHIP_ID)
2557 proto = DSA_TAG_PROTO_KSZ9893;
2558
2559 if (dev->chip_id == KSZ9477_CHIP_ID ||
2560 dev->chip_id == KSZ9896_CHIP_ID ||
2561 dev->chip_id == KSZ9897_CHIP_ID ||
2562 dev->chip_id == KSZ9567_CHIP_ID)
2563 proto = DSA_TAG_PROTO_KSZ9477;
2564
2565 if (is_lan937x(dev))
2566 proto = DSA_TAG_PROTO_LAN937X_VALUE;
2567
2568 return proto;
2569 }
2570
ksz_connect_tag_protocol(struct dsa_switch * ds,enum dsa_tag_protocol proto)2571 static int ksz_connect_tag_protocol(struct dsa_switch *ds,
2572 enum dsa_tag_protocol proto)
2573 {
2574 struct ksz_tagger_data *tagger_data;
2575
2576 tagger_data = ksz_tagger_data(ds);
2577 tagger_data->xmit_work_fn = ksz_port_deferred_xmit;
2578
2579 return 0;
2580 }
2581
ksz_port_vlan_filtering(struct dsa_switch * ds,int port,bool flag,struct netlink_ext_ack * extack)2582 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port,
2583 bool flag, struct netlink_ext_ack *extack)
2584 {
2585 struct ksz_device *dev = ds->priv;
2586
2587 if (!dev->dev_ops->vlan_filtering)
2588 return -EOPNOTSUPP;
2589
2590 return dev->dev_ops->vlan_filtering(dev, port, flag, extack);
2591 }
2592
ksz_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)2593 static int ksz_port_vlan_add(struct dsa_switch *ds, int port,
2594 const struct switchdev_obj_port_vlan *vlan,
2595 struct netlink_ext_ack *extack)
2596 {
2597 struct ksz_device *dev = ds->priv;
2598
2599 if (!dev->dev_ops->vlan_add)
2600 return -EOPNOTSUPP;
2601
2602 return dev->dev_ops->vlan_add(dev, port, vlan, extack);
2603 }
2604
ksz_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)2605 static int ksz_port_vlan_del(struct dsa_switch *ds, int port,
2606 const struct switchdev_obj_port_vlan *vlan)
2607 {
2608 struct ksz_device *dev = ds->priv;
2609
2610 if (!dev->dev_ops->vlan_del)
2611 return -EOPNOTSUPP;
2612
2613 return dev->dev_ops->vlan_del(dev, port, vlan);
2614 }
2615
ksz_port_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress,struct netlink_ext_ack * extack)2616 static int ksz_port_mirror_add(struct dsa_switch *ds, int port,
2617 struct dsa_mall_mirror_tc_entry *mirror,
2618 bool ingress, struct netlink_ext_ack *extack)
2619 {
2620 struct ksz_device *dev = ds->priv;
2621
2622 if (!dev->dev_ops->mirror_add)
2623 return -EOPNOTSUPP;
2624
2625 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack);
2626 }
2627
ksz_port_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)2628 static void ksz_port_mirror_del(struct dsa_switch *ds, int port,
2629 struct dsa_mall_mirror_tc_entry *mirror)
2630 {
2631 struct ksz_device *dev = ds->priv;
2632
2633 if (dev->dev_ops->mirror_del)
2634 dev->dev_ops->mirror_del(dev, port, mirror);
2635 }
2636
ksz_change_mtu(struct dsa_switch * ds,int port,int mtu)2637 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu)
2638 {
2639 struct ksz_device *dev = ds->priv;
2640
2641 if (!dev->dev_ops->change_mtu)
2642 return -EOPNOTSUPP;
2643
2644 return dev->dev_ops->change_mtu(dev, port, mtu);
2645 }
2646
ksz_max_mtu(struct dsa_switch * ds,int port)2647 static int ksz_max_mtu(struct dsa_switch *ds, int port)
2648 {
2649 struct ksz_device *dev = ds->priv;
2650
2651 switch (dev->chip_id) {
2652 case KSZ8795_CHIP_ID:
2653 case KSZ8794_CHIP_ID:
2654 case KSZ8765_CHIP_ID:
2655 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
2656 case KSZ8830_CHIP_ID:
2657 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
2658 case KSZ8563_CHIP_ID:
2659 case KSZ9477_CHIP_ID:
2660 case KSZ9563_CHIP_ID:
2661 case KSZ9567_CHIP_ID:
2662 case KSZ9893_CHIP_ID:
2663 case KSZ9896_CHIP_ID:
2664 case KSZ9897_CHIP_ID:
2665 case LAN9370_CHIP_ID:
2666 case LAN9371_CHIP_ID:
2667 case LAN9372_CHIP_ID:
2668 case LAN9373_CHIP_ID:
2669 case LAN9374_CHIP_ID:
2670 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
2671 }
2672
2673 return -EOPNOTSUPP;
2674 }
2675
ksz_validate_eee(struct dsa_switch * ds,int port)2676 static int ksz_validate_eee(struct dsa_switch *ds, int port)
2677 {
2678 struct ksz_device *dev = ds->priv;
2679
2680 if (!dev->info->internal_phy[port])
2681 return -EOPNOTSUPP;
2682
2683 switch (dev->chip_id) {
2684 case KSZ8563_CHIP_ID:
2685 case KSZ9477_CHIP_ID:
2686 case KSZ9563_CHIP_ID:
2687 case KSZ9567_CHIP_ID:
2688 case KSZ9893_CHIP_ID:
2689 case KSZ9896_CHIP_ID:
2690 case KSZ9897_CHIP_ID:
2691 return 0;
2692 }
2693
2694 return -EOPNOTSUPP;
2695 }
2696
ksz_get_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)2697 static int ksz_get_mac_eee(struct dsa_switch *ds, int port,
2698 struct ethtool_eee *e)
2699 {
2700 int ret;
2701
2702 ret = ksz_validate_eee(ds, port);
2703 if (ret)
2704 return ret;
2705
2706 /* There is no documented control of Tx LPI configuration. */
2707 e->tx_lpi_enabled = true;
2708
2709 /* There is no documented control of Tx LPI timer. According to tests
2710 * Tx LPI timer seems to be set by default to minimal value.
2711 */
2712 e->tx_lpi_timer = 0;
2713
2714 return 0;
2715 }
2716
ksz_set_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)2717 static int ksz_set_mac_eee(struct dsa_switch *ds, int port,
2718 struct ethtool_eee *e)
2719 {
2720 struct ksz_device *dev = ds->priv;
2721 int ret;
2722
2723 ret = ksz_validate_eee(ds, port);
2724 if (ret)
2725 return ret;
2726
2727 if (!e->tx_lpi_enabled) {
2728 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n");
2729 return -EINVAL;
2730 }
2731
2732 if (e->tx_lpi_timer) {
2733 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n");
2734 return -EINVAL;
2735 }
2736
2737 return 0;
2738 }
2739
ksz_set_xmii(struct ksz_device * dev,int port,phy_interface_t interface)2740 static void ksz_set_xmii(struct ksz_device *dev, int port,
2741 phy_interface_t interface)
2742 {
2743 const u8 *bitval = dev->info->xmii_ctrl1;
2744 struct ksz_port *p = &dev->ports[port];
2745 const u16 *regs = dev->info->regs;
2746 u8 data8;
2747
2748 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2749
2750 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE |
2751 P_RGMII_ID_EG_ENABLE);
2752
2753 switch (interface) {
2754 case PHY_INTERFACE_MODE_MII:
2755 data8 |= bitval[P_MII_SEL];
2756 break;
2757 case PHY_INTERFACE_MODE_RMII:
2758 data8 |= bitval[P_RMII_SEL];
2759 break;
2760 case PHY_INTERFACE_MODE_GMII:
2761 data8 |= bitval[P_GMII_SEL];
2762 break;
2763 case PHY_INTERFACE_MODE_RGMII:
2764 case PHY_INTERFACE_MODE_RGMII_ID:
2765 case PHY_INTERFACE_MODE_RGMII_TXID:
2766 case PHY_INTERFACE_MODE_RGMII_RXID:
2767 data8 |= bitval[P_RGMII_SEL];
2768 /* On KSZ9893, disable RGMII in-band status support */
2769 if (dev->chip_id == KSZ9893_CHIP_ID ||
2770 dev->chip_id == KSZ8563_CHIP_ID ||
2771 dev->chip_id == KSZ9563_CHIP_ID)
2772 data8 &= ~P_MII_MAC_MODE;
2773 break;
2774 default:
2775 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
2776 phy_modes(interface), port);
2777 return;
2778 }
2779
2780 if (p->rgmii_tx_val)
2781 data8 |= P_RGMII_ID_EG_ENABLE;
2782
2783 if (p->rgmii_rx_val)
2784 data8 |= P_RGMII_ID_IG_ENABLE;
2785
2786 /* Write the updated value */
2787 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
2788 }
2789
ksz_get_xmii(struct ksz_device * dev,int port,bool gbit)2790 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit)
2791 {
2792 const u8 *bitval = dev->info->xmii_ctrl1;
2793 const u16 *regs = dev->info->regs;
2794 phy_interface_t interface;
2795 u8 data8;
2796 u8 val;
2797
2798 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2799
2800 val = FIELD_GET(P_MII_SEL_M, data8);
2801
2802 if (val == bitval[P_MII_SEL]) {
2803 if (gbit)
2804 interface = PHY_INTERFACE_MODE_GMII;
2805 else
2806 interface = PHY_INTERFACE_MODE_MII;
2807 } else if (val == bitval[P_RMII_SEL]) {
2808 interface = PHY_INTERFACE_MODE_RGMII;
2809 } else {
2810 interface = PHY_INTERFACE_MODE_RGMII;
2811 if (data8 & P_RGMII_ID_EG_ENABLE)
2812 interface = PHY_INTERFACE_MODE_RGMII_TXID;
2813 if (data8 & P_RGMII_ID_IG_ENABLE) {
2814 interface = PHY_INTERFACE_MODE_RGMII_RXID;
2815 if (data8 & P_RGMII_ID_EG_ENABLE)
2816 interface = PHY_INTERFACE_MODE_RGMII_ID;
2817 }
2818 }
2819
2820 return interface;
2821 }
2822
ksz_phylink_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)2823 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port,
2824 unsigned int mode,
2825 const struct phylink_link_state *state)
2826 {
2827 struct ksz_device *dev = ds->priv;
2828
2829 if (ksz_is_ksz88x3(dev))
2830 return;
2831
2832 /* Internal PHYs */
2833 if (dev->info->internal_phy[port])
2834 return;
2835
2836 if (phylink_autoneg_inband(mode)) {
2837 dev_err(dev->dev, "In-band AN not supported!\n");
2838 return;
2839 }
2840
2841 ksz_set_xmii(dev, port, state->interface);
2842
2843 if (dev->dev_ops->phylink_mac_config)
2844 dev->dev_ops->phylink_mac_config(dev, port, mode, state);
2845
2846 if (dev->dev_ops->setup_rgmii_delay)
2847 dev->dev_ops->setup_rgmii_delay(dev, port);
2848 }
2849
ksz_get_gbit(struct ksz_device * dev,int port)2850 bool ksz_get_gbit(struct ksz_device *dev, int port)
2851 {
2852 const u8 *bitval = dev->info->xmii_ctrl1;
2853 const u16 *regs = dev->info->regs;
2854 bool gbit = false;
2855 u8 data8;
2856 bool val;
2857
2858 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2859
2860 val = FIELD_GET(P_GMII_1GBIT_M, data8);
2861
2862 if (val == bitval[P_GMII_1GBIT])
2863 gbit = true;
2864
2865 return gbit;
2866 }
2867
ksz_set_gbit(struct ksz_device * dev,int port,bool gbit)2868 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
2869 {
2870 const u8 *bitval = dev->info->xmii_ctrl1;
2871 const u16 *regs = dev->info->regs;
2872 u8 data8;
2873
2874 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2875
2876 data8 &= ~P_GMII_1GBIT_M;
2877
2878 if (gbit)
2879 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]);
2880 else
2881 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]);
2882
2883 /* Write the updated value */
2884 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
2885 }
2886
ksz_set_100_10mbit(struct ksz_device * dev,int port,int speed)2887 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
2888 {
2889 const u8 *bitval = dev->info->xmii_ctrl0;
2890 const u16 *regs = dev->info->regs;
2891 u8 data8;
2892
2893 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8);
2894
2895 data8 &= ~P_MII_100MBIT_M;
2896
2897 if (speed == SPEED_100)
2898 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]);
2899 else
2900 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]);
2901
2902 /* Write the updated value */
2903 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
2904 }
2905
ksz_port_set_xmii_speed(struct ksz_device * dev,int port,int speed)2906 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed)
2907 {
2908 if (speed == SPEED_1000)
2909 ksz_set_gbit(dev, port, true);
2910 else
2911 ksz_set_gbit(dev, port, false);
2912
2913 if (speed == SPEED_100 || speed == SPEED_10)
2914 ksz_set_100_10mbit(dev, port, speed);
2915 }
2916
ksz_duplex_flowctrl(struct ksz_device * dev,int port,int duplex,bool tx_pause,bool rx_pause)2917 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex,
2918 bool tx_pause, bool rx_pause)
2919 {
2920 const u8 *bitval = dev->info->xmii_ctrl0;
2921 const u32 *masks = dev->info->masks;
2922 const u16 *regs = dev->info->regs;
2923 u8 mask;
2924 u8 val;
2925
2926 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] |
2927 masks[P_MII_RX_FLOW_CTRL];
2928
2929 if (duplex == DUPLEX_FULL)
2930 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]);
2931 else
2932 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]);
2933
2934 if (tx_pause)
2935 val |= masks[P_MII_TX_FLOW_CTRL];
2936
2937 if (rx_pause)
2938 val |= masks[P_MII_RX_FLOW_CTRL];
2939
2940 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val);
2941 }
2942
ksz9477_phylink_mac_link_up(struct ksz_device * dev,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)2943 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port,
2944 unsigned int mode,
2945 phy_interface_t interface,
2946 struct phy_device *phydev, int speed,
2947 int duplex, bool tx_pause,
2948 bool rx_pause)
2949 {
2950 struct ksz_port *p;
2951
2952 p = &dev->ports[port];
2953
2954 /* Internal PHYs */
2955 if (dev->info->internal_phy[port])
2956 return;
2957
2958 p->phydev.speed = speed;
2959
2960 ksz_port_set_xmii_speed(dev, port, speed);
2961
2962 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause);
2963 }
2964
ksz_phylink_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)2965 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port,
2966 unsigned int mode,
2967 phy_interface_t interface,
2968 struct phy_device *phydev, int speed,
2969 int duplex, bool tx_pause, bool rx_pause)
2970 {
2971 struct ksz_device *dev = ds->priv;
2972
2973 if (dev->dev_ops->phylink_mac_link_up)
2974 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface,
2975 phydev, speed, duplex,
2976 tx_pause, rx_pause);
2977 }
2978
ksz_switch_detect(struct ksz_device * dev)2979 static int ksz_switch_detect(struct ksz_device *dev)
2980 {
2981 u8 id1, id2, id4;
2982 u16 id16;
2983 u32 id32;
2984 int ret;
2985
2986 /* read chip id */
2987 ret = ksz_read16(dev, REG_CHIP_ID0, &id16);
2988 if (ret)
2989 return ret;
2990
2991 id1 = FIELD_GET(SW_FAMILY_ID_M, id16);
2992 id2 = FIELD_GET(SW_CHIP_ID_M, id16);
2993
2994 switch (id1) {
2995 case KSZ87_FAMILY_ID:
2996 if (id2 == KSZ87_CHIP_ID_95) {
2997 u8 val;
2998
2999 dev->chip_id = KSZ8795_CHIP_ID;
3000
3001 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val);
3002 if (val & KSZ8_PORT_FIBER_MODE)
3003 dev->chip_id = KSZ8765_CHIP_ID;
3004 } else if (id2 == KSZ87_CHIP_ID_94) {
3005 dev->chip_id = KSZ8794_CHIP_ID;
3006 } else {
3007 return -ENODEV;
3008 }
3009 break;
3010 case KSZ88_FAMILY_ID:
3011 if (id2 == KSZ88_CHIP_ID_63)
3012 dev->chip_id = KSZ8830_CHIP_ID;
3013 else
3014 return -ENODEV;
3015 break;
3016 default:
3017 ret = ksz_read32(dev, REG_CHIP_ID0, &id32);
3018 if (ret)
3019 return ret;
3020
3021 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32);
3022 id32 &= ~0xFF;
3023
3024 switch (id32) {
3025 case KSZ9477_CHIP_ID:
3026 case KSZ9896_CHIP_ID:
3027 case KSZ9897_CHIP_ID:
3028 case KSZ9567_CHIP_ID:
3029 case LAN9370_CHIP_ID:
3030 case LAN9371_CHIP_ID:
3031 case LAN9372_CHIP_ID:
3032 case LAN9373_CHIP_ID:
3033 case LAN9374_CHIP_ID:
3034 dev->chip_id = id32;
3035 break;
3036 case KSZ9893_CHIP_ID:
3037 ret = ksz_read8(dev, REG_CHIP_ID4,
3038 &id4);
3039 if (ret)
3040 return ret;
3041
3042 if (id4 == SKU_ID_KSZ8563)
3043 dev->chip_id = KSZ8563_CHIP_ID;
3044 else if (id4 == SKU_ID_KSZ9563)
3045 dev->chip_id = KSZ9563_CHIP_ID;
3046 else
3047 dev->chip_id = KSZ9893_CHIP_ID;
3048
3049 break;
3050 default:
3051 dev_err(dev->dev,
3052 "unsupported switch detected %x)\n", id32);
3053 return -ENODEV;
3054 }
3055 }
3056 return 0;
3057 }
3058
3059 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth
3060 * is converted to Hex-decimal using the successive multiplication method. On
3061 * every step, integer part is taken and decimal part is carry forwarded.
3062 */
cinc_cal(s32 idle_slope,s32 send_slope,u32 * bw)3063 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw)
3064 {
3065 u32 cinc = 0;
3066 u32 txrate;
3067 u32 rate;
3068 u8 temp;
3069 u8 i;
3070
3071 txrate = idle_slope - send_slope;
3072
3073 if (!txrate)
3074 return -EINVAL;
3075
3076 rate = idle_slope;
3077
3078 /* 24 bit register */
3079 for (i = 0; i < 6; i++) {
3080 rate = rate * 16;
3081
3082 temp = rate / txrate;
3083
3084 rate %= txrate;
3085
3086 cinc = ((cinc << 4) | temp);
3087 }
3088
3089 *bw = cinc;
3090
3091 return 0;
3092 }
3093
ksz_setup_tc_cbs(struct dsa_switch * ds,int port,struct tc_cbs_qopt_offload * qopt)3094 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port,
3095 struct tc_cbs_qopt_offload *qopt)
3096 {
3097 struct ksz_device *dev = ds->priv;
3098 int ret;
3099 u32 bw;
3100
3101 if (!dev->info->tc_cbs_supported)
3102 return -EOPNOTSUPP;
3103
3104 if (qopt->queue > dev->info->num_tx_queues)
3105 return -EINVAL;
3106
3107 /* Queue Selection */
3108 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue);
3109 if (ret)
3110 return ret;
3111
3112 if (!qopt->enable)
3113 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0,
3114 KSZ_CBS_DISABLE);
3115
3116 /* High Credit */
3117 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK,
3118 qopt->hicredit);
3119 if (ret)
3120 return ret;
3121
3122 /* Low Credit */
3123 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK,
3124 qopt->locredit);
3125 if (ret)
3126 return ret;
3127
3128 /* Credit Increment Register */
3129 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw);
3130 if (ret)
3131 return ret;
3132
3133 if (dev->dev_ops->tc_cbs_set_cinc) {
3134 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw);
3135 if (ret)
3136 return ret;
3137 }
3138
3139 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0,
3140 KSZ_CBS_ENABLE);
3141 }
3142
ksz_setup_tc(struct dsa_switch * ds,int port,enum tc_setup_type type,void * type_data)3143 static int ksz_setup_tc(struct dsa_switch *ds, int port,
3144 enum tc_setup_type type, void *type_data)
3145 {
3146 switch (type) {
3147 case TC_SETUP_QDISC_CBS:
3148 return ksz_setup_tc_cbs(ds, port, type_data);
3149 default:
3150 return -EOPNOTSUPP;
3151 }
3152 }
3153
3154 static const struct dsa_switch_ops ksz_switch_ops = {
3155 .get_tag_protocol = ksz_get_tag_protocol,
3156 .connect_tag_protocol = ksz_connect_tag_protocol,
3157 .get_phy_flags = ksz_get_phy_flags,
3158 .setup = ksz_setup,
3159 .teardown = ksz_teardown,
3160 .phy_read = ksz_phy_read16,
3161 .phy_write = ksz_phy_write16,
3162 .phylink_get_caps = ksz_phylink_get_caps,
3163 .phylink_mac_config = ksz_phylink_mac_config,
3164 .phylink_mac_link_up = ksz_phylink_mac_link_up,
3165 .phylink_mac_link_down = ksz_mac_link_down,
3166 .port_enable = ksz_enable_port,
3167 .set_ageing_time = ksz_set_ageing_time,
3168 .get_strings = ksz_get_strings,
3169 .get_ethtool_stats = ksz_get_ethtool_stats,
3170 .get_sset_count = ksz_sset_count,
3171 .port_bridge_join = ksz_port_bridge_join,
3172 .port_bridge_leave = ksz_port_bridge_leave,
3173 .port_stp_state_set = ksz_port_stp_state_set,
3174 .port_pre_bridge_flags = ksz_port_pre_bridge_flags,
3175 .port_bridge_flags = ksz_port_bridge_flags,
3176 .port_fast_age = ksz_port_fast_age,
3177 .port_vlan_filtering = ksz_port_vlan_filtering,
3178 .port_vlan_add = ksz_port_vlan_add,
3179 .port_vlan_del = ksz_port_vlan_del,
3180 .port_fdb_dump = ksz_port_fdb_dump,
3181 .port_fdb_add = ksz_port_fdb_add,
3182 .port_fdb_del = ksz_port_fdb_del,
3183 .port_mdb_add = ksz_port_mdb_add,
3184 .port_mdb_del = ksz_port_mdb_del,
3185 .port_mirror_add = ksz_port_mirror_add,
3186 .port_mirror_del = ksz_port_mirror_del,
3187 .get_stats64 = ksz_get_stats64,
3188 .get_pause_stats = ksz_get_pause_stats,
3189 .port_change_mtu = ksz_change_mtu,
3190 .port_max_mtu = ksz_max_mtu,
3191 .get_ts_info = ksz_get_ts_info,
3192 .port_hwtstamp_get = ksz_hwtstamp_get,
3193 .port_hwtstamp_set = ksz_hwtstamp_set,
3194 .port_txtstamp = ksz_port_txtstamp,
3195 .port_rxtstamp = ksz_port_rxtstamp,
3196 .port_setup_tc = ksz_setup_tc,
3197 .get_mac_eee = ksz_get_mac_eee,
3198 .set_mac_eee = ksz_set_mac_eee,
3199 };
3200
ksz_switch_alloc(struct device * base,void * priv)3201 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv)
3202 {
3203 struct dsa_switch *ds;
3204 struct ksz_device *swdev;
3205
3206 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
3207 if (!ds)
3208 return NULL;
3209
3210 ds->dev = base;
3211 ds->num_ports = DSA_MAX_PORTS;
3212 ds->ops = &ksz_switch_ops;
3213
3214 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL);
3215 if (!swdev)
3216 return NULL;
3217
3218 ds->priv = swdev;
3219 swdev->dev = base;
3220
3221 swdev->ds = ds;
3222 swdev->priv = priv;
3223
3224 return swdev;
3225 }
3226 EXPORT_SYMBOL(ksz_switch_alloc);
3227
ksz_parse_rgmii_delay(struct ksz_device * dev,int port_num,struct device_node * port_dn)3228 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num,
3229 struct device_node *port_dn)
3230 {
3231 phy_interface_t phy_mode = dev->ports[port_num].interface;
3232 int rx_delay = -1, tx_delay = -1;
3233
3234 if (!phy_interface_mode_is_rgmii(phy_mode))
3235 return;
3236
3237 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
3238 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
3239
3240 if (rx_delay == -1 && tx_delay == -1) {
3241 dev_warn(dev->dev,
3242 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
3243 "please update device tree to specify \"rx-internal-delay-ps\" and "
3244 "\"tx-internal-delay-ps\"",
3245 port_num);
3246
3247 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
3248 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
3249 rx_delay = 2000;
3250
3251 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
3252 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
3253 tx_delay = 2000;
3254 }
3255
3256 if (rx_delay < 0)
3257 rx_delay = 0;
3258 if (tx_delay < 0)
3259 tx_delay = 0;
3260
3261 dev->ports[port_num].rgmii_rx_val = rx_delay;
3262 dev->ports[port_num].rgmii_tx_val = tx_delay;
3263 }
3264
ksz_switch_register(struct ksz_device * dev)3265 int ksz_switch_register(struct ksz_device *dev)
3266 {
3267 const struct ksz_chip_data *info;
3268 struct device_node *port, *ports;
3269 phy_interface_t interface;
3270 unsigned int port_num;
3271 int ret;
3272 int i;
3273
3274 if (dev->pdata)
3275 dev->chip_id = dev->pdata->chip_id;
3276
3277 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset",
3278 GPIOD_OUT_LOW);
3279 if (IS_ERR(dev->reset_gpio))
3280 return PTR_ERR(dev->reset_gpio);
3281
3282 if (dev->reset_gpio) {
3283 gpiod_set_value_cansleep(dev->reset_gpio, 1);
3284 usleep_range(10000, 12000);
3285 gpiod_set_value_cansleep(dev->reset_gpio, 0);
3286 msleep(100);
3287 }
3288
3289 mutex_init(&dev->dev_mutex);
3290 mutex_init(&dev->regmap_mutex);
3291 mutex_init(&dev->alu_mutex);
3292 mutex_init(&dev->vlan_mutex);
3293
3294 ret = ksz_switch_detect(dev);
3295 if (ret)
3296 return ret;
3297
3298 info = ksz_lookup_info(dev->chip_id);
3299 if (!info)
3300 return -ENODEV;
3301
3302 /* Update the compatible info with the probed one */
3303 dev->info = info;
3304
3305 dev_info(dev->dev, "found switch: %s, rev %i\n",
3306 dev->info->dev_name, dev->chip_rev);
3307
3308 ret = ksz_check_device_id(dev);
3309 if (ret)
3310 return ret;
3311
3312 dev->dev_ops = dev->info->ops;
3313
3314 ret = dev->dev_ops->init(dev);
3315 if (ret)
3316 return ret;
3317
3318 dev->ports = devm_kzalloc(dev->dev,
3319 dev->info->port_cnt * sizeof(struct ksz_port),
3320 GFP_KERNEL);
3321 if (!dev->ports)
3322 return -ENOMEM;
3323
3324 for (i = 0; i < dev->info->port_cnt; i++) {
3325 spin_lock_init(&dev->ports[i].mib.stats64_lock);
3326 mutex_init(&dev->ports[i].mib.cnt_mutex);
3327 dev->ports[i].mib.counters =
3328 devm_kzalloc(dev->dev,
3329 sizeof(u64) * (dev->info->mib_cnt + 1),
3330 GFP_KERNEL);
3331 if (!dev->ports[i].mib.counters)
3332 return -ENOMEM;
3333
3334 dev->ports[i].ksz_dev = dev;
3335 dev->ports[i].num = i;
3336 }
3337
3338 /* set the real number of ports */
3339 dev->ds->num_ports = dev->info->port_cnt;
3340
3341 /* Host port interface will be self detected, or specifically set in
3342 * device tree.
3343 */
3344 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num)
3345 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA;
3346 if (dev->dev->of_node) {
3347 ret = of_get_phy_mode(dev->dev->of_node, &interface);
3348 if (ret == 0)
3349 dev->compat_interface = interface;
3350 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports");
3351 if (!ports)
3352 ports = of_get_child_by_name(dev->dev->of_node, "ports");
3353 if (ports) {
3354 for_each_available_child_of_node(ports, port) {
3355 if (of_property_read_u32(port, "reg",
3356 &port_num))
3357 continue;
3358 if (!(dev->port_mask & BIT(port_num))) {
3359 of_node_put(port);
3360 of_node_put(ports);
3361 return -EINVAL;
3362 }
3363 of_get_phy_mode(port,
3364 &dev->ports[port_num].interface);
3365
3366 ksz_parse_rgmii_delay(dev, port_num, port);
3367 }
3368 of_node_put(ports);
3369 }
3370 dev->synclko_125 = of_property_read_bool(dev->dev->of_node,
3371 "microchip,synclko-125");
3372 dev->synclko_disable = of_property_read_bool(dev->dev->of_node,
3373 "microchip,synclko-disable");
3374 if (dev->synclko_125 && dev->synclko_disable) {
3375 dev_err(dev->dev, "inconsistent synclko settings\n");
3376 return -EINVAL;
3377 }
3378 }
3379
3380 ret = dsa_register_switch(dev->ds);
3381 if (ret) {
3382 dev->dev_ops->exit(dev);
3383 return ret;
3384 }
3385
3386 /* Read MIB counters every 30 seconds to avoid overflow. */
3387 dev->mib_read_interval = msecs_to_jiffies(5000);
3388
3389 /* Start the MIB timer. */
3390 schedule_delayed_work(&dev->mib_read, 0);
3391
3392 return ret;
3393 }
3394 EXPORT_SYMBOL(ksz_switch_register);
3395
ksz_switch_remove(struct ksz_device * dev)3396 void ksz_switch_remove(struct ksz_device *dev)
3397 {
3398 /* timer started */
3399 if (dev->mib_read_interval) {
3400 dev->mib_read_interval = 0;
3401 cancel_delayed_work_sync(&dev->mib_read);
3402 }
3403
3404 dev->dev_ops->exit(dev);
3405 dsa_unregister_switch(dev->ds);
3406
3407 if (dev->reset_gpio)
3408 gpiod_set_value_cansleep(dev->reset_gpio, 1);
3409
3410 }
3411 EXPORT_SYMBOL(ksz_switch_remove);
3412
3413 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
3414 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver");
3415 MODULE_LICENSE("GPL");
3416