1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Ethernet driver
3 *
4 * Copyright (C) 2020 Marvell.
5 *
6 */
7
8 #ifndef OTX2_COMMON_H
9 #define OTX2_COMMON_H
10
11 #include <linux/ethtool.h>
12 #include <linux/pci.h>
13 #include <linux/iommu.h>
14 #include <linux/net_tstamp.h>
15 #include <linux/ptp_clock_kernel.h>
16 #include <linux/timecounter.h>
17 #include <linux/soc/marvell/octeontx2/asm.h>
18 #include <net/pkt_cls.h>
19 #include <net/devlink.h>
20 #include <linux/time64.h>
21 #include <linux/dim.h>
22 #include <uapi/linux/if_macsec.h>
23
24 #include <mbox.h>
25 #include <npc.h>
26 #include "otx2_reg.h"
27 #include "otx2_txrx.h"
28 #include "otx2_devlink.h"
29 #include <rvu_trace.h>
30
31 /* IPv4 flag more fragment bit */
32 #define IPV4_FLAG_MORE 0x20
33
34 /* PCI device IDs */
35 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063
36 #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064
37 #define PCI_DEVID_OCTEONTX2_RVU_AFVF 0xA0F8
38
39 #define PCI_SUBSYS_DEVID_96XX_RVU_PFVF 0xB200
40 #define PCI_SUBSYS_DEVID_CN10K_B_RVU_PFVF 0xBD00
41
42 /* PCI BAR nos */
43 #define PCI_CFG_REG_BAR_NUM 2
44 #define PCI_MBOX_BAR_NUM 4
45
46 #define NAME_SIZE 32
47
48 #ifdef CONFIG_DCB
49 /* Max priority supported for PFC */
50 #define NIX_PF_PFC_PRIO_MAX 8
51 #endif
52
53 enum arua_mapped_qtypes {
54 AURA_NIX_RQ,
55 AURA_NIX_SQ,
56 };
57
58 /* NIX LF interrupts range*/
59 #define NIX_LF_QINT_VEC_START 0x00
60 #define NIX_LF_CINT_VEC_START 0x40
61 #define NIX_LF_GINT_VEC 0x80
62 #define NIX_LF_ERR_VEC 0x81
63 #define NIX_LF_POISON_VEC 0x82
64
65 /* Send skid of 2000 packets required for CQ size of 4K CQEs. */
66 #define SEND_CQ_SKID 2000
67
68 #define OTX2_GET_RX_STATS(reg) \
69 otx2_read64(pfvf, NIX_LF_RX_STATX(reg))
70 #define OTX2_GET_TX_STATS(reg) \
71 otx2_read64(pfvf, NIX_LF_TX_STATX(reg))
72
73 struct otx2_lmt_info {
74 u64 lmt_addr;
75 u16 lmt_id;
76 };
77 /* RSS configuration */
78 struct otx2_rss_ctx {
79 u8 ind_tbl[MAX_RSS_INDIR_TBL_SIZE];
80 };
81
82 struct otx2_rss_info {
83 u8 enable;
84 u32 flowkey_cfg;
85 u16 rss_size;
86 #define RSS_HASH_KEY_SIZE 44 /* 352 bit key */
87 u8 key[RSS_HASH_KEY_SIZE];
88 struct otx2_rss_ctx *rss_ctx[MAX_RSS_GROUPS];
89 };
90
91 /* NIX (or NPC) RX errors */
92 enum otx2_errlvl {
93 NPC_ERRLVL_RE,
94 NPC_ERRLVL_LID_LA,
95 NPC_ERRLVL_LID_LB,
96 NPC_ERRLVL_LID_LC,
97 NPC_ERRLVL_LID_LD,
98 NPC_ERRLVL_LID_LE,
99 NPC_ERRLVL_LID_LF,
100 NPC_ERRLVL_LID_LG,
101 NPC_ERRLVL_LID_LH,
102 NPC_ERRLVL_NIX = 0x0F,
103 };
104
105 enum otx2_errcodes_re {
106 /* NPC_ERRLVL_RE errcodes */
107 ERRCODE_FCS = 0x7,
108 ERRCODE_FCS_RCV = 0x8,
109 ERRCODE_UNDERSIZE = 0x10,
110 ERRCODE_OVERSIZE = 0x11,
111 ERRCODE_OL2_LEN_MISMATCH = 0x12,
112 /* NPC_ERRLVL_NIX errcodes */
113 ERRCODE_OL3_LEN = 0x10,
114 ERRCODE_OL4_LEN = 0x11,
115 ERRCODE_OL4_CSUM = 0x12,
116 ERRCODE_IL3_LEN = 0x20,
117 ERRCODE_IL4_LEN = 0x21,
118 ERRCODE_IL4_CSUM = 0x22,
119 };
120
121 /* NIX TX stats */
122 enum nix_stat_lf_tx {
123 TX_UCAST = 0x0,
124 TX_BCAST = 0x1,
125 TX_MCAST = 0x2,
126 TX_DROP = 0x3,
127 TX_OCTS = 0x4,
128 TX_STATS_ENUM_LAST,
129 };
130
131 /* NIX RX stats */
132 enum nix_stat_lf_rx {
133 RX_OCTS = 0x0,
134 RX_UCAST = 0x1,
135 RX_BCAST = 0x2,
136 RX_MCAST = 0x3,
137 RX_DROP = 0x4,
138 RX_DROP_OCTS = 0x5,
139 RX_FCS = 0x6,
140 RX_ERR = 0x7,
141 RX_DRP_BCAST = 0x8,
142 RX_DRP_MCAST = 0x9,
143 RX_DRP_L3BCAST = 0xa,
144 RX_DRP_L3MCAST = 0xb,
145 RX_STATS_ENUM_LAST,
146 };
147
148 struct otx2_dev_stats {
149 u64 rx_bytes;
150 u64 rx_frames;
151 u64 rx_ucast_frames;
152 u64 rx_bcast_frames;
153 u64 rx_mcast_frames;
154 u64 rx_drops;
155
156 u64 tx_bytes;
157 u64 tx_frames;
158 u64 tx_ucast_frames;
159 u64 tx_bcast_frames;
160 u64 tx_mcast_frames;
161 u64 tx_drops;
162 };
163
164 /* Driver counted stats */
165 struct otx2_drv_stats {
166 atomic_t rx_fcs_errs;
167 atomic_t rx_oversize_errs;
168 atomic_t rx_undersize_errs;
169 atomic_t rx_csum_errs;
170 atomic_t rx_len_errs;
171 atomic_t rx_other_errs;
172 };
173
174 struct mbox {
175 struct otx2_mbox mbox;
176 struct work_struct mbox_wrk;
177 struct otx2_mbox mbox_up;
178 struct work_struct mbox_up_wrk;
179 struct otx2_nic *pfvf;
180 void *bbuf_base; /* Bounce buffer for mbox memory */
181 struct mutex lock; /* serialize mailbox access */
182 int num_msgs; /* mbox number of messages */
183 int up_num_msgs; /* mbox_up number of messages */
184 };
185
186 struct otx2_hw {
187 struct pci_dev *pdev;
188 struct otx2_rss_info rss_info;
189 u16 rx_queues;
190 u16 tx_queues;
191 u16 xdp_queues;
192 u16 tot_tx_queues;
193 u16 max_queues;
194 u16 pool_cnt;
195 u16 rqpool_cnt;
196 u16 sqpool_cnt;
197
198 #define OTX2_DEFAULT_RBUF_LEN 2048
199 u16 rbuf_len;
200 u32 xqe_size;
201
202 /* NPA */
203 u32 stack_pg_ptrs; /* No of ptrs per stack page */
204 u32 stack_pg_bytes; /* Size of stack page */
205 u16 sqb_size;
206
207 /* NIX */
208 u8 txschq_link_cfg_lvl;
209 u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
210 u16 matchall_ipolicer;
211 u32 dwrr_mtu;
212
213 /* HW settings, coalescing etc */
214 u16 rx_chan_base;
215 u16 tx_chan_base;
216 u16 cq_qcount_wait;
217 u16 cq_ecount_wait;
218 u16 rq_skid;
219 u8 cq_time_wait;
220
221 /* Segmentation */
222 u8 lso_tsov4_idx;
223 u8 lso_tsov6_idx;
224 u8 lso_udpv4_idx;
225 u8 lso_udpv6_idx;
226
227 /* RSS */
228 u8 flowkey_alg_idx;
229
230 /* MSI-X */
231 u8 cint_cnt; /* CQ interrupt count */
232 u16 npa_msixoff; /* Offset of NPA vectors */
233 u16 nix_msixoff; /* Offset of NIX vectors */
234 char *irq_name;
235 cpumask_var_t *affinity_mask;
236
237 /* Stats */
238 struct otx2_dev_stats dev_stats;
239 struct otx2_drv_stats drv_stats;
240 u64 cgx_rx_stats[CGX_RX_STATS_COUNT];
241 u64 cgx_tx_stats[CGX_TX_STATS_COUNT];
242 u64 cgx_fec_corr_blks;
243 u64 cgx_fec_uncorr_blks;
244 u8 cgx_links; /* No. of CGX links present in HW */
245 u8 lbk_links; /* No. of LBK links present in HW */
246 u8 tx_link; /* Transmit channel link number */
247 #define HW_TSO 0
248 #define CN10K_MBOX 1
249 #define CN10K_LMTST 2
250 #define CN10K_RPM 3
251 #define CN10K_PTP_ONESTEP 4
252 #define CN10K_HW_MACSEC 5
253 unsigned long cap_flag;
254
255 #define LMT_LINE_SIZE 128
256 #define LMT_BURST_SIZE 32 /* 32 LMTST lines for burst SQE flush */
257 u64 *lmt_base;
258 struct otx2_lmt_info __percpu *lmt_info;
259 };
260
261 enum vfperm {
262 OTX2_RESET_VF_PERM,
263 OTX2_TRUSTED_VF,
264 };
265
266 struct otx2_vf_config {
267 struct otx2_nic *pf;
268 struct delayed_work link_event_work;
269 bool intf_down; /* interface was either configured or not */
270 u8 mac[ETH_ALEN];
271 u16 vlan;
272 int tx_vtag_idx;
273 bool trusted;
274 };
275
276 struct flr_work {
277 struct work_struct work;
278 struct otx2_nic *pf;
279 };
280
281 struct refill_work {
282 struct delayed_work pool_refill_work;
283 struct otx2_nic *pf;
284 };
285
286 /* PTPv2 originTimestamp structure */
287 struct ptpv2_tstamp {
288 __be16 seconds_msb; /* 16 bits + */
289 __be32 seconds_lsb; /* 32 bits = 48 bits*/
290 __be32 nanoseconds;
291 } __packed;
292
293 struct otx2_ptp {
294 struct ptp_clock_info ptp_info;
295 struct ptp_clock *ptp_clock;
296 struct otx2_nic *nic;
297
298 struct cyclecounter cycle_counter;
299 struct timecounter time_counter;
300
301 struct delayed_work extts_work;
302 u64 last_extts;
303 u64 thresh;
304
305 struct ptp_pin_desc extts_config;
306 u64 (*convert_rx_ptp_tstmp)(u64 timestamp);
307 u64 (*convert_tx_ptp_tstmp)(u64 timestamp);
308 struct delayed_work synctstamp_work;
309 u64 tstamp;
310 u32 base_ns;
311 };
312
313 #define OTX2_HW_TIMESTAMP_LEN 8
314
315 struct otx2_mac_table {
316 u8 addr[ETH_ALEN];
317 u16 mcam_entry;
318 bool inuse;
319 };
320
321 struct otx2_flow_config {
322 u16 *flow_ent;
323 u16 *def_ent;
324 u16 nr_flows;
325 #define OTX2_DEFAULT_FLOWCOUNT 16
326 #define OTX2_MAX_UNICAST_FLOWS 8
327 #define OTX2_MAX_VLAN_FLOWS 1
328 #define OTX2_MAX_TC_FLOWS OTX2_DEFAULT_FLOWCOUNT
329 #define OTX2_MCAM_COUNT (OTX2_DEFAULT_FLOWCOUNT + \
330 OTX2_MAX_UNICAST_FLOWS + \
331 OTX2_MAX_VLAN_FLOWS)
332 u16 unicast_offset;
333 u16 rx_vlan_offset;
334 u16 vf_vlan_offset;
335 #define OTX2_PER_VF_VLAN_FLOWS 2 /* Rx + Tx per VF */
336 #define OTX2_VF_VLAN_RX_INDEX 0
337 #define OTX2_VF_VLAN_TX_INDEX 1
338 u16 max_flows;
339 u8 dmacflt_max_flows;
340 u32 *bmap_to_dmacindex;
341 unsigned long *dmacflt_bmap;
342 struct list_head flow_list;
343 };
344
345 struct otx2_tc_info {
346 /* hash table to store TC offloaded flows */
347 struct rhashtable flow_table;
348 struct rhashtable_params flow_ht_params;
349 unsigned long *tc_entries_bitmap;
350 };
351
352 struct dev_hw_ops {
353 int (*sq_aq_init)(void *dev, u16 qidx, u16 sqb_aura);
354 void (*sqe_flush)(void *dev, struct otx2_snd_queue *sq,
355 int size, int qidx);
356 void (*refill_pool_ptrs)(void *dev, struct otx2_cq_queue *cq);
357 void (*aura_freeptr)(void *dev, int aura, u64 buf);
358 };
359
360 #define CN10K_MCS_SA_PER_SC 4
361
362 /* Stats which need to be accumulated in software because
363 * of shared counters in hardware.
364 */
365 struct cn10k_txsc_stats {
366 u64 InPktsUntagged;
367 u64 InPktsNoTag;
368 u64 InPktsBadTag;
369 u64 InPktsUnknownSCI;
370 u64 InPktsNoSCI;
371 u64 InPktsOverrun;
372 };
373
374 struct cn10k_rxsc_stats {
375 u64 InOctetsValidated;
376 u64 InOctetsDecrypted;
377 u64 InPktsUnchecked;
378 u64 InPktsDelayed;
379 u64 InPktsOK;
380 u64 InPktsInvalid;
381 u64 InPktsLate;
382 u64 InPktsNotValid;
383 u64 InPktsNotUsingSA;
384 u64 InPktsUnusedSA;
385 };
386
387 struct cn10k_mcs_txsc {
388 struct macsec_secy *sw_secy;
389 struct cn10k_txsc_stats stats;
390 struct list_head entry;
391 enum macsec_validation_type last_validate_frames;
392 bool last_protect_frames;
393 u16 hw_secy_id_tx;
394 u16 hw_secy_id_rx;
395 u16 hw_flow_id;
396 u16 hw_sc_id;
397 u16 hw_sa_id[CN10K_MCS_SA_PER_SC];
398 u8 sa_bmap;
399 u8 sa_key[CN10K_MCS_SA_PER_SC][MACSEC_MAX_KEY_LEN];
400 u8 encoding_sa;
401 };
402
403 struct cn10k_mcs_rxsc {
404 struct macsec_secy *sw_secy;
405 struct macsec_rx_sc *sw_rxsc;
406 struct cn10k_rxsc_stats stats;
407 struct list_head entry;
408 u16 hw_flow_id;
409 u16 hw_sc_id;
410 u16 hw_sa_id[CN10K_MCS_SA_PER_SC];
411 u8 sa_bmap;
412 u8 sa_key[CN10K_MCS_SA_PER_SC][MACSEC_MAX_KEY_LEN];
413 };
414
415 struct cn10k_mcs_cfg {
416 struct list_head txsc_list;
417 struct list_head rxsc_list;
418 };
419
420 struct otx2_nic {
421 void __iomem *reg_base;
422 struct net_device *netdev;
423 struct dev_hw_ops *hw_ops;
424 void *iommu_domain;
425 u16 tx_max_pktlen;
426 u16 rbsize; /* Receive buffer size */
427
428 #define OTX2_FLAG_RX_TSTAMP_ENABLED BIT_ULL(0)
429 #define OTX2_FLAG_TX_TSTAMP_ENABLED BIT_ULL(1)
430 #define OTX2_FLAG_INTF_DOWN BIT_ULL(2)
431 #define OTX2_FLAG_MCAM_ENTRIES_ALLOC BIT_ULL(3)
432 #define OTX2_FLAG_NTUPLE_SUPPORT BIT_ULL(4)
433 #define OTX2_FLAG_UCAST_FLTR_SUPPORT BIT_ULL(5)
434 #define OTX2_FLAG_RX_VLAN_SUPPORT BIT_ULL(6)
435 #define OTX2_FLAG_VF_VLAN_SUPPORT BIT_ULL(7)
436 #define OTX2_FLAG_PF_SHUTDOWN BIT_ULL(8)
437 #define OTX2_FLAG_RX_PAUSE_ENABLED BIT_ULL(9)
438 #define OTX2_FLAG_TX_PAUSE_ENABLED BIT_ULL(10)
439 #define OTX2_FLAG_TC_FLOWER_SUPPORT BIT_ULL(11)
440 #define OTX2_FLAG_TC_MATCHALL_EGRESS_ENABLED BIT_ULL(12)
441 #define OTX2_FLAG_TC_MATCHALL_INGRESS_ENABLED BIT_ULL(13)
442 #define OTX2_FLAG_DMACFLTR_SUPPORT BIT_ULL(14)
443 #define OTX2_FLAG_PTP_ONESTEP_SYNC BIT_ULL(15)
444 #define OTX2_FLAG_ADPTV_INT_COAL_ENABLED BIT_ULL(16)
445 u64 flags;
446 u64 *cq_op_addr;
447
448 struct bpf_prog *xdp_prog;
449 struct otx2_qset qset;
450 struct otx2_hw hw;
451 struct pci_dev *pdev;
452 struct device *dev;
453
454 /* Mbox */
455 struct mbox mbox;
456 struct mbox *mbox_pfvf;
457 struct workqueue_struct *mbox_wq;
458 struct workqueue_struct *mbox_pfvf_wq;
459
460 u8 total_vfs;
461 u16 pcifunc; /* RVU PF_FUNC */
462 u16 bpid[NIX_MAX_BPID_CHAN];
463 struct otx2_vf_config *vf_configs;
464 struct cgx_link_user_info linfo;
465
466 /* NPC MCAM */
467 struct otx2_flow_config *flow_cfg;
468 struct otx2_mac_table *mac_table;
469 struct otx2_tc_info tc_info;
470
471 u64 reset_count;
472 struct work_struct reset_task;
473 struct workqueue_struct *flr_wq;
474 struct flr_work *flr_wrk;
475 struct refill_work *refill_wrk;
476 struct workqueue_struct *otx2_wq;
477 struct work_struct rx_mode_work;
478
479 /* Ethtool stuff */
480 u32 msg_enable;
481
482 /* Block address of NIX either BLKADDR_NIX0 or BLKADDR_NIX1 */
483 int nix_blkaddr;
484 /* LMTST Lines info */
485 struct qmem *dync_lmt;
486 u16 tot_lmt_lines;
487 u16 npa_lmt_lines;
488 u32 nix_lmt_size;
489
490 struct otx2_ptp *ptp;
491 struct hwtstamp_config tstamp;
492
493 unsigned long rq_bmap;
494
495 /* Devlink */
496 struct otx2_devlink *dl;
497 #ifdef CONFIG_DCB
498 /* PFC */
499 u8 pfc_en;
500 u8 *queue_to_pfc_map;
501 u16 pfc_schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
502 bool pfc_alloc_status[NIX_PF_PFC_PRIO_MAX];
503 #endif
504
505 /* napi event count. It is needed for adaptive irq coalescing. */
506 u32 napi_events;
507
508 #if IS_ENABLED(CONFIG_MACSEC)
509 struct cn10k_mcs_cfg *macsec_cfg;
510 #endif
511 };
512
is_otx2_lbkvf(struct pci_dev * pdev)513 static inline bool is_otx2_lbkvf(struct pci_dev *pdev)
514 {
515 return pdev->device == PCI_DEVID_OCTEONTX2_RVU_AFVF;
516 }
517
is_96xx_A0(struct pci_dev * pdev)518 static inline bool is_96xx_A0(struct pci_dev *pdev)
519 {
520 return (pdev->revision == 0x00) &&
521 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF);
522 }
523
is_96xx_B0(struct pci_dev * pdev)524 static inline bool is_96xx_B0(struct pci_dev *pdev)
525 {
526 return (pdev->revision == 0x01) &&
527 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF);
528 }
529
530 /* REVID for PCIe devices.
531 * Bits 0..1: minor pass, bit 3..2: major pass
532 * bits 7..4: midr id
533 */
534 #define PCI_REVISION_ID_96XX 0x00
535 #define PCI_REVISION_ID_95XX 0x10
536 #define PCI_REVISION_ID_95XXN 0x20
537 #define PCI_REVISION_ID_98XX 0x30
538 #define PCI_REVISION_ID_95XXMM 0x40
539 #define PCI_REVISION_ID_95XXO 0xE0
540
is_dev_otx2(struct pci_dev * pdev)541 static inline bool is_dev_otx2(struct pci_dev *pdev)
542 {
543 u8 midr = pdev->revision & 0xF0;
544
545 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX ||
546 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX ||
547 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO);
548 }
549
is_dev_cn10kb(struct pci_dev * pdev)550 static inline bool is_dev_cn10kb(struct pci_dev *pdev)
551 {
552 return pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_B_RVU_PFVF;
553 }
554
otx2_setup_dev_hw_settings(struct otx2_nic * pfvf)555 static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf)
556 {
557 struct otx2_hw *hw = &pfvf->hw;
558
559 pfvf->hw.cq_time_wait = CQ_TIMER_THRESH_DEFAULT;
560 pfvf->hw.cq_ecount_wait = CQ_CQE_THRESH_DEFAULT;
561 pfvf->hw.cq_qcount_wait = CQ_QCOUNT_DEFAULT;
562
563 __set_bit(HW_TSO, &hw->cap_flag);
564
565 if (is_96xx_A0(pfvf->pdev)) {
566 __clear_bit(HW_TSO, &hw->cap_flag);
567
568 /* Time based irq coalescing is not supported */
569 pfvf->hw.cq_qcount_wait = 0x0;
570
571 /* Due to HW issue previous silicons required minimum
572 * 600 unused CQE to avoid CQ overflow.
573 */
574 pfvf->hw.rq_skid = 600;
575 pfvf->qset.rqe_cnt = Q_COUNT(Q_SIZE_1K);
576 }
577 if (is_96xx_B0(pfvf->pdev))
578 __clear_bit(HW_TSO, &hw->cap_flag);
579
580 if (!is_dev_otx2(pfvf->pdev)) {
581 __set_bit(CN10K_MBOX, &hw->cap_flag);
582 __set_bit(CN10K_LMTST, &hw->cap_flag);
583 __set_bit(CN10K_RPM, &hw->cap_flag);
584 __set_bit(CN10K_PTP_ONESTEP, &hw->cap_flag);
585 }
586
587 if (is_dev_cn10kb(pfvf->pdev))
588 __set_bit(CN10K_HW_MACSEC, &hw->cap_flag);
589 }
590
591 /* Register read/write APIs */
otx2_get_regaddr(struct otx2_nic * nic,u64 offset)592 static inline void __iomem *otx2_get_regaddr(struct otx2_nic *nic, u64 offset)
593 {
594 u64 blkaddr;
595
596 switch ((offset >> RVU_FUNC_BLKADDR_SHIFT) & RVU_FUNC_BLKADDR_MASK) {
597 case BLKTYPE_NIX:
598 blkaddr = nic->nix_blkaddr;
599 break;
600 case BLKTYPE_NPA:
601 blkaddr = BLKADDR_NPA;
602 break;
603 default:
604 blkaddr = BLKADDR_RVUM;
605 break;
606 }
607
608 offset &= ~(RVU_FUNC_BLKADDR_MASK << RVU_FUNC_BLKADDR_SHIFT);
609 offset |= (blkaddr << RVU_FUNC_BLKADDR_SHIFT);
610
611 return nic->reg_base + offset;
612 }
613
otx2_write64(struct otx2_nic * nic,u64 offset,u64 val)614 static inline void otx2_write64(struct otx2_nic *nic, u64 offset, u64 val)
615 {
616 void __iomem *addr = otx2_get_regaddr(nic, offset);
617
618 writeq(val, addr);
619 }
620
otx2_read64(struct otx2_nic * nic,u64 offset)621 static inline u64 otx2_read64(struct otx2_nic *nic, u64 offset)
622 {
623 void __iomem *addr = otx2_get_regaddr(nic, offset);
624
625 return readq(addr);
626 }
627
628 /* Mbox bounce buffer APIs */
otx2_mbox_bbuf_init(struct mbox * mbox,struct pci_dev * pdev)629 static inline int otx2_mbox_bbuf_init(struct mbox *mbox, struct pci_dev *pdev)
630 {
631 struct otx2_mbox *otx2_mbox;
632 struct otx2_mbox_dev *mdev;
633
634 mbox->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL);
635 if (!mbox->bbuf_base)
636 return -ENOMEM;
637
638 /* Overwrite mbox mbase to point to bounce buffer, so that PF/VF
639 * prepare all mbox messages in bounce buffer instead of directly
640 * in hw mbox memory.
641 */
642 otx2_mbox = &mbox->mbox;
643 mdev = &otx2_mbox->dev[0];
644 mdev->mbase = mbox->bbuf_base;
645
646 otx2_mbox = &mbox->mbox_up;
647 mdev = &otx2_mbox->dev[0];
648 mdev->mbase = mbox->bbuf_base;
649 return 0;
650 }
651
otx2_sync_mbox_bbuf(struct otx2_mbox * mbox,int devid)652 static inline void otx2_sync_mbox_bbuf(struct otx2_mbox *mbox, int devid)
653 {
654 u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
655 void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE);
656 struct otx2_mbox_dev *mdev = &mbox->dev[devid];
657 struct mbox_hdr *hdr;
658 u64 msg_size;
659
660 if (mdev->mbase == hw_mbase)
661 return;
662
663 hdr = hw_mbase + mbox->rx_start;
664 msg_size = hdr->msg_size;
665
666 if (msg_size > mbox->rx_size - msgs_offset)
667 msg_size = mbox->rx_size - msgs_offset;
668
669 /* Copy mbox messages from mbox memory to bounce buffer */
670 memcpy(mdev->mbase + mbox->rx_start,
671 hw_mbase + mbox->rx_start, msg_size + msgs_offset);
672 }
673
674 /* With the absence of API for 128-bit IO memory access for arm64,
675 * implement required operations at place.
676 */
677 #if defined(CONFIG_ARM64)
otx2_write128(u64 lo,u64 hi,void __iomem * addr)678 static inline void otx2_write128(u64 lo, u64 hi, void __iomem *addr)
679 {
680 __asm__ volatile("stp %x[x0], %x[x1], [%x[p1],#0]!"
681 ::[x0]"r"(lo), [x1]"r"(hi), [p1]"r"(addr));
682 }
683
otx2_atomic64_add(u64 incr,u64 * ptr)684 static inline u64 otx2_atomic64_add(u64 incr, u64 *ptr)
685 {
686 u64 result;
687
688 __asm__ volatile(".cpu generic+lse\n"
689 "ldadd %x[i], %x[r], [%[b]]"
690 : [r]"=r"(result), "+m"(*ptr)
691 : [i]"r"(incr), [b]"r"(ptr)
692 : "memory");
693 return result;
694 }
695
696 #else
697 #define otx2_write128(lo, hi, addr) writeq((hi) | (lo), addr)
698 #define otx2_atomic64_add(incr, ptr) ({ *ptr += incr; })
699 #endif
700
__cn10k_aura_freeptr(struct otx2_nic * pfvf,u64 aura,u64 * ptrs,u64 num_ptrs)701 static inline void __cn10k_aura_freeptr(struct otx2_nic *pfvf, u64 aura,
702 u64 *ptrs, u64 num_ptrs)
703 {
704 struct otx2_lmt_info *lmt_info;
705 u64 size = 0, count_eot = 0;
706 u64 tar_addr, val = 0;
707
708 lmt_info = per_cpu_ptr(pfvf->hw.lmt_info, smp_processor_id());
709 tar_addr = (__force u64)otx2_get_regaddr(pfvf, NPA_LF_AURA_BATCH_FREE0);
710 /* LMTID is same as AURA Id */
711 val = (lmt_info->lmt_id & 0x7FF) | BIT_ULL(63);
712 /* Set if [127:64] of last 128bit word has a valid pointer */
713 count_eot = (num_ptrs % 2) ? 0ULL : 1ULL;
714 /* Set AURA ID to free pointer */
715 ptrs[0] = (count_eot << 32) | (aura & 0xFFFFF);
716 /* Target address for LMTST flush tells HW how many 128bit
717 * words are valid from NPA_LF_AURA_BATCH_FREE0.
718 *
719 * tar_addr[6:4] is LMTST size-1 in units of 128b.
720 */
721 if (num_ptrs > 2) {
722 size = (sizeof(u64) * num_ptrs) / 16;
723 if (!count_eot)
724 size++;
725 tar_addr |= ((size - 1) & 0x7) << 4;
726 }
727 dma_wmb();
728 memcpy((u64 *)lmt_info->lmt_addr, ptrs, sizeof(u64) * num_ptrs);
729 /* Perform LMTST flush */
730 cn10k_lmt_flush(val, tar_addr);
731 }
732
cn10k_aura_freeptr(void * dev,int aura,u64 buf)733 static inline void cn10k_aura_freeptr(void *dev, int aura, u64 buf)
734 {
735 struct otx2_nic *pfvf = dev;
736 u64 ptrs[2];
737
738 ptrs[1] = buf;
739 get_cpu();
740 /* Free only one buffer at time during init and teardown */
741 __cn10k_aura_freeptr(pfvf, aura, ptrs, 2);
742 put_cpu();
743 }
744
745 /* Alloc pointer from pool/aura */
otx2_aura_allocptr(struct otx2_nic * pfvf,int aura)746 static inline u64 otx2_aura_allocptr(struct otx2_nic *pfvf, int aura)
747 {
748 u64 *ptr = (u64 *)otx2_get_regaddr(pfvf,
749 NPA_LF_AURA_OP_ALLOCX(0));
750 u64 incr = (u64)aura | BIT_ULL(63);
751
752 return otx2_atomic64_add(incr, ptr);
753 }
754
755 /* Free pointer to a pool/aura */
otx2_aura_freeptr(void * dev,int aura,u64 buf)756 static inline void otx2_aura_freeptr(void *dev, int aura, u64 buf)
757 {
758 struct otx2_nic *pfvf = dev;
759 void __iomem *addr = otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_FREE0);
760
761 otx2_write128(buf, (u64)aura | BIT_ULL(63), addr);
762 }
763
otx2_get_pool_idx(struct otx2_nic * pfvf,int type,int idx)764 static inline int otx2_get_pool_idx(struct otx2_nic *pfvf, int type, int idx)
765 {
766 if (type == AURA_NIX_SQ)
767 return pfvf->hw.rqpool_cnt + idx;
768
769 /* AURA_NIX_RQ */
770 return idx;
771 }
772
773 /* Mbox APIs */
otx2_sync_mbox_msg(struct mbox * mbox)774 static inline int otx2_sync_mbox_msg(struct mbox *mbox)
775 {
776 int err;
777
778 if (!otx2_mbox_nonempty(&mbox->mbox, 0))
779 return 0;
780 otx2_mbox_msg_send(&mbox->mbox, 0);
781 err = otx2_mbox_wait_for_rsp(&mbox->mbox, 0);
782 if (err)
783 return err;
784
785 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0);
786 }
787
otx2_sync_mbox_up_msg(struct mbox * mbox,int devid)788 static inline int otx2_sync_mbox_up_msg(struct mbox *mbox, int devid)
789 {
790 int err;
791
792 if (!otx2_mbox_nonempty(&mbox->mbox_up, devid))
793 return 0;
794 otx2_mbox_msg_send(&mbox->mbox_up, devid);
795 err = otx2_mbox_wait_for_rsp(&mbox->mbox_up, devid);
796 if (err)
797 return err;
798
799 return otx2_mbox_check_rsp_msgs(&mbox->mbox_up, devid);
800 }
801
802 /* Use this API to send mbox msgs in atomic context
803 * where sleeping is not allowed
804 */
otx2_sync_mbox_msg_busy_poll(struct mbox * mbox)805 static inline int otx2_sync_mbox_msg_busy_poll(struct mbox *mbox)
806 {
807 int err;
808
809 if (!otx2_mbox_nonempty(&mbox->mbox, 0))
810 return 0;
811 otx2_mbox_msg_send(&mbox->mbox, 0);
812 err = otx2_mbox_busy_poll_for_rsp(&mbox->mbox, 0);
813 if (err)
814 return err;
815
816 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0);
817 }
818
819 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
820 static struct _req_type __maybe_unused \
821 *otx2_mbox_alloc_msg_ ## _fn_name(struct mbox *mbox) \
822 { \
823 struct _req_type *req; \
824 \
825 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \
826 &mbox->mbox, 0, sizeof(struct _req_type), \
827 sizeof(struct _rsp_type)); \
828 if (!req) \
829 return NULL; \
830 req->hdr.sig = OTX2_MBOX_REQ_SIG; \
831 req->hdr.id = _id; \
832 trace_otx2_msg_alloc(mbox->mbox.pdev, _id, sizeof(*req)); \
833 return req; \
834 }
835
836 MBOX_MESSAGES
837 #undef M
838
839 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
840 int \
841 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \
842 struct _req_type *req, \
843 struct _rsp_type *rsp); \
844
845 MBOX_UP_CGX_MESSAGES
846 MBOX_UP_MCS_MESSAGES
847 #undef M
848
849 /* Time to wait before watchdog kicks off */
850 #define OTX2_TX_TIMEOUT (100 * HZ)
851
852 #define RVU_PFVF_PF_SHIFT 10
853 #define RVU_PFVF_PF_MASK 0x3F
854 #define RVU_PFVF_FUNC_SHIFT 0
855 #define RVU_PFVF_FUNC_MASK 0x3FF
856
is_otx2_vf(u16 pcifunc)857 static inline bool is_otx2_vf(u16 pcifunc)
858 {
859 return !!(pcifunc & RVU_PFVF_FUNC_MASK);
860 }
861
rvu_get_pf(u16 pcifunc)862 static inline int rvu_get_pf(u16 pcifunc)
863 {
864 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK;
865 }
866
otx2_dma_map_page(struct otx2_nic * pfvf,struct page * page,size_t offset,size_t size,enum dma_data_direction dir)867 static inline dma_addr_t otx2_dma_map_page(struct otx2_nic *pfvf,
868 struct page *page,
869 size_t offset, size_t size,
870 enum dma_data_direction dir)
871 {
872 dma_addr_t iova;
873
874 iova = dma_map_page_attrs(pfvf->dev, page,
875 offset, size, dir, DMA_ATTR_SKIP_CPU_SYNC);
876 if (unlikely(dma_mapping_error(pfvf->dev, iova)))
877 return (dma_addr_t)NULL;
878 return iova;
879 }
880
otx2_dma_unmap_page(struct otx2_nic * pfvf,dma_addr_t addr,size_t size,enum dma_data_direction dir)881 static inline void otx2_dma_unmap_page(struct otx2_nic *pfvf,
882 dma_addr_t addr, size_t size,
883 enum dma_data_direction dir)
884 {
885 dma_unmap_page_attrs(pfvf->dev, addr, size,
886 dir, DMA_ATTR_SKIP_CPU_SYNC);
887 }
888
otx2_get_smq_idx(struct otx2_nic * pfvf,u16 qidx)889 static inline u16 otx2_get_smq_idx(struct otx2_nic *pfvf, u16 qidx)
890 {
891 #ifdef CONFIG_DCB
892 if (qidx < NIX_PF_PFC_PRIO_MAX && pfvf->pfc_alloc_status[qidx])
893 return pfvf->pfc_schq_list[NIX_TXSCH_LVL_SMQ][qidx];
894 #endif
895
896 return pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][0];
897 }
898
899 /* MSI-X APIs */
900 void otx2_free_cints(struct otx2_nic *pfvf, int n);
901 void otx2_set_cints_affinity(struct otx2_nic *pfvf);
902 int otx2_set_mac_address(struct net_device *netdev, void *p);
903 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu);
904 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq);
905 void otx2_get_mac_from_af(struct net_device *netdev);
906 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx);
907 int otx2_config_pause_frm(struct otx2_nic *pfvf);
908 void otx2_setup_segmentation(struct otx2_nic *pfvf);
909
910 /* RVU block related APIs */
911 int otx2_attach_npa_nix(struct otx2_nic *pfvf);
912 int otx2_detach_resources(struct mbox *mbox);
913 int otx2_config_npa(struct otx2_nic *pfvf);
914 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf);
915 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf);
916 void otx2_aura_pool_free(struct otx2_nic *pfvf);
917 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type);
918 void otx2_sq_free_sqbs(struct otx2_nic *pfvf);
919 int otx2_config_nix(struct otx2_nic *pfvf);
920 int otx2_config_nix_queues(struct otx2_nic *pfvf);
921 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool pfc_en);
922 int otx2_txsch_alloc(struct otx2_nic *pfvf);
923 int otx2_txschq_stop(struct otx2_nic *pfvf);
924 void otx2_sqb_flush(struct otx2_nic *pfvf);
925 int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool,
926 dma_addr_t *dma);
927 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable);
928 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa);
929 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable);
930 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq);
931 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq);
932 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura);
933 int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura);
934 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq,
935 dma_addr_t *dma);
936
937 /* RSS configuration APIs*/
938 int otx2_rss_init(struct otx2_nic *pfvf);
939 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf);
940 void otx2_set_rss_key(struct otx2_nic *pfvf);
941 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id);
942
943 /* Mbox handlers */
944 void mbox_handler_msix_offset(struct otx2_nic *pfvf,
945 struct msix_offset_rsp *rsp);
946 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf,
947 struct npa_lf_alloc_rsp *rsp);
948 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf,
949 struct nix_lf_alloc_rsp *rsp);
950 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf,
951 struct nix_txsch_alloc_rsp *rsp);
952 void mbox_handler_cgx_stats(struct otx2_nic *pfvf,
953 struct cgx_stats_rsp *rsp);
954 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf,
955 struct cgx_fec_stats_rsp *rsp);
956 void otx2_set_fec_stats_count(struct otx2_nic *pfvf);
957 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf,
958 struct nix_bp_cfg_rsp *rsp);
959
960 /* Device stats APIs */
961 void otx2_get_dev_stats(struct otx2_nic *pfvf);
962 void otx2_get_stats64(struct net_device *netdev,
963 struct rtnl_link_stats64 *stats);
964 void otx2_update_lmac_stats(struct otx2_nic *pfvf);
965 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf);
966 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx);
967 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx);
968 void otx2_set_ethtool_ops(struct net_device *netdev);
969 void otx2vf_set_ethtool_ops(struct net_device *netdev);
970
971 int otx2_open(struct net_device *netdev);
972 int otx2_stop(struct net_device *netdev);
973 int otx2_set_real_num_queues(struct net_device *netdev,
974 int tx_queues, int rx_queues);
975 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd);
976 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr);
977
978 /* MCAM filter related APIs */
979 int otx2_mcam_flow_init(struct otx2_nic *pf);
980 int otx2vf_mcam_flow_init(struct otx2_nic *pfvf);
981 int otx2_alloc_mcam_entries(struct otx2_nic *pfvf, u16 count);
982 void otx2_mcam_flow_del(struct otx2_nic *pf);
983 int otx2_destroy_ntuple_flows(struct otx2_nic *pf);
984 int otx2_destroy_mcam_flows(struct otx2_nic *pfvf);
985 int otx2_get_flow(struct otx2_nic *pfvf,
986 struct ethtool_rxnfc *nfc, u32 location);
987 int otx2_get_all_flows(struct otx2_nic *pfvf,
988 struct ethtool_rxnfc *nfc, u32 *rule_locs);
989 int otx2_add_flow(struct otx2_nic *pfvf,
990 struct ethtool_rxnfc *nfc);
991 int otx2_remove_flow(struct otx2_nic *pfvf, u32 location);
992 int otx2_get_maxflows(struct otx2_flow_config *flow_cfg);
993 void otx2_rss_ctx_flow_del(struct otx2_nic *pfvf, int ctx_id);
994 int otx2_del_macfilter(struct net_device *netdev, const u8 *mac);
995 int otx2_add_macfilter(struct net_device *netdev, const u8 *mac);
996 int otx2_enable_rxvlan(struct otx2_nic *pf, bool enable);
997 int otx2_install_rxvlan_offload_flow(struct otx2_nic *pfvf);
998 bool otx2_xdp_sq_append_pkt(struct otx2_nic *pfvf, u64 iova, int len, u16 qidx);
999 u16 otx2_get_max_mtu(struct otx2_nic *pfvf);
1000 int otx2_handle_ntuple_tc_features(struct net_device *netdev,
1001 netdev_features_t features);
1002 int otx2_smq_flush(struct otx2_nic *pfvf, int smq);
1003
1004 /* tc support */
1005 int otx2_init_tc(struct otx2_nic *nic);
1006 void otx2_shutdown_tc(struct otx2_nic *nic);
1007 int otx2_setup_tc(struct net_device *netdev, enum tc_setup_type type,
1008 void *type_data);
1009 int otx2_tc_alloc_ent_bitmap(struct otx2_nic *nic);
1010 /* CGX/RPM DMAC filters support */
1011 int otx2_dmacflt_get_max_cnt(struct otx2_nic *pf);
1012 int otx2_dmacflt_add(struct otx2_nic *pf, const u8 *mac, u32 bit_pos);
1013 int otx2_dmacflt_remove(struct otx2_nic *pf, const u8 *mac, u32 bit_pos);
1014 int otx2_dmacflt_update(struct otx2_nic *pf, u8 *mac, u32 bit_pos);
1015 void otx2_dmacflt_reinstall_flows(struct otx2_nic *pf);
1016 void otx2_dmacflt_update_pfmac_flow(struct otx2_nic *pfvf);
1017
1018 #ifdef CONFIG_DCB
1019 /* DCB support*/
1020 void otx2_update_bpid_in_rqctx(struct otx2_nic *pfvf, int vlan_prio, int qidx, bool pfc_enable);
1021 int otx2_config_priority_flow_ctrl(struct otx2_nic *pfvf);
1022 int otx2_dcbnl_set_ops(struct net_device *dev);
1023 /* PFC support */
1024 int otx2_pfc_txschq_config(struct otx2_nic *pfvf);
1025 int otx2_pfc_txschq_alloc(struct otx2_nic *pfvf);
1026 int otx2_pfc_txschq_update(struct otx2_nic *pfvf);
1027 int otx2_pfc_txschq_stop(struct otx2_nic *pfvf);
1028 #endif
1029
1030 #if IS_ENABLED(CONFIG_MACSEC)
1031 /* MACSEC offload support */
1032 int cn10k_mcs_init(struct otx2_nic *pfvf);
1033 void cn10k_mcs_free(struct otx2_nic *pfvf);
1034 void cn10k_handle_mcs_event(struct otx2_nic *pfvf, struct mcs_intr_info *event);
1035 #else
cn10k_mcs_init(struct otx2_nic * pfvf)1036 static inline int cn10k_mcs_init(struct otx2_nic *pfvf) { return 0; }
cn10k_mcs_free(struct otx2_nic * pfvf)1037 static inline void cn10k_mcs_free(struct otx2_nic *pfvf) {}
cn10k_handle_mcs_event(struct otx2_nic * pfvf,struct mcs_intr_info * event)1038 static inline void cn10k_handle_mcs_event(struct otx2_nic *pfvf,
1039 struct mcs_intr_info *event)
1040 {}
1041 #endif /* CONFIG_MACSEC */
1042
1043 #endif /* OTX2_COMMON_H */
1044