1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Ethernet driver
3 *
4 * Copyright (C) 2020 Marvell.
5 *
6 */
7
8 #include <linux/etherdevice.h>
9 #include <net/ip.h>
10 #include <net/tso.h>
11 #include <linux/bpf.h>
12 #include <linux/bpf_trace.h>
13 #include <net/ip6_checksum.h>
14
15 #include "otx2_reg.h"
16 #include "otx2_common.h"
17 #include "otx2_struct.h"
18 #include "otx2_txrx.h"
19 #include "otx2_ptp.h"
20 #include "cn10k.h"
21
22 #define CQE_ADDR(CQ, idx) ((CQ)->cqe_base + ((CQ)->cqe_size * (idx)))
23 #define PTP_PORT 0x13F
24 /* PTPv2 header Original Timestamp starts at byte offset 34 and
25 * contains 6 byte seconds field and 4 byte nano seconds field.
26 */
27 #define PTP_SYNC_SEC_OFFSET 34
28
29 static bool otx2_xdp_rcv_pkt_handler(struct otx2_nic *pfvf,
30 struct bpf_prog *prog,
31 struct nix_cqe_rx_s *cqe,
32 struct otx2_cq_queue *cq);
33
otx2_nix_cq_op_status(struct otx2_nic * pfvf,struct otx2_cq_queue * cq)34 static int otx2_nix_cq_op_status(struct otx2_nic *pfvf,
35 struct otx2_cq_queue *cq)
36 {
37 u64 incr = (u64)(cq->cq_idx) << 32;
38 u64 status;
39
40 status = otx2_atomic64_fetch_add(incr, pfvf->cq_op_addr);
41
42 if (unlikely(status & BIT_ULL(CQ_OP_STAT_OP_ERR) ||
43 status & BIT_ULL(CQ_OP_STAT_CQ_ERR))) {
44 dev_err(pfvf->dev, "CQ stopped due to error");
45 return -EINVAL;
46 }
47
48 cq->cq_tail = status & 0xFFFFF;
49 cq->cq_head = (status >> 20) & 0xFFFFF;
50 if (cq->cq_tail < cq->cq_head)
51 cq->pend_cqe = (cq->cqe_cnt - cq->cq_head) +
52 cq->cq_tail;
53 else
54 cq->pend_cqe = cq->cq_tail - cq->cq_head;
55
56 return 0;
57 }
58
otx2_get_next_cqe(struct otx2_cq_queue * cq)59 static struct nix_cqe_hdr_s *otx2_get_next_cqe(struct otx2_cq_queue *cq)
60 {
61 struct nix_cqe_hdr_s *cqe_hdr;
62
63 cqe_hdr = (struct nix_cqe_hdr_s *)CQE_ADDR(cq, cq->cq_head);
64 if (cqe_hdr->cqe_type == NIX_XQE_TYPE_INVALID)
65 return NULL;
66
67 cq->cq_head++;
68 cq->cq_head &= (cq->cqe_cnt - 1);
69
70 return cqe_hdr;
71 }
72
frag_num(unsigned int i)73 static unsigned int frag_num(unsigned int i)
74 {
75 #ifdef __BIG_ENDIAN
76 return (i & ~3) + 3 - (i & 3);
77 #else
78 return i;
79 #endif
80 }
81
otx2_dma_map_skb_frag(struct otx2_nic * pfvf,struct sk_buff * skb,int seg,int * len)82 static dma_addr_t otx2_dma_map_skb_frag(struct otx2_nic *pfvf,
83 struct sk_buff *skb, int seg, int *len)
84 {
85 const skb_frag_t *frag;
86 struct page *page;
87 int offset;
88
89 /* First segment is always skb->data */
90 if (!seg) {
91 page = virt_to_page(skb->data);
92 offset = offset_in_page(skb->data);
93 *len = skb_headlen(skb);
94 } else {
95 frag = &skb_shinfo(skb)->frags[seg - 1];
96 page = skb_frag_page(frag);
97 offset = skb_frag_off(frag);
98 *len = skb_frag_size(frag);
99 }
100 return otx2_dma_map_page(pfvf, page, offset, *len, DMA_TO_DEVICE);
101 }
102
otx2_dma_unmap_skb_frags(struct otx2_nic * pfvf,struct sg_list * sg)103 static void otx2_dma_unmap_skb_frags(struct otx2_nic *pfvf, struct sg_list *sg)
104 {
105 int seg;
106
107 for (seg = 0; seg < sg->num_segs; seg++) {
108 otx2_dma_unmap_page(pfvf, sg->dma_addr[seg],
109 sg->size[seg], DMA_TO_DEVICE);
110 }
111 sg->num_segs = 0;
112 }
113
otx2_xdp_snd_pkt_handler(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct nix_cqe_tx_s * cqe)114 static void otx2_xdp_snd_pkt_handler(struct otx2_nic *pfvf,
115 struct otx2_snd_queue *sq,
116 struct nix_cqe_tx_s *cqe)
117 {
118 struct nix_send_comp_s *snd_comp = &cqe->comp;
119 struct sg_list *sg;
120 struct page *page;
121 u64 pa;
122
123 sg = &sq->sg[snd_comp->sqe_id];
124
125 pa = otx2_iova_to_phys(pfvf->iommu_domain, sg->dma_addr[0]);
126 otx2_dma_unmap_page(pfvf, sg->dma_addr[0],
127 sg->size[0], DMA_TO_DEVICE);
128 page = virt_to_page(phys_to_virt(pa));
129 put_page(page);
130 }
131
otx2_snd_pkt_handler(struct otx2_nic * pfvf,struct otx2_cq_queue * cq,struct otx2_snd_queue * sq,struct nix_cqe_tx_s * cqe,int budget,int * tx_pkts,int * tx_bytes)132 static void otx2_snd_pkt_handler(struct otx2_nic *pfvf,
133 struct otx2_cq_queue *cq,
134 struct otx2_snd_queue *sq,
135 struct nix_cqe_tx_s *cqe,
136 int budget, int *tx_pkts, int *tx_bytes)
137 {
138 struct nix_send_comp_s *snd_comp = &cqe->comp;
139 struct skb_shared_hwtstamps ts;
140 struct sk_buff *skb = NULL;
141 u64 timestamp, tsns;
142 struct sg_list *sg;
143 int err;
144
145 if (unlikely(snd_comp->status) && netif_msg_tx_err(pfvf))
146 net_err_ratelimited("%s: TX%d: Error in send CQ status:%x\n",
147 pfvf->netdev->name, cq->cint_idx,
148 snd_comp->status);
149
150 sg = &sq->sg[snd_comp->sqe_id];
151 skb = (struct sk_buff *)sg->skb;
152 if (unlikely(!skb))
153 return;
154
155 if (skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) {
156 timestamp = ((u64 *)sq->timestamps->base)[snd_comp->sqe_id];
157 if (timestamp != 1) {
158 timestamp = pfvf->ptp->convert_tx_ptp_tstmp(timestamp);
159 err = otx2_ptp_tstamp2time(pfvf, timestamp, &tsns);
160 if (!err) {
161 memset(&ts, 0, sizeof(ts));
162 ts.hwtstamp = ns_to_ktime(tsns);
163 skb_tstamp_tx(skb, &ts);
164 }
165 }
166 }
167
168 *tx_bytes += skb->len;
169 (*tx_pkts)++;
170 otx2_dma_unmap_skb_frags(pfvf, sg);
171 napi_consume_skb(skb, budget);
172 sg->skb = (u64)NULL;
173 }
174
otx2_set_rxtstamp(struct otx2_nic * pfvf,struct sk_buff * skb,void * data)175 static void otx2_set_rxtstamp(struct otx2_nic *pfvf,
176 struct sk_buff *skb, void *data)
177 {
178 u64 timestamp, tsns;
179 int err;
180
181 if (!(pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED))
182 return;
183
184 timestamp = pfvf->ptp->convert_rx_ptp_tstmp(*(u64 *)data);
185 /* The first 8 bytes is the timestamp */
186 err = otx2_ptp_tstamp2time(pfvf, timestamp, &tsns);
187 if (err)
188 return;
189
190 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(tsns);
191 }
192
otx2_skb_add_frag(struct otx2_nic * pfvf,struct sk_buff * skb,u64 iova,int len,struct nix_rx_parse_s * parse,int qidx)193 static bool otx2_skb_add_frag(struct otx2_nic *pfvf, struct sk_buff *skb,
194 u64 iova, int len, struct nix_rx_parse_s *parse,
195 int qidx)
196 {
197 struct page *page;
198 int off = 0;
199 void *va;
200
201 va = phys_to_virt(otx2_iova_to_phys(pfvf->iommu_domain, iova));
202
203 if (likely(!skb_shinfo(skb)->nr_frags)) {
204 /* Check if data starts at some nonzero offset
205 * from the start of the buffer. For now the
206 * only possible offset is 8 bytes in the case
207 * where packet is prepended by a timestamp.
208 */
209 if (parse->laptr) {
210 otx2_set_rxtstamp(pfvf, skb, va);
211 off = OTX2_HW_TIMESTAMP_LEN;
212 }
213 }
214
215 page = virt_to_page(va);
216 if (likely(skb_shinfo(skb)->nr_frags < MAX_SKB_FRAGS)) {
217 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
218 va - page_address(page) + off,
219 len - off, pfvf->rbsize);
220
221 otx2_dma_unmap_page(pfvf, iova - OTX2_HEAD_ROOM,
222 pfvf->rbsize, DMA_FROM_DEVICE);
223 return true;
224 }
225
226 /* If more than MAX_SKB_FRAGS fragments are received then
227 * give back those buffer pointers to hardware for reuse.
228 */
229 pfvf->hw_ops->aura_freeptr(pfvf, qidx, iova & ~0x07ULL);
230
231 return false;
232 }
233
otx2_set_rxhash(struct otx2_nic * pfvf,struct nix_cqe_rx_s * cqe,struct sk_buff * skb)234 static void otx2_set_rxhash(struct otx2_nic *pfvf,
235 struct nix_cqe_rx_s *cqe, struct sk_buff *skb)
236 {
237 enum pkt_hash_types hash_type = PKT_HASH_TYPE_NONE;
238 struct otx2_rss_info *rss;
239 u32 hash = 0;
240
241 if (!(pfvf->netdev->features & NETIF_F_RXHASH))
242 return;
243
244 rss = &pfvf->hw.rss_info;
245 if (rss->flowkey_cfg) {
246 if (rss->flowkey_cfg &
247 ~(NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6))
248 hash_type = PKT_HASH_TYPE_L4;
249 else
250 hash_type = PKT_HASH_TYPE_L3;
251 hash = cqe->hdr.flow_tag;
252 }
253 skb_set_hash(skb, hash, hash_type);
254 }
255
otx2_free_rcv_seg(struct otx2_nic * pfvf,struct nix_cqe_rx_s * cqe,int qidx)256 static void otx2_free_rcv_seg(struct otx2_nic *pfvf, struct nix_cqe_rx_s *cqe,
257 int qidx)
258 {
259 struct nix_rx_sg_s *sg = &cqe->sg;
260 void *end, *start;
261 u64 *seg_addr;
262 int seg;
263
264 start = (void *)sg;
265 end = start + ((cqe->parse.desc_sizem1 + 1) * 16);
266 while (start < end) {
267 sg = (struct nix_rx_sg_s *)start;
268 seg_addr = &sg->seg_addr;
269 for (seg = 0; seg < sg->segs; seg++, seg_addr++)
270 pfvf->hw_ops->aura_freeptr(pfvf, qidx,
271 *seg_addr & ~0x07ULL);
272 start += sizeof(*sg);
273 }
274 }
275
otx2_check_rcv_errors(struct otx2_nic * pfvf,struct nix_cqe_rx_s * cqe,int qidx)276 static bool otx2_check_rcv_errors(struct otx2_nic *pfvf,
277 struct nix_cqe_rx_s *cqe, int qidx)
278 {
279 struct otx2_drv_stats *stats = &pfvf->hw.drv_stats;
280 struct nix_rx_parse_s *parse = &cqe->parse;
281
282 if (netif_msg_rx_err(pfvf))
283 netdev_err(pfvf->netdev,
284 "RQ%d: Error pkt with errlev:0x%x errcode:0x%x\n",
285 qidx, parse->errlev, parse->errcode);
286
287 if (parse->errlev == NPC_ERRLVL_RE) {
288 switch (parse->errcode) {
289 case ERRCODE_FCS:
290 case ERRCODE_FCS_RCV:
291 atomic_inc(&stats->rx_fcs_errs);
292 break;
293 case ERRCODE_UNDERSIZE:
294 atomic_inc(&stats->rx_undersize_errs);
295 break;
296 case ERRCODE_OVERSIZE:
297 atomic_inc(&stats->rx_oversize_errs);
298 break;
299 case ERRCODE_OL2_LEN_MISMATCH:
300 atomic_inc(&stats->rx_len_errs);
301 break;
302 default:
303 atomic_inc(&stats->rx_other_errs);
304 break;
305 }
306 } else if (parse->errlev == NPC_ERRLVL_NIX) {
307 switch (parse->errcode) {
308 case ERRCODE_OL3_LEN:
309 case ERRCODE_OL4_LEN:
310 case ERRCODE_IL3_LEN:
311 case ERRCODE_IL4_LEN:
312 atomic_inc(&stats->rx_len_errs);
313 break;
314 case ERRCODE_OL4_CSUM:
315 case ERRCODE_IL4_CSUM:
316 atomic_inc(&stats->rx_csum_errs);
317 break;
318 default:
319 atomic_inc(&stats->rx_other_errs);
320 break;
321 }
322 } else {
323 atomic_inc(&stats->rx_other_errs);
324 /* For now ignore all the NPC parser errors and
325 * pass the packets to stack.
326 */
327 return false;
328 }
329
330 /* If RXALL is enabled pass on packets to stack. */
331 if (pfvf->netdev->features & NETIF_F_RXALL)
332 return false;
333
334 /* Free buffer back to pool */
335 if (cqe->sg.segs)
336 otx2_free_rcv_seg(pfvf, cqe, qidx);
337 return true;
338 }
339
otx2_rcv_pkt_handler(struct otx2_nic * pfvf,struct napi_struct * napi,struct otx2_cq_queue * cq,struct nix_cqe_rx_s * cqe)340 static void otx2_rcv_pkt_handler(struct otx2_nic *pfvf,
341 struct napi_struct *napi,
342 struct otx2_cq_queue *cq,
343 struct nix_cqe_rx_s *cqe)
344 {
345 struct nix_rx_parse_s *parse = &cqe->parse;
346 struct nix_rx_sg_s *sg = &cqe->sg;
347 struct sk_buff *skb = NULL;
348 void *end, *start;
349 u64 *seg_addr;
350 u16 *seg_size;
351 int seg;
352
353 if (unlikely(parse->errlev || parse->errcode)) {
354 if (otx2_check_rcv_errors(pfvf, cqe, cq->cq_idx))
355 return;
356 }
357
358 if (pfvf->xdp_prog)
359 if (otx2_xdp_rcv_pkt_handler(pfvf, pfvf->xdp_prog, cqe, cq))
360 return;
361
362 skb = napi_get_frags(napi);
363 if (unlikely(!skb))
364 return;
365
366 start = (void *)sg;
367 end = start + ((cqe->parse.desc_sizem1 + 1) * 16);
368 while (start < end) {
369 sg = (struct nix_rx_sg_s *)start;
370 seg_addr = &sg->seg_addr;
371 seg_size = (void *)sg;
372 for (seg = 0; seg < sg->segs; seg++, seg_addr++) {
373 if (otx2_skb_add_frag(pfvf, skb, *seg_addr,
374 seg_size[seg], parse, cq->cq_idx))
375 cq->pool_ptrs++;
376 }
377 start += sizeof(*sg);
378 }
379 otx2_set_rxhash(pfvf, cqe, skb);
380
381 skb_record_rx_queue(skb, cq->cq_idx);
382 if (pfvf->netdev->features & NETIF_F_RXCSUM)
383 skb->ip_summed = CHECKSUM_UNNECESSARY;
384
385 napi_gro_frags(napi);
386 }
387
otx2_rx_napi_handler(struct otx2_nic * pfvf,struct napi_struct * napi,struct otx2_cq_queue * cq,int budget)388 static int otx2_rx_napi_handler(struct otx2_nic *pfvf,
389 struct napi_struct *napi,
390 struct otx2_cq_queue *cq, int budget)
391 {
392 struct nix_cqe_rx_s *cqe;
393 int processed_cqe = 0;
394
395 if (cq->pend_cqe >= budget)
396 goto process_cqe;
397
398 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe)
399 return 0;
400
401 process_cqe:
402 while (likely(processed_cqe < budget) && cq->pend_cqe) {
403 cqe = (struct nix_cqe_rx_s *)CQE_ADDR(cq, cq->cq_head);
404 if (cqe->hdr.cqe_type == NIX_XQE_TYPE_INVALID ||
405 !cqe->sg.seg_addr) {
406 if (!processed_cqe)
407 return 0;
408 break;
409 }
410 cq->cq_head++;
411 cq->cq_head &= (cq->cqe_cnt - 1);
412
413 otx2_rcv_pkt_handler(pfvf, napi, cq, cqe);
414
415 cqe->hdr.cqe_type = NIX_XQE_TYPE_INVALID;
416 cqe->sg.seg_addr = 0x00;
417 processed_cqe++;
418 cq->pend_cqe--;
419 }
420
421 /* Free CQEs to HW */
422 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR,
423 ((u64)cq->cq_idx << 32) | processed_cqe);
424
425 return processed_cqe;
426 }
427
otx2_refill_pool_ptrs(void * dev,struct otx2_cq_queue * cq)428 void otx2_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq)
429 {
430 struct otx2_nic *pfvf = dev;
431 dma_addr_t bufptr;
432
433 while (cq->pool_ptrs) {
434 if (otx2_alloc_buffer(pfvf, cq, &bufptr))
435 break;
436 otx2_aura_freeptr(pfvf, cq->cq_idx, bufptr + OTX2_HEAD_ROOM);
437 cq->pool_ptrs--;
438 }
439 }
440
otx2_tx_napi_handler(struct otx2_nic * pfvf,struct otx2_cq_queue * cq,int budget)441 static int otx2_tx_napi_handler(struct otx2_nic *pfvf,
442 struct otx2_cq_queue *cq, int budget)
443 {
444 int tx_pkts = 0, tx_bytes = 0, qidx;
445 struct otx2_snd_queue *sq;
446 struct nix_cqe_tx_s *cqe;
447 int processed_cqe = 0;
448
449 if (cq->pend_cqe >= budget)
450 goto process_cqe;
451
452 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe)
453 return 0;
454
455 process_cqe:
456 qidx = cq->cq_idx - pfvf->hw.rx_queues;
457 sq = &pfvf->qset.sq[qidx];
458
459 while (likely(processed_cqe < budget) && cq->pend_cqe) {
460 cqe = (struct nix_cqe_tx_s *)otx2_get_next_cqe(cq);
461 if (unlikely(!cqe)) {
462 if (!processed_cqe)
463 return 0;
464 break;
465 }
466
467 if (cq->cq_type == CQ_XDP) {
468 otx2_xdp_snd_pkt_handler(pfvf, sq, cqe);
469 } else {
470 otx2_snd_pkt_handler(pfvf, cq, sq, cqe, budget,
471 &tx_pkts, &tx_bytes);
472 }
473
474 cqe->hdr.cqe_type = NIX_XQE_TYPE_INVALID;
475 processed_cqe++;
476 cq->pend_cqe--;
477
478 sq->cons_head++;
479 sq->cons_head &= (sq->sqe_cnt - 1);
480 }
481
482 /* Free CQEs to HW */
483 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR,
484 ((u64)cq->cq_idx << 32) | processed_cqe);
485
486 if (likely(tx_pkts)) {
487 struct netdev_queue *txq;
488
489 txq = netdev_get_tx_queue(pfvf->netdev, cq->cint_idx);
490 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes);
491 /* Check if queue was stopped earlier due to ring full */
492 smp_mb();
493 if (netif_tx_queue_stopped(txq) &&
494 netif_carrier_ok(pfvf->netdev))
495 netif_tx_wake_queue(txq);
496 }
497 return 0;
498 }
499
otx2_adjust_adaptive_coalese(struct otx2_nic * pfvf,struct otx2_cq_poll * cq_poll)500 static void otx2_adjust_adaptive_coalese(struct otx2_nic *pfvf, struct otx2_cq_poll *cq_poll)
501 {
502 struct dim_sample dim_sample;
503 u64 rx_frames, rx_bytes;
504
505 rx_frames = OTX2_GET_RX_STATS(RX_BCAST) + OTX2_GET_RX_STATS(RX_MCAST) +
506 OTX2_GET_RX_STATS(RX_UCAST);
507 rx_bytes = OTX2_GET_RX_STATS(RX_OCTS);
508 dim_update_sample(pfvf->napi_events, rx_frames, rx_bytes, &dim_sample);
509 net_dim(&cq_poll->dim, dim_sample);
510 }
511
otx2_napi_handler(struct napi_struct * napi,int budget)512 int otx2_napi_handler(struct napi_struct *napi, int budget)
513 {
514 struct otx2_cq_queue *rx_cq = NULL;
515 struct otx2_cq_poll *cq_poll;
516 int workdone = 0, cq_idx, i;
517 struct otx2_cq_queue *cq;
518 struct otx2_qset *qset;
519 struct otx2_nic *pfvf;
520
521 cq_poll = container_of(napi, struct otx2_cq_poll, napi);
522 pfvf = (struct otx2_nic *)cq_poll->dev;
523 qset = &pfvf->qset;
524
525 for (i = 0; i < CQS_PER_CINT; i++) {
526 cq_idx = cq_poll->cq_ids[i];
527 if (unlikely(cq_idx == CINT_INVALID_CQ))
528 continue;
529 cq = &qset->cq[cq_idx];
530 if (cq->cq_type == CQ_RX) {
531 rx_cq = cq;
532 workdone += otx2_rx_napi_handler(pfvf, napi,
533 cq, budget);
534 } else {
535 workdone += otx2_tx_napi_handler(pfvf, cq, budget);
536 }
537 }
538
539 if (rx_cq && rx_cq->pool_ptrs)
540 pfvf->hw_ops->refill_pool_ptrs(pfvf, rx_cq);
541 /* Clear the IRQ */
542 otx2_write64(pfvf, NIX_LF_CINTX_INT(cq_poll->cint_idx), BIT_ULL(0));
543
544 if (workdone < budget && napi_complete_done(napi, workdone)) {
545 /* If interface is going down, don't re-enable IRQ */
546 if (pfvf->flags & OTX2_FLAG_INTF_DOWN)
547 return workdone;
548
549 /* Check for adaptive interrupt coalesce */
550 if (workdone != 0 &&
551 ((pfvf->flags & OTX2_FLAG_ADPTV_INT_COAL_ENABLED) ==
552 OTX2_FLAG_ADPTV_INT_COAL_ENABLED)) {
553 /* Adjust irq coalese using net_dim */
554 otx2_adjust_adaptive_coalese(pfvf, cq_poll);
555 /* Update irq coalescing */
556 for (i = 0; i < pfvf->hw.cint_cnt; i++)
557 otx2_config_irq_coalescing(pfvf, i);
558 }
559
560 /* Re-enable interrupts */
561 otx2_write64(pfvf, NIX_LF_CINTX_ENA_W1S(cq_poll->cint_idx),
562 BIT_ULL(0));
563 }
564 return workdone;
565 }
566
otx2_sqe_flush(void * dev,struct otx2_snd_queue * sq,int size,int qidx)567 void otx2_sqe_flush(void *dev, struct otx2_snd_queue *sq,
568 int size, int qidx)
569 {
570 u64 status;
571
572 /* Packet data stores should finish before SQE is flushed to HW */
573 dma_wmb();
574
575 do {
576 memcpy(sq->lmt_addr, sq->sqe_base, size);
577 status = otx2_lmt_flush(sq->io_addr);
578 } while (status == 0);
579
580 sq->head++;
581 sq->head &= (sq->sqe_cnt - 1);
582 }
583
584 #define MAX_SEGS_PER_SG 3
585 /* Add SQE scatter/gather subdescriptor structure */
otx2_sqe_add_sg(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct sk_buff * skb,int num_segs,int * offset)586 static bool otx2_sqe_add_sg(struct otx2_nic *pfvf, struct otx2_snd_queue *sq,
587 struct sk_buff *skb, int num_segs, int *offset)
588 {
589 struct nix_sqe_sg_s *sg = NULL;
590 u64 dma_addr, *iova = NULL;
591 u16 *sg_lens = NULL;
592 int seg, len;
593
594 sq->sg[sq->head].num_segs = 0;
595
596 for (seg = 0; seg < num_segs; seg++) {
597 if ((seg % MAX_SEGS_PER_SG) == 0) {
598 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset);
599 sg->ld_type = NIX_SEND_LDTYPE_LDD;
600 sg->subdc = NIX_SUBDC_SG;
601 sg->segs = 0;
602 sg_lens = (void *)sg;
603 iova = (void *)sg + sizeof(*sg);
604 /* Next subdc always starts at a 16byte boundary.
605 * So if sg->segs is whether 2 or 3, offset += 16bytes.
606 */
607 if ((num_segs - seg) >= (MAX_SEGS_PER_SG - 1))
608 *offset += sizeof(*sg) + (3 * sizeof(u64));
609 else
610 *offset += sizeof(*sg) + sizeof(u64);
611 }
612 dma_addr = otx2_dma_map_skb_frag(pfvf, skb, seg, &len);
613 if (dma_mapping_error(pfvf->dev, dma_addr))
614 return false;
615
616 sg_lens[frag_num(seg % MAX_SEGS_PER_SG)] = len;
617 sg->segs++;
618 *iova++ = dma_addr;
619
620 /* Save DMA mapping info for later unmapping */
621 sq->sg[sq->head].dma_addr[seg] = dma_addr;
622 sq->sg[sq->head].size[seg] = len;
623 sq->sg[sq->head].num_segs++;
624 }
625
626 sq->sg[sq->head].skb = (u64)skb;
627 return true;
628 }
629
630 /* Add SQE extended header subdescriptor */
otx2_sqe_add_ext(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct sk_buff * skb,int * offset)631 static void otx2_sqe_add_ext(struct otx2_nic *pfvf, struct otx2_snd_queue *sq,
632 struct sk_buff *skb, int *offset)
633 {
634 struct nix_sqe_ext_s *ext;
635
636 ext = (struct nix_sqe_ext_s *)(sq->sqe_base + *offset);
637 ext->subdc = NIX_SUBDC_EXT;
638 if (skb_shinfo(skb)->gso_size) {
639 ext->lso = 1;
640 ext->lso_sb = skb_tcp_all_headers(skb);
641 ext->lso_mps = skb_shinfo(skb)->gso_size;
642
643 /* Only TSOv4 and TSOv6 GSO offloads are supported */
644 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) {
645 ext->lso_format = pfvf->hw.lso_tsov4_idx;
646
647 /* HW adds payload size to 'ip_hdr->tot_len' while
648 * sending TSO segment, hence set payload length
649 * in IP header of the packet to just header length.
650 */
651 ip_hdr(skb)->tot_len =
652 htons(ext->lso_sb - skb_network_offset(skb));
653 } else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
654 ext->lso_format = pfvf->hw.lso_tsov6_idx;
655
656 ipv6_hdr(skb)->payload_len =
657 htons(ext->lso_sb - skb_network_offset(skb));
658 } else if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
659 __be16 l3_proto = vlan_get_protocol(skb);
660 struct udphdr *udph = udp_hdr(skb);
661 u16 iplen;
662
663 ext->lso_sb = skb_transport_offset(skb) +
664 sizeof(struct udphdr);
665
666 /* HW adds payload size to length fields in IP and
667 * UDP headers while segmentation, hence adjust the
668 * lengths to just header sizes.
669 */
670 iplen = htons(ext->lso_sb - skb_network_offset(skb));
671 if (l3_proto == htons(ETH_P_IP)) {
672 ip_hdr(skb)->tot_len = iplen;
673 ext->lso_format = pfvf->hw.lso_udpv4_idx;
674 } else {
675 ipv6_hdr(skb)->payload_len = iplen;
676 ext->lso_format = pfvf->hw.lso_udpv6_idx;
677 }
678
679 udph->len = htons(sizeof(struct udphdr));
680 }
681 } else if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
682 ext->tstmp = 1;
683 }
684
685 #define OTX2_VLAN_PTR_OFFSET (ETH_HLEN - ETH_TLEN)
686 if (skb_vlan_tag_present(skb)) {
687 if (skb->vlan_proto == htons(ETH_P_8021Q)) {
688 ext->vlan1_ins_ena = 1;
689 ext->vlan1_ins_ptr = OTX2_VLAN_PTR_OFFSET;
690 ext->vlan1_ins_tci = skb_vlan_tag_get(skb);
691 } else if (skb->vlan_proto == htons(ETH_P_8021AD)) {
692 ext->vlan0_ins_ena = 1;
693 ext->vlan0_ins_ptr = OTX2_VLAN_PTR_OFFSET;
694 ext->vlan0_ins_tci = skb_vlan_tag_get(skb);
695 }
696 }
697
698 *offset += sizeof(*ext);
699 }
700
otx2_sqe_add_mem(struct otx2_snd_queue * sq,int * offset,int alg,u64 iova,int ptp_offset,u64 base_ns,bool udp_csum_crt)701 static void otx2_sqe_add_mem(struct otx2_snd_queue *sq, int *offset,
702 int alg, u64 iova, int ptp_offset,
703 u64 base_ns, bool udp_csum_crt)
704 {
705 struct nix_sqe_mem_s *mem;
706
707 mem = (struct nix_sqe_mem_s *)(sq->sqe_base + *offset);
708 mem->subdc = NIX_SUBDC_MEM;
709 mem->alg = alg;
710 mem->wmem = 1; /* wait for the memory operation */
711 mem->addr = iova;
712
713 if (ptp_offset) {
714 mem->start_offset = ptp_offset;
715 mem->udp_csum_crt = !!udp_csum_crt;
716 mem->base_ns = base_ns;
717 mem->step_type = 1;
718 }
719
720 *offset += sizeof(*mem);
721 }
722
723 /* Add SQE header subdescriptor structure */
otx2_sqe_add_hdr(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct nix_sqe_hdr_s * sqe_hdr,struct sk_buff * skb,u16 qidx)724 static void otx2_sqe_add_hdr(struct otx2_nic *pfvf, struct otx2_snd_queue *sq,
725 struct nix_sqe_hdr_s *sqe_hdr,
726 struct sk_buff *skb, u16 qidx)
727 {
728 int proto = 0;
729
730 /* Check if SQE was framed before, if yes then no need to
731 * set these constants again and again.
732 */
733 if (!sqe_hdr->total) {
734 /* Don't free Tx buffers to Aura */
735 sqe_hdr->df = 1;
736 sqe_hdr->aura = sq->aura_id;
737 /* Post a CQE Tx after pkt transmission */
738 sqe_hdr->pnc = 1;
739 sqe_hdr->sq = qidx;
740 }
741 sqe_hdr->total = skb->len;
742 /* Set SQE identifier which will be used later for freeing SKB */
743 sqe_hdr->sqe_id = sq->head;
744
745 /* Offload TCP/UDP checksum to HW */
746 if (skb->ip_summed == CHECKSUM_PARTIAL) {
747 sqe_hdr->ol3ptr = skb_network_offset(skb);
748 sqe_hdr->ol4ptr = skb_transport_offset(skb);
749 /* get vlan protocol Ethertype */
750 if (eth_type_vlan(skb->protocol))
751 skb->protocol = vlan_get_protocol(skb);
752
753 if (skb->protocol == htons(ETH_P_IP)) {
754 proto = ip_hdr(skb)->protocol;
755 /* In case of TSO, HW needs this to be explicitly set.
756 * So set this always, instead of adding a check.
757 */
758 sqe_hdr->ol3type = NIX_SENDL3TYPE_IP4_CKSUM;
759 } else if (skb->protocol == htons(ETH_P_IPV6)) {
760 proto = ipv6_hdr(skb)->nexthdr;
761 sqe_hdr->ol3type = NIX_SENDL3TYPE_IP6;
762 }
763
764 if (proto == IPPROTO_TCP)
765 sqe_hdr->ol4type = NIX_SENDL4TYPE_TCP_CKSUM;
766 else if (proto == IPPROTO_UDP)
767 sqe_hdr->ol4type = NIX_SENDL4TYPE_UDP_CKSUM;
768 }
769 }
770
otx2_dma_map_tso_skb(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct sk_buff * skb,int sqe,int hdr_len)771 static int otx2_dma_map_tso_skb(struct otx2_nic *pfvf,
772 struct otx2_snd_queue *sq,
773 struct sk_buff *skb, int sqe, int hdr_len)
774 {
775 int num_segs = skb_shinfo(skb)->nr_frags + 1;
776 struct sg_list *sg = &sq->sg[sqe];
777 u64 dma_addr;
778 int seg, len;
779
780 sg->num_segs = 0;
781
782 /* Get payload length at skb->data */
783 len = skb_headlen(skb) - hdr_len;
784
785 for (seg = 0; seg < num_segs; seg++) {
786 /* Skip skb->data, if there is no payload */
787 if (!seg && !len)
788 continue;
789 dma_addr = otx2_dma_map_skb_frag(pfvf, skb, seg, &len);
790 if (dma_mapping_error(pfvf->dev, dma_addr))
791 goto unmap;
792
793 /* Save DMA mapping info for later unmapping */
794 sg->dma_addr[sg->num_segs] = dma_addr;
795 sg->size[sg->num_segs] = len;
796 sg->num_segs++;
797 }
798 return 0;
799 unmap:
800 otx2_dma_unmap_skb_frags(pfvf, sg);
801 return -EINVAL;
802 }
803
otx2_tso_frag_dma_addr(struct otx2_snd_queue * sq,struct sk_buff * skb,int seg,u64 seg_addr,int hdr_len,int sqe)804 static u64 otx2_tso_frag_dma_addr(struct otx2_snd_queue *sq,
805 struct sk_buff *skb, int seg,
806 u64 seg_addr, int hdr_len, int sqe)
807 {
808 struct sg_list *sg = &sq->sg[sqe];
809 const skb_frag_t *frag;
810 int offset;
811
812 if (seg < 0)
813 return sg->dma_addr[0] + (seg_addr - (u64)skb->data);
814
815 frag = &skb_shinfo(skb)->frags[seg];
816 offset = seg_addr - (u64)skb_frag_address(frag);
817 if (skb_headlen(skb) - hdr_len)
818 seg++;
819 return sg->dma_addr[seg] + offset;
820 }
821
otx2_sqe_tso_add_sg(struct otx2_snd_queue * sq,struct sg_list * list,int * offset)822 static void otx2_sqe_tso_add_sg(struct otx2_snd_queue *sq,
823 struct sg_list *list, int *offset)
824 {
825 struct nix_sqe_sg_s *sg = NULL;
826 u16 *sg_lens = NULL;
827 u64 *iova = NULL;
828 int seg;
829
830 /* Add SG descriptors with buffer addresses */
831 for (seg = 0; seg < list->num_segs; seg++) {
832 if ((seg % MAX_SEGS_PER_SG) == 0) {
833 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset);
834 sg->ld_type = NIX_SEND_LDTYPE_LDD;
835 sg->subdc = NIX_SUBDC_SG;
836 sg->segs = 0;
837 sg_lens = (void *)sg;
838 iova = (void *)sg + sizeof(*sg);
839 /* Next subdc always starts at a 16byte boundary.
840 * So if sg->segs is whether 2 or 3, offset += 16bytes.
841 */
842 if ((list->num_segs - seg) >= (MAX_SEGS_PER_SG - 1))
843 *offset += sizeof(*sg) + (3 * sizeof(u64));
844 else
845 *offset += sizeof(*sg) + sizeof(u64);
846 }
847 sg_lens[frag_num(seg % MAX_SEGS_PER_SG)] = list->size[seg];
848 *iova++ = list->dma_addr[seg];
849 sg->segs++;
850 }
851 }
852
otx2_sq_append_tso(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct sk_buff * skb,u16 qidx)853 static void otx2_sq_append_tso(struct otx2_nic *pfvf, struct otx2_snd_queue *sq,
854 struct sk_buff *skb, u16 qidx)
855 {
856 struct netdev_queue *txq = netdev_get_tx_queue(pfvf->netdev, qidx);
857 int hdr_len, tcp_data, seg_len, pkt_len, offset;
858 struct nix_sqe_hdr_s *sqe_hdr;
859 int first_sqe = sq->head;
860 struct sg_list list;
861 struct tso_t tso;
862
863 hdr_len = tso_start(skb, &tso);
864
865 /* Map SKB's fragments to DMA.
866 * It's done here to avoid mapping for every TSO segment's packet.
867 */
868 if (otx2_dma_map_tso_skb(pfvf, sq, skb, first_sqe, hdr_len)) {
869 dev_kfree_skb_any(skb);
870 return;
871 }
872
873 netdev_tx_sent_queue(txq, skb->len);
874
875 tcp_data = skb->len - hdr_len;
876 while (tcp_data > 0) {
877 char *hdr;
878
879 seg_len = min_t(int, skb_shinfo(skb)->gso_size, tcp_data);
880 tcp_data -= seg_len;
881
882 /* Set SQE's SEND_HDR */
883 memset(sq->sqe_base, 0, sq->sqe_size);
884 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base);
885 otx2_sqe_add_hdr(pfvf, sq, sqe_hdr, skb, qidx);
886 offset = sizeof(*sqe_hdr);
887
888 /* Add TSO segment's pkt header */
889 hdr = sq->tso_hdrs->base + (sq->head * TSO_HEADER_SIZE);
890 tso_build_hdr(skb, hdr, &tso, seg_len, tcp_data == 0);
891 list.dma_addr[0] =
892 sq->tso_hdrs->iova + (sq->head * TSO_HEADER_SIZE);
893 list.size[0] = hdr_len;
894 list.num_segs = 1;
895
896 /* Add TSO segment's payload data fragments */
897 pkt_len = hdr_len;
898 while (seg_len > 0) {
899 int size;
900
901 size = min_t(int, tso.size, seg_len);
902
903 list.size[list.num_segs] = size;
904 list.dma_addr[list.num_segs] =
905 otx2_tso_frag_dma_addr(sq, skb,
906 tso.next_frag_idx - 1,
907 (u64)tso.data, hdr_len,
908 first_sqe);
909 list.num_segs++;
910 pkt_len += size;
911 seg_len -= size;
912 tso_build_data(skb, &tso, size);
913 }
914 sqe_hdr->total = pkt_len;
915 otx2_sqe_tso_add_sg(sq, &list, &offset);
916
917 /* DMA mappings and skb needs to be freed only after last
918 * TSO segment is transmitted out. So set 'PNC' only for
919 * last segment. Also point last segment's sqe_id to first
920 * segment's SQE index where skb address and DMA mappings
921 * are saved.
922 */
923 if (!tcp_data) {
924 sqe_hdr->pnc = 1;
925 sqe_hdr->sqe_id = first_sqe;
926 sq->sg[first_sqe].skb = (u64)skb;
927 } else {
928 sqe_hdr->pnc = 0;
929 }
930
931 sqe_hdr->sizem1 = (offset / 16) - 1;
932
933 /* Flush SQE to HW */
934 pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx);
935 }
936 }
937
is_hw_tso_supported(struct otx2_nic * pfvf,struct sk_buff * skb)938 static bool is_hw_tso_supported(struct otx2_nic *pfvf,
939 struct sk_buff *skb)
940 {
941 int payload_len, last_seg_size;
942
943 if (test_bit(HW_TSO, &pfvf->hw.cap_flag))
944 return true;
945
946 /* On 96xx A0, HW TSO not supported */
947 if (!is_96xx_B0(pfvf->pdev))
948 return false;
949
950 /* HW has an issue due to which when the payload of the last LSO
951 * segment is shorter than 16 bytes, some header fields may not
952 * be correctly modified, hence don't offload such TSO segments.
953 */
954
955 payload_len = skb->len - skb_tcp_all_headers(skb);
956 last_seg_size = payload_len % skb_shinfo(skb)->gso_size;
957 if (last_seg_size && last_seg_size < 16)
958 return false;
959
960 return true;
961 }
962
otx2_get_sqe_count(struct otx2_nic * pfvf,struct sk_buff * skb)963 static int otx2_get_sqe_count(struct otx2_nic *pfvf, struct sk_buff *skb)
964 {
965 if (!skb_shinfo(skb)->gso_size)
966 return 1;
967
968 /* HW TSO */
969 if (is_hw_tso_supported(pfvf, skb))
970 return 1;
971
972 /* SW TSO */
973 return skb_shinfo(skb)->gso_segs;
974 }
975
otx2_validate_network_transport(struct sk_buff * skb)976 static bool otx2_validate_network_transport(struct sk_buff *skb)
977 {
978 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) ||
979 (ipv6_hdr(skb)->nexthdr == IPPROTO_UDP)) {
980 struct udphdr *udph = udp_hdr(skb);
981
982 if (udph->source == htons(PTP_PORT) &&
983 udph->dest == htons(PTP_PORT))
984 return true;
985 }
986
987 return false;
988 }
989
otx2_ptp_is_sync(struct sk_buff * skb,int * offset,bool * udp_csum_crt)990 static bool otx2_ptp_is_sync(struct sk_buff *skb, int *offset, bool *udp_csum_crt)
991 {
992 struct ethhdr *eth = (struct ethhdr *)(skb->data);
993 u16 nix_offload_hlen = 0, inner_vhlen = 0;
994 bool udp_hdr_present = false, is_sync;
995 u8 *data = skb->data, *msgtype;
996 __be16 proto = eth->h_proto;
997 int network_depth = 0;
998
999 /* NIX is programmed to offload outer VLAN header
1000 * in case of single vlan protocol field holds Network header ETH_IP/V6
1001 * in case of stacked vlan protocol field holds Inner vlan (8100)
1002 */
1003 if (skb->dev->features & NETIF_F_HW_VLAN_CTAG_TX &&
1004 skb->dev->features & NETIF_F_HW_VLAN_STAG_TX) {
1005 if (skb->vlan_proto == htons(ETH_P_8021AD)) {
1006 /* Get vlan protocol */
1007 proto = __vlan_get_protocol(skb, eth->h_proto, NULL);
1008 /* SKB APIs like skb_transport_offset does not include
1009 * offloaded vlan header length. Need to explicitly add
1010 * the length
1011 */
1012 nix_offload_hlen = VLAN_HLEN;
1013 inner_vhlen = VLAN_HLEN;
1014 } else if (skb->vlan_proto == htons(ETH_P_8021Q)) {
1015 nix_offload_hlen = VLAN_HLEN;
1016 }
1017 } else if (eth_type_vlan(eth->h_proto)) {
1018 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
1019 }
1020
1021 switch (ntohs(proto)) {
1022 case ETH_P_1588:
1023 if (network_depth)
1024 *offset = network_depth;
1025 else
1026 *offset = ETH_HLEN + nix_offload_hlen +
1027 inner_vhlen;
1028 break;
1029 case ETH_P_IP:
1030 case ETH_P_IPV6:
1031 if (!otx2_validate_network_transport(skb))
1032 return false;
1033
1034 *offset = nix_offload_hlen + skb_transport_offset(skb) +
1035 sizeof(struct udphdr);
1036 udp_hdr_present = true;
1037
1038 }
1039
1040 msgtype = data + *offset;
1041 /* Check PTP messageId is SYNC or not */
1042 is_sync = !(*msgtype & 0xf);
1043 if (is_sync)
1044 *udp_csum_crt = udp_hdr_present;
1045 else
1046 *offset = 0;
1047
1048 return is_sync;
1049 }
1050
otx2_set_txtstamp(struct otx2_nic * pfvf,struct sk_buff * skb,struct otx2_snd_queue * sq,int * offset)1051 static void otx2_set_txtstamp(struct otx2_nic *pfvf, struct sk_buff *skb,
1052 struct otx2_snd_queue *sq, int *offset)
1053 {
1054 struct ethhdr *eth = (struct ethhdr *)(skb->data);
1055 struct ptpv2_tstamp *origin_tstamp;
1056 bool udp_csum_crt = false;
1057 unsigned int udphoff;
1058 struct timespec64 ts;
1059 int ptp_offset = 0;
1060 __wsum skb_csum;
1061 u64 iova;
1062
1063 if (unlikely(!skb_shinfo(skb)->gso_size &&
1064 (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) {
1065 if (unlikely(pfvf->flags & OTX2_FLAG_PTP_ONESTEP_SYNC &&
1066 otx2_ptp_is_sync(skb, &ptp_offset, &udp_csum_crt))) {
1067 origin_tstamp = (struct ptpv2_tstamp *)
1068 ((u8 *)skb->data + ptp_offset +
1069 PTP_SYNC_SEC_OFFSET);
1070 ts = ns_to_timespec64(pfvf->ptp->tstamp);
1071 origin_tstamp->seconds_msb = htons((ts.tv_sec >> 32) & 0xffff);
1072 origin_tstamp->seconds_lsb = htonl(ts.tv_sec & 0xffffffff);
1073 origin_tstamp->nanoseconds = htonl(ts.tv_nsec);
1074 /* Point to correction field in PTP packet */
1075 ptp_offset += 8;
1076
1077 /* When user disables hw checksum, stack calculates the csum,
1078 * but it does not cover ptp timestamp which is added later.
1079 * Recalculate the checksum manually considering the timestamp.
1080 */
1081 if (udp_csum_crt) {
1082 struct udphdr *uh = udp_hdr(skb);
1083
1084 if (skb->ip_summed != CHECKSUM_PARTIAL && uh->check != 0) {
1085 udphoff = skb_transport_offset(skb);
1086 uh->check = 0;
1087 skb_csum = skb_checksum(skb, udphoff, skb->len - udphoff,
1088 0);
1089 if (ntohs(eth->h_proto) == ETH_P_IPV6)
1090 uh->check = csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1091 &ipv6_hdr(skb)->daddr,
1092 skb->len - udphoff,
1093 ipv6_hdr(skb)->nexthdr,
1094 skb_csum);
1095 else
1096 uh->check = csum_tcpudp_magic(ip_hdr(skb)->saddr,
1097 ip_hdr(skb)->daddr,
1098 skb->len - udphoff,
1099 IPPROTO_UDP,
1100 skb_csum);
1101 }
1102 }
1103 } else {
1104 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1105 }
1106 iova = sq->timestamps->iova + (sq->head * sizeof(u64));
1107 otx2_sqe_add_mem(sq, offset, NIX_SENDMEMALG_E_SETTSTMP, iova,
1108 ptp_offset, pfvf->ptp->base_ns, udp_csum_crt);
1109 } else {
1110 skb_tx_timestamp(skb);
1111 }
1112 }
1113
otx2_sq_append_skb(struct net_device * netdev,struct otx2_snd_queue * sq,struct sk_buff * skb,u16 qidx)1114 bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq,
1115 struct sk_buff *skb, u16 qidx)
1116 {
1117 struct netdev_queue *txq = netdev_get_tx_queue(netdev, qidx);
1118 struct otx2_nic *pfvf = netdev_priv(netdev);
1119 int offset, num_segs, free_desc;
1120 struct nix_sqe_hdr_s *sqe_hdr;
1121
1122 /* Check if there is enough room between producer
1123 * and consumer index.
1124 */
1125 free_desc = (sq->cons_head - sq->head - 1 + sq->sqe_cnt) & (sq->sqe_cnt - 1);
1126 if (free_desc < sq->sqe_thresh)
1127 return false;
1128
1129 if (free_desc < otx2_get_sqe_count(pfvf, skb))
1130 return false;
1131
1132 num_segs = skb_shinfo(skb)->nr_frags + 1;
1133
1134 /* If SKB doesn't fit in a single SQE, linearize it.
1135 * TODO: Consider adding JUMP descriptor instead.
1136 */
1137 if (unlikely(num_segs > OTX2_MAX_FRAGS_IN_SQE)) {
1138 if (__skb_linearize(skb)) {
1139 dev_kfree_skb_any(skb);
1140 return true;
1141 }
1142 num_segs = skb_shinfo(skb)->nr_frags + 1;
1143 }
1144
1145 if (skb_shinfo(skb)->gso_size && !is_hw_tso_supported(pfvf, skb)) {
1146 /* Insert vlan tag before giving pkt to tso */
1147 if (skb_vlan_tag_present(skb))
1148 skb = __vlan_hwaccel_push_inside(skb);
1149 otx2_sq_append_tso(pfvf, sq, skb, qidx);
1150 return true;
1151 }
1152
1153 /* Set SQE's SEND_HDR.
1154 * Do not clear the first 64bit as it contains constant info.
1155 */
1156 memset(sq->sqe_base + 8, 0, sq->sqe_size - 8);
1157 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base);
1158 otx2_sqe_add_hdr(pfvf, sq, sqe_hdr, skb, qidx);
1159 offset = sizeof(*sqe_hdr);
1160
1161 /* Add extended header if needed */
1162 otx2_sqe_add_ext(pfvf, sq, skb, &offset);
1163
1164 /* Add SG subdesc with data frags */
1165 if (!otx2_sqe_add_sg(pfvf, sq, skb, num_segs, &offset)) {
1166 otx2_dma_unmap_skb_frags(pfvf, &sq->sg[sq->head]);
1167 return false;
1168 }
1169
1170 otx2_set_txtstamp(pfvf, skb, sq, &offset);
1171
1172 sqe_hdr->sizem1 = (offset / 16) - 1;
1173
1174 netdev_tx_sent_queue(txq, skb->len);
1175
1176 /* Flush SQE to HW */
1177 pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx);
1178
1179 return true;
1180 }
1181 EXPORT_SYMBOL(otx2_sq_append_skb);
1182
otx2_cleanup_rx_cqes(struct otx2_nic * pfvf,struct otx2_cq_queue * cq)1183 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq)
1184 {
1185 struct nix_cqe_rx_s *cqe;
1186 int processed_cqe = 0;
1187 u64 iova, pa;
1188
1189 if (pfvf->xdp_prog)
1190 xdp_rxq_info_unreg(&cq->xdp_rxq);
1191
1192 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe)
1193 return;
1194
1195 while (cq->pend_cqe) {
1196 cqe = (struct nix_cqe_rx_s *)otx2_get_next_cqe(cq);
1197 processed_cqe++;
1198 cq->pend_cqe--;
1199
1200 if (!cqe)
1201 continue;
1202 if (cqe->sg.segs > 1) {
1203 otx2_free_rcv_seg(pfvf, cqe, cq->cq_idx);
1204 continue;
1205 }
1206 iova = cqe->sg.seg_addr - OTX2_HEAD_ROOM;
1207 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova);
1208 otx2_dma_unmap_page(pfvf, iova, pfvf->rbsize, DMA_FROM_DEVICE);
1209 put_page(virt_to_page(phys_to_virt(pa)));
1210 }
1211
1212 /* Free CQEs to HW */
1213 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR,
1214 ((u64)cq->cq_idx << 32) | processed_cqe);
1215 }
1216
otx2_cleanup_tx_cqes(struct otx2_nic * pfvf,struct otx2_cq_queue * cq)1217 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq)
1218 {
1219 struct sk_buff *skb = NULL;
1220 struct otx2_snd_queue *sq;
1221 struct nix_cqe_tx_s *cqe;
1222 int processed_cqe = 0;
1223 struct sg_list *sg;
1224
1225 sq = &pfvf->qset.sq[cq->cint_idx];
1226
1227 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe)
1228 return;
1229
1230 while (cq->pend_cqe) {
1231 cqe = (struct nix_cqe_tx_s *)otx2_get_next_cqe(cq);
1232 processed_cqe++;
1233 cq->pend_cqe--;
1234
1235 if (!cqe)
1236 continue;
1237 sg = &sq->sg[cqe->comp.sqe_id];
1238 skb = (struct sk_buff *)sg->skb;
1239 if (skb) {
1240 otx2_dma_unmap_skb_frags(pfvf, sg);
1241 dev_kfree_skb_any(skb);
1242 sg->skb = (u64)NULL;
1243 }
1244 }
1245
1246 /* Free CQEs to HW */
1247 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR,
1248 ((u64)cq->cq_idx << 32) | processed_cqe);
1249 }
1250
otx2_rxtx_enable(struct otx2_nic * pfvf,bool enable)1251 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable)
1252 {
1253 struct msg_req *msg;
1254 int err;
1255
1256 mutex_lock(&pfvf->mbox.lock);
1257 if (enable)
1258 msg = otx2_mbox_alloc_msg_nix_lf_start_rx(&pfvf->mbox);
1259 else
1260 msg = otx2_mbox_alloc_msg_nix_lf_stop_rx(&pfvf->mbox);
1261
1262 if (!msg) {
1263 mutex_unlock(&pfvf->mbox.lock);
1264 return -ENOMEM;
1265 }
1266
1267 err = otx2_sync_mbox_msg(&pfvf->mbox);
1268 mutex_unlock(&pfvf->mbox.lock);
1269 return err;
1270 }
1271
otx2_xdp_sqe_add_sg(struct otx2_snd_queue * sq,u64 dma_addr,int len,int * offset)1272 static void otx2_xdp_sqe_add_sg(struct otx2_snd_queue *sq, u64 dma_addr,
1273 int len, int *offset)
1274 {
1275 struct nix_sqe_sg_s *sg = NULL;
1276 u64 *iova = NULL;
1277
1278 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset);
1279 sg->ld_type = NIX_SEND_LDTYPE_LDD;
1280 sg->subdc = NIX_SUBDC_SG;
1281 sg->segs = 1;
1282 sg->seg1_size = len;
1283 iova = (void *)sg + sizeof(*sg);
1284 *iova = dma_addr;
1285 *offset += sizeof(*sg) + sizeof(u64);
1286
1287 sq->sg[sq->head].dma_addr[0] = dma_addr;
1288 sq->sg[sq->head].size[0] = len;
1289 sq->sg[sq->head].num_segs = 1;
1290 }
1291
otx2_xdp_sq_append_pkt(struct otx2_nic * pfvf,u64 iova,int len,u16 qidx)1292 bool otx2_xdp_sq_append_pkt(struct otx2_nic *pfvf, u64 iova, int len, u16 qidx)
1293 {
1294 struct nix_sqe_hdr_s *sqe_hdr;
1295 struct otx2_snd_queue *sq;
1296 int offset, free_sqe;
1297
1298 sq = &pfvf->qset.sq[qidx];
1299 free_sqe = (sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb;
1300 if (free_sqe < sq->sqe_thresh)
1301 return false;
1302
1303 memset(sq->sqe_base + 8, 0, sq->sqe_size - 8);
1304
1305 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base);
1306
1307 if (!sqe_hdr->total) {
1308 sqe_hdr->aura = sq->aura_id;
1309 sqe_hdr->df = 1;
1310 sqe_hdr->sq = qidx;
1311 sqe_hdr->pnc = 1;
1312 }
1313 sqe_hdr->total = len;
1314 sqe_hdr->sqe_id = sq->head;
1315
1316 offset = sizeof(*sqe_hdr);
1317
1318 otx2_xdp_sqe_add_sg(sq, iova, len, &offset);
1319 sqe_hdr->sizem1 = (offset / 16) - 1;
1320 pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx);
1321
1322 return true;
1323 }
1324
otx2_xdp_rcv_pkt_handler(struct otx2_nic * pfvf,struct bpf_prog * prog,struct nix_cqe_rx_s * cqe,struct otx2_cq_queue * cq)1325 static bool otx2_xdp_rcv_pkt_handler(struct otx2_nic *pfvf,
1326 struct bpf_prog *prog,
1327 struct nix_cqe_rx_s *cqe,
1328 struct otx2_cq_queue *cq)
1329 {
1330 unsigned char *hard_start, *data;
1331 int qidx = cq->cq_idx;
1332 struct xdp_buff xdp;
1333 struct page *page;
1334 u64 iova, pa;
1335 u32 act;
1336 int err;
1337
1338 iova = cqe->sg.seg_addr - OTX2_HEAD_ROOM;
1339 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova);
1340 page = virt_to_page(phys_to_virt(pa));
1341
1342 xdp_init_buff(&xdp, pfvf->rbsize, &cq->xdp_rxq);
1343
1344 data = (unsigned char *)phys_to_virt(pa);
1345 hard_start = page_address(page);
1346 xdp_prepare_buff(&xdp, hard_start, data - hard_start,
1347 cqe->sg.seg_size, false);
1348
1349 act = bpf_prog_run_xdp(prog, &xdp);
1350
1351 switch (act) {
1352 case XDP_PASS:
1353 break;
1354 case XDP_TX:
1355 qidx += pfvf->hw.tx_queues;
1356 cq->pool_ptrs++;
1357 return otx2_xdp_sq_append_pkt(pfvf, iova,
1358 cqe->sg.seg_size, qidx);
1359 case XDP_REDIRECT:
1360 cq->pool_ptrs++;
1361 err = xdp_do_redirect(pfvf->netdev, &xdp, prog);
1362
1363 otx2_dma_unmap_page(pfvf, iova, pfvf->rbsize,
1364 DMA_FROM_DEVICE);
1365 if (!err)
1366 return true;
1367 put_page(page);
1368 break;
1369 default:
1370 bpf_warn_invalid_xdp_action(pfvf->netdev, prog, act);
1371 break;
1372 case XDP_ABORTED:
1373 trace_xdp_exception(pfvf->netdev, prog, act);
1374 break;
1375 case XDP_DROP:
1376 otx2_dma_unmap_page(pfvf, iova, pfvf->rbsize,
1377 DMA_FROM_DEVICE);
1378 put_page(page);
1379 cq->pool_ptrs++;
1380 return true;
1381 }
1382 return false;
1383 }
1384