1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5 #ifndef __RTW8723D_H__
6 #define __RTW8723D_H__
7
8 enum rtw8723d_path {
9 PATH_S1,
10 PATH_S0,
11 PATH_NR,
12 };
13
14 enum rtw8723d_iqk_round {
15 IQK_ROUND_0,
16 IQK_ROUND_1,
17 IQK_ROUND_2,
18 IQK_ROUND_HYBRID,
19 IQK_ROUND_SIZE,
20 IQK_ROUND_INVALID = 0xff,
21 };
22
23 enum rtw8723d_iqk_result {
24 IQK_S1_TX_X,
25 IQK_S1_TX_Y,
26 IQK_S1_RX_X,
27 IQK_S1_RX_Y,
28 IQK_S0_TX_X,
29 IQK_S0_TX_Y,
30 IQK_S0_RX_X,
31 IQK_S0_RX_Y,
32 IQK_NR,
33 IQK_SX_NR = IQK_NR / PATH_NR,
34 };
35
36 struct rtw8723de_efuse {
37 u8 mac_addr[ETH_ALEN]; /* 0xd0 */
38 u8 vender_id[2];
39 u8 device_id[2];
40 u8 sub_vender_id[2];
41 u8 sub_device_id[2];
42 };
43
44 struct rtw8723du_efuse {
45 u8 res4[48]; /* 0xd0 */
46 u8 vender_id[2]; /* 0x100 */
47 u8 product_id[2]; /* 0x102 */
48 u8 usb_option; /* 0x104 */
49 u8 mac_addr[ETH_ALEN]; /* 0x107 */
50 };
51
52 struct rtw8723d_efuse {
53 __le16 rtl_id;
54 u8 rsvd[2];
55 u8 afe;
56 u8 rsvd1[11];
57
58 /* power index for four RF paths */
59 struct rtw_txpwr_idx txpwr_idx_table[4];
60
61 u8 channel_plan; /* 0xb8 */
62 u8 xtal_k;
63 u8 thermal_meter;
64 u8 iqk_lck;
65 u8 pa_type; /* 0xbc */
66 u8 lna_type_2g[2]; /* 0xbd */
67 u8 lna_type_5g[2];
68 u8 rf_board_option;
69 u8 rf_feature_option;
70 u8 rf_bt_setting;
71 u8 eeprom_version;
72 u8 eeprom_customer_id;
73 u8 tx_bb_swing_setting_2g;
74 u8 res_c7;
75 u8 tx_pwr_calibrate_rate;
76 u8 rf_antenna_option; /* 0xc9 */
77 u8 rfe_option;
78 u8 country_code[2];
79 u8 res[3];
80 union {
81 struct rtw8723de_efuse e;
82 struct rtw8723du_efuse u;
83 };
84 };
85
86 extern const struct rtw_chip_info rtw8723d_hw_spec;
87
88 /* phy status page0 */
89 #define GET_PHY_STAT_P0_PWDB(phy_stat) \
90 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
91
92 /* phy status page1 */
93 #define GET_PHY_STAT_P1_PWDB_A(phy_stat) \
94 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
95 #define GET_PHY_STAT_P1_PWDB_B(phy_stat) \
96 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
97 #define GET_PHY_STAT_P1_RF_MODE(phy_stat) \
98 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
99 #define GET_PHY_STAT_P1_L_RXSC(phy_stat) \
100 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
101 #define GET_PHY_STAT_P1_HT_RXSC(phy_stat) \
102 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
103 #define GET_PHY_STAT_P1_RXEVM_A(phy_stat) \
104 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
105 #define GET_PHY_STAT_P1_CFO_TAIL_A(phy_stat) \
106 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
107 #define GET_PHY_STAT_P1_RXSNR_A(phy_stat) \
108 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
109
iqkxy_to_s32(s32 val)110 static inline s32 iqkxy_to_s32(s32 val)
111 {
112 /* val is Q10.8 */
113 return sign_extend32(val, 9);
114 }
115
iqk_mult(s32 x,s32 y,s32 * ext)116 static inline s32 iqk_mult(s32 x, s32 y, s32 *ext)
117 {
118 /* x, y and return value are Q10.8 */
119 s32 t;
120
121 t = x * y;
122 if (ext)
123 *ext = (t >> 7) & 0x1; /* Q.16 --> Q.9; get LSB of Q.9 */
124
125 return (t >> 8); /* Q.16 --> Q.8 */
126 }
127
128 #define OFDM_SWING_A(swing) FIELD_GET(GENMASK(9, 0), swing)
129 #define OFDM_SWING_B(swing) FIELD_GET(GENMASK(15, 10), swing)
130 #define OFDM_SWING_C(swing) FIELD_GET(GENMASK(21, 16), swing)
131 #define OFDM_SWING_D(swing) FIELD_GET(GENMASK(31, 22), swing)
132 #define RTW_DEF_OFDM_SWING_INDEX 28
133 #define RTW_DEF_CCK_SWING_INDEX 28
134
135 #define MAX_TOLERANCE 5
136 #define IQK_TX_X_ERR 0x142
137 #define IQK_TX_Y_ERR 0x42
138 #define IQK_RX_X_UPPER 0x11a
139 #define IQK_RX_X_LOWER 0xe6
140 #define IQK_RX_Y_LMT 0x1a
141 #define IQK_TX_OK BIT(0)
142 #define IQK_RX_OK BIT(1)
143 #define PATH_IQK_RETRY 2
144
145 #define SPUR_THRES 0x16
146 #define CCK_DFIR_NR 3
147 #define DIS_3WIRE 0xccf000c0
148 #define EN_3WIRE 0xccc000c0
149 #define START_PSD 0x400000
150 #define FREQ_CH13 0xfccd
151 #define FREQ_CH14 0xff9a
152 #define RFCFGCH_CHANNEL_MASK GENMASK(7, 0)
153 #define RFCFGCH_BW_MASK (BIT(11) | BIT(10))
154 #define RFCFGCH_BW_20M (BIT(11) | BIT(10))
155 #define RFCFGCH_BW_40M BIT(10)
156 #define BIT_MASK_RFMOD BIT(0)
157 #define BIT_LCK BIT(15)
158
159 #define REG_GPIO_INTM 0x0048
160 #define REG_BTG_SEL 0x0067
161 #define BIT_MASK_BTG_WL BIT(7)
162 #define REG_LTECOEX_PATH_CONTROL 0x0070
163 #define REG_LTECOEX_CTRL 0x07c0
164 #define REG_LTECOEX_WRITE_DATA 0x07c4
165 #define REG_LTECOEX_READ_DATA 0x07c8
166 #define REG_PSDFN 0x0808
167 #define REG_BB_PWR_SAV1_11N 0x0874
168 #define REG_ANA_PARAM1 0x0880
169 #define REG_ANALOG_P4 0x088c
170 #define REG_PSDRPT 0x08b4
171 #define REG_FPGA1_RFMOD 0x0900
172 #define REG_BB_SEL_BTG 0x0948
173 #define REG_BBRX_DFIR 0x0954
174 #define BIT_MASK_RXBB_DFIR GENMASK(27, 24)
175 #define BIT_RXBB_DFIR_EN BIT(19)
176 #define REG_CCK0_SYS 0x0a00
177 #define BIT_CCK_SIDE_BAND BIT(4)
178 #define REG_CCK_ANT_SEL_11N 0x0a04
179 #define REG_PWRTH 0x0a08
180 #define REG_CCK_FA_RST_11N 0x0a2c
181 #define BIT_MASK_CCK_CNT_KEEP BIT(12)
182 #define BIT_MASK_CCK_CNT_EN BIT(13)
183 #define BIT_MASK_CCK_CNT_KPEN (BIT_MASK_CCK_CNT_KEEP | BIT_MASK_CCK_CNT_EN)
184 #define BIT_MASK_CCK_FA_KEEP BIT(14)
185 #define BIT_MASK_CCK_FA_EN BIT(15)
186 #define BIT_MASK_CCK_FA_KPEN (BIT_MASK_CCK_FA_KEEP | BIT_MASK_CCK_FA_EN)
187 #define REG_CCK_FA_LSB_11N 0x0a5c
188 #define REG_CCK_FA_MSB_11N 0x0a58
189 #define REG_CCK_CCA_CNT_11N 0x0a60
190 #define BIT_MASK_CCK_FA_MSB GENMASK(7, 0)
191 #define BIT_MASK_CCK_FA_LSB GENMASK(15, 8)
192 #define REG_PWRTH2 0x0aa8
193 #define REG_CSRATIO 0x0aaa
194 #define REG_OFDM_FA_HOLDC_11N 0x0c00
195 #define BIT_MASK_OFDM_FA_KEEP BIT(31)
196 #define REG_BB_RX_PATH_11N 0x0c04
197 #define REG_TRMUX_11N 0x0c08
198 #define REG_OFDM_FA_RSTC_11N 0x0c0c
199 #define BIT_MASK_OFDM_FA_RST BIT(31)
200 #define REG_A_RXIQI 0x0c14
201 #define BIT_MASK_RXIQ_S1_X 0x000003FF
202 #define BIT_MASK_RXIQ_S1_Y1 0x0000FC00
203 #define BIT_SET_RXIQ_S1_Y1(y) ((y) & 0x3F)
204 #define REG_OFDM0_RXDSP 0x0c40
205 #define BIT_MASK_RXDSP GENMASK(28, 24)
206 #define BIT_EN_RXDSP BIT(9)
207 #define REG_OFDM_0_ECCA_THRESHOLD 0x0c4c
208 #define BIT_MASK_OFDM0_EXT_A BIT(31)
209 #define BIT_MASK_OFDM0_EXT_C BIT(29)
210 #define BIT_MASK_OFDM0_EXTS (BIT(31) | BIT(29) | BIT(28))
211 #define BIT_SET_OFDM0_EXTS(a, c, d) (((a) << 31) | ((c) << 29) | ((d) << 28))
212 #define REG_OFDM0_XAAGC1 0x0c50
213 #define REG_OFDM0_XBAGC1 0x0c58
214 #define REG_AGCRSSI 0x0c78
215 #define REG_OFDM_0_XA_TX_IQ_IMBALANCE 0x0c80
216 #define BIT_MASK_TXIQ_ELM_A 0x03ff
217 #define BIT_SET_TXIQ_ELM_ACD(a, c, d) (((d) << 22) | (((c) & 0x3F) << 16) | \
218 ((a) & 0x03ff))
219 #define BIT_MASK_TXIQ_ELM_C GENMASK(21, 16)
220 #define BIT_SET_TXIQ_ELM_C2(c) ((c) & 0x3F)
221 #define BIT_MASK_TXIQ_ELM_D GENMASK(31, 22)
222 #define REG_TXIQK_MATRIXA_LSB2_11N 0x0c94
223 #define BIT_SET_TXIQ_ELM_C1(c) (((c) & 0x000003C0) >> 6)
224 #define REG_RXIQK_MATRIX_LSB_11N 0x0ca0
225 #define BIT_MASK_RXIQ_S1_Y2 0xF0000000
226 #define BIT_SET_RXIQ_S1_Y2(y) (((y) >> 6) & 0xF)
227 #define REG_TXIQ_AB_S0 0x0cd0
228 #define BIT_MASK_TXIQ_A_S0 0x000007FE
229 #define BIT_MASK_TXIQ_A_EXT_S0 BIT(0)
230 #define BIT_MASK_TXIQ_B_S0 0x0007E000
231 #define REG_TXIQ_CD_S0 0x0cd4
232 #define BIT_MASK_TXIQ_C_S0 0x000007FE
233 #define BIT_MASK_TXIQ_C_EXT_S0 BIT(0)
234 #define BIT_MASK_TXIQ_D_S0 GENMASK(22, 13)
235 #define BIT_MASK_TXIQ_D_EXT_S0 BIT(12)
236 #define REG_RXIQ_AB_S0 0x0cd8
237 #define BIT_MASK_RXIQ_X_S0 0x000003FF
238 #define BIT_MASK_RXIQ_Y_S0 0x003FF000
239 #define REG_OFDM_FA_TYPE1_11N 0x0cf0
240 #define BIT_MASK_OFDM_FF_CNT GENMASK(15, 0)
241 #define BIT_MASK_OFDM_SF_CNT GENMASK(31, 16)
242 #define REG_OFDM_FA_RSTD_11N 0x0d00
243 #define BIT_MASK_OFDM_FA_RST1 BIT(27)
244 #define BIT_MASK_OFDM_FA_KEEP1 BIT(31)
245 #define REG_CTX 0x0d03
246 #define BIT_MASK_CTX_TYPE GENMASK(6, 4)
247 #define REG_OFDM1_CFOTRK 0x0d2c
248 #define BIT_EN_CFOTRK BIT(28)
249 #define REG_OFDM1_CSI1 0x0d40
250 #define REG_OFDM1_CSI2 0x0d44
251 #define REG_OFDM1_CSI3 0x0d48
252 #define REG_OFDM1_CSI4 0x0d4c
253 #define REG_OFDM_FA_TYPE2_11N 0x0da0
254 #define BIT_MASK_OFDM_CCA_CNT GENMASK(15, 0)
255 #define BIT_MASK_OFDM_PF_CNT GENMASK(31, 16)
256 #define REG_OFDM_FA_TYPE3_11N 0x0da4
257 #define BIT_MASK_OFDM_RI_CNT GENMASK(15, 0)
258 #define BIT_MASK_OFDM_CRC_CNT GENMASK(31, 16)
259 #define REG_OFDM_FA_TYPE4_11N 0x0da8
260 #define BIT_MASK_OFDM_MNS_CNT GENMASK(15, 0)
261 #define REG_FPGA0_IQK_11N 0x0e28
262 #define BIT_MASK_IQK_MOD 0xffffff00
263 #define EN_IQK 0x808000
264 #define RST_IQK 0x000000
265 #define REG_TXIQK_TONE_A_11N 0x0e30
266 #define REG_RXIQK_TONE_A_11N 0x0e34
267 #define REG_TXIQK_PI_A_11N 0x0e38
268 #define REG_RXIQK_PI_A_11N 0x0e3c
269 #define REG_TXIQK_11N 0x0e40
270 #define BIT_SET_TXIQK_11N(x, y) (0x80007C00 | ((x) << 16) | (y))
271 #define REG_RXIQK_11N 0x0e44
272 #define REG_IQK_AGC_PTS_11N 0x0e48
273 #define REG_IQK_AGC_RSP_11N 0x0e4c
274 #define REG_TX_IQK_TONE_B 0x0e50
275 #define REG_RX_IQK_TONE_B 0x0e54
276 #define REG_IQK_RES_TX 0x0e94
277 #define BIT_MASK_RES_TX GENMASK(25, 16)
278 #define REG_IQK_RES_TY 0x0e9c
279 #define BIT_MASK_RES_TY GENMASK(25, 16)
280 #define REG_IQK_RES_RX 0x0ea4
281 #define BIT_MASK_RES_RX GENMASK(25, 16)
282 #define REG_IQK_RES_RY 0x0eac
283 #define BIT_IQK_TX_FAIL BIT(28)
284 #define BIT_IQK_RX_FAIL BIT(27)
285 #define BIT_IQK_DONE BIT(26)
286 #define BIT_MASK_RES_RY GENMASK(25, 16)
287 #define REG_PAGE_F_RST_11N 0x0f14
288 #define BIT_MASK_F_RST_ALL BIT(16)
289 #define REG_IGI_C_11N 0x0f84
290 #define REG_IGI_D_11N 0x0f88
291 #define REG_HT_CRC32_CNT_11N 0x0f90
292 #define BIT_MASK_HT_CRC_OK GENMASK(15, 0)
293 #define BIT_MASK_HT_CRC_ERR GENMASK(31, 16)
294 #define REG_OFDM_CRC32_CNT_11N 0x0f94
295 #define BIT_MASK_OFDM_LCRC_OK GENMASK(15, 0)
296 #define BIT_MASK_OFDM_LCRC_ERR GENMASK(31, 16)
297 #define REG_HT_CRC32_CNT_11N_AGG 0x0fb8
298
299 #endif
300