1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2020 NXP.
4 *
5 * Author: Anson Huang <Anson.Huang@nxp.com>
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/err.h>
11 #include <linux/io.h>
12 #include <linux/module.h>
13 #include <linux/nvmem-consumer.h>
14 #include <linux/of.h>
15 #include <linux/of_device.h>
16 #include <linux/platform_device.h>
17 #include <linux/slab.h>
18 #include <linux/thermal.h>
19
20 #include "thermal_hwmon.h"
21
22 #define TER 0x0 /* TMU enable */
23 #define TPS 0x4
24 #define TRITSR 0x20 /* TMU immediate temp */
25 /* TMU calibration data registers */
26 #define TASR 0x28
27 #define TASR_BUF_SLOPE_MASK GENMASK(19, 16)
28 #define TASR_BUF_VREF_MASK GENMASK(4, 0) /* TMU_V1 */
29 #define TASR_BUF_VERF_SEL_MASK GENMASK(1, 0) /* TMU_V2 */
30 #define TCALIV(n) (0x30 + ((n) * 4))
31 #define TCALIV_EN BIT(31)
32 #define TCALIV_HR_MASK GENMASK(23, 16) /* TMU_V1 */
33 #define TCALIV_RT_MASK GENMASK(7, 0) /* TMU_V1 */
34 #define TCALIV_SNSR105C_MASK GENMASK(27, 16) /* TMU_V2 */
35 #define TCALIV_SNSR25C_MASK GENMASK(11, 0) /* TMU_V2 */
36 #define TRIM 0x3c
37 #define TRIM_BJT_CUR_MASK GENMASK(23, 20)
38 #define TRIM_BGR_MASK GENMASK(31, 28)
39 #define TRIM_VLSB_MASK GENMASK(15, 12)
40 #define TRIM_EN_CH BIT(7)
41
42 #define TER_ADC_PD BIT(30)
43 #define TER_EN BIT(31)
44 #define TRITSR_TEMP0_VAL_MASK GENMASK(7, 0)
45 #define TRITSR_TEMP1_VAL_MASK GENMASK(23, 16)
46
47 #define PROBE_SEL_ALL GENMASK(31, 30)
48
49 #define probe_status_offset(x) (30 + x)
50 #define SIGN_BIT BIT(7)
51 #define TEMP_VAL_MASK GENMASK(6, 0)
52
53 /* TMU OCOTP calibration data bitfields */
54 #define ANA0_EN BIT(25)
55 #define ANA0_BUF_VREF_MASK GENMASK(24, 20)
56 #define ANA0_BUF_SLOPE_MASK GENMASK(19, 16)
57 #define ANA0_HR_MASK GENMASK(15, 8)
58 #define ANA0_RT_MASK GENMASK(7, 0)
59 #define TRIM2_VLSB_MASK GENMASK(23, 20)
60 #define TRIM2_BGR_MASK GENMASK(19, 16)
61 #define TRIM2_BJT_CUR_MASK GENMASK(15, 12)
62 #define TRIM2_BUF_SLOP_SEL_MASK GENMASK(11, 8)
63 #define TRIM2_BUF_VERF_SEL_MASK GENMASK(7, 6)
64 #define TRIM3_TCA25_0_LSB_MASK GENMASK(31, 28)
65 #define TRIM3_TCA40_0_MASK GENMASK(27, 16)
66 #define TRIM4_TCA40_1_MASK GENMASK(31, 20)
67 #define TRIM4_TCA105_0_MASK GENMASK(19, 8)
68 #define TRIM4_TCA25_0_MSB_MASK GENMASK(7, 0)
69 #define TRIM5_TCA105_1_MASK GENMASK(23, 12)
70 #define TRIM5_TCA25_1_MASK GENMASK(11, 0)
71
72 #define VER1_TEMP_LOW_LIMIT 10000
73 #define VER2_TEMP_LOW_LIMIT -40000
74 #define VER2_TEMP_HIGH_LIMIT 125000
75
76 #define TMU_VER1 0x1
77 #define TMU_VER2 0x2
78
79 struct thermal_soc_data {
80 u32 num_sensors;
81 u32 version;
82 int (*get_temp)(void *, int *);
83 };
84
85 struct tmu_sensor {
86 struct imx8mm_tmu *priv;
87 u32 hw_id;
88 struct thermal_zone_device *tzd;
89 };
90
91 struct imx8mm_tmu {
92 void __iomem *base;
93 struct clk *clk;
94 const struct thermal_soc_data *socdata;
95 struct tmu_sensor sensors[];
96 };
97
imx8mm_tmu_get_temp(void * data,int * temp)98 static int imx8mm_tmu_get_temp(void *data, int *temp)
99 {
100 struct tmu_sensor *sensor = data;
101 struct imx8mm_tmu *tmu = sensor->priv;
102 u32 val;
103
104 val = readl_relaxed(tmu->base + TRITSR) & TRITSR_TEMP0_VAL_MASK;
105
106 /*
107 * Do not validate against the V bit (bit 31) due to errata
108 * ERR051272: TMU: Bit 31 of registers TMU_TSCR/TMU_TRITSR/TMU_TRATSR invalid
109 */
110
111 *temp = val * 1000;
112 if (*temp < VER1_TEMP_LOW_LIMIT || *temp > VER2_TEMP_HIGH_LIMIT)
113 return -EAGAIN;
114
115 return 0;
116 }
117
imx8mp_tmu_get_temp(void * data,int * temp)118 static int imx8mp_tmu_get_temp(void *data, int *temp)
119 {
120 struct tmu_sensor *sensor = data;
121 struct imx8mm_tmu *tmu = sensor->priv;
122 unsigned long val;
123 bool ready;
124
125 val = readl_relaxed(tmu->base + TRITSR);
126 ready = test_bit(probe_status_offset(sensor->hw_id), &val);
127 if (!ready)
128 return -EAGAIN;
129
130 val = sensor->hw_id ? FIELD_GET(TRITSR_TEMP1_VAL_MASK, val) :
131 FIELD_GET(TRITSR_TEMP0_VAL_MASK, val);
132 if (val & SIGN_BIT) /* negative */
133 val = (~(val & TEMP_VAL_MASK) + 1);
134
135 *temp = val * 1000;
136 if (*temp < VER2_TEMP_LOW_LIMIT || *temp > VER2_TEMP_HIGH_LIMIT)
137 return -EAGAIN;
138
139 return 0;
140 }
141
tmu_get_temp(struct thermal_zone_device * tz,int * temp)142 static int tmu_get_temp(struct thermal_zone_device *tz, int *temp)
143 {
144 struct tmu_sensor *sensor = tz->devdata;
145 struct imx8mm_tmu *tmu = sensor->priv;
146
147 return tmu->socdata->get_temp(sensor, temp);
148 }
149
150 static const struct thermal_zone_device_ops tmu_tz_ops = {
151 .get_temp = tmu_get_temp,
152 };
153
imx8mm_tmu_enable(struct imx8mm_tmu * tmu,bool enable)154 static void imx8mm_tmu_enable(struct imx8mm_tmu *tmu, bool enable)
155 {
156 u32 val;
157
158 val = readl_relaxed(tmu->base + TER);
159 val = enable ? (val | TER_EN) : (val & ~TER_EN);
160 if (tmu->socdata->version == TMU_VER2)
161 val = enable ? (val & ~TER_ADC_PD) : (val | TER_ADC_PD);
162 writel_relaxed(val, tmu->base + TER);
163 }
164
imx8mm_tmu_probe_sel_all(struct imx8mm_tmu * tmu)165 static void imx8mm_tmu_probe_sel_all(struct imx8mm_tmu *tmu)
166 {
167 u32 val;
168
169 val = readl_relaxed(tmu->base + TPS);
170 val |= PROBE_SEL_ALL;
171 writel_relaxed(val, tmu->base + TPS);
172 }
173
imx8mm_tmu_probe_set_calib_v1(struct platform_device * pdev,struct imx8mm_tmu * tmu)174 static int imx8mm_tmu_probe_set_calib_v1(struct platform_device *pdev,
175 struct imx8mm_tmu *tmu)
176 {
177 struct device *dev = &pdev->dev;
178 u32 ana0;
179 int ret;
180
181 ret = nvmem_cell_read_u32(&pdev->dev, "calib", &ana0);
182 if (ret) {
183 dev_warn(dev, "Failed to read OCOTP nvmem cell (%d).\n", ret);
184 return ret;
185 }
186
187 writel(FIELD_PREP(TASR_BUF_VREF_MASK,
188 FIELD_GET(ANA0_BUF_VREF_MASK, ana0)) |
189 FIELD_PREP(TASR_BUF_SLOPE_MASK,
190 FIELD_GET(ANA0_BUF_SLOPE_MASK, ana0)),
191 tmu->base + TASR);
192
193 writel(FIELD_PREP(TCALIV_RT_MASK, FIELD_GET(ANA0_RT_MASK, ana0)) |
194 FIELD_PREP(TCALIV_HR_MASK, FIELD_GET(ANA0_HR_MASK, ana0)) |
195 ((ana0 & ANA0_EN) ? TCALIV_EN : 0),
196 tmu->base + TCALIV(0));
197
198 return 0;
199 }
200
imx8mm_tmu_probe_set_calib_v2(struct platform_device * pdev,struct imx8mm_tmu * tmu)201 static int imx8mm_tmu_probe_set_calib_v2(struct platform_device *pdev,
202 struct imx8mm_tmu *tmu)
203 {
204 struct device *dev = &pdev->dev;
205 struct nvmem_cell *cell;
206 u32 trim[4] = { 0 };
207 size_t len;
208 void *buf;
209
210 cell = nvmem_cell_get(dev, "calib");
211 if (IS_ERR(cell))
212 return PTR_ERR(cell);
213
214 buf = nvmem_cell_read(cell, &len);
215 nvmem_cell_put(cell);
216
217 if (IS_ERR(buf))
218 return PTR_ERR(buf);
219
220 memcpy(trim, buf, min(len, sizeof(trim)));
221 kfree(buf);
222
223 if (len != 16) {
224 dev_err(dev,
225 "OCOTP nvmem cell length is %zu, must be 16.\n", len);
226 return -EINVAL;
227 }
228
229 /* Blank sample hardware */
230 if (!trim[0] && !trim[1] && !trim[2] && !trim[3]) {
231 /* Use a default 25C binary codes */
232 writel(FIELD_PREP(TCALIV_SNSR25C_MASK, 0x63c),
233 tmu->base + TCALIV(0));
234 writel(FIELD_PREP(TCALIV_SNSR25C_MASK, 0x63c),
235 tmu->base + TCALIV(1));
236 return 0;
237 }
238
239 writel(FIELD_PREP(TASR_BUF_VERF_SEL_MASK,
240 FIELD_GET(TRIM2_BUF_VERF_SEL_MASK, trim[0])) |
241 FIELD_PREP(TASR_BUF_SLOPE_MASK,
242 FIELD_GET(TRIM2_BUF_SLOP_SEL_MASK, trim[0])),
243 tmu->base + TASR);
244
245 writel(FIELD_PREP(TRIM_BJT_CUR_MASK,
246 FIELD_GET(TRIM2_BJT_CUR_MASK, trim[0])) |
247 FIELD_PREP(TRIM_BGR_MASK, FIELD_GET(TRIM2_BGR_MASK, trim[0])) |
248 FIELD_PREP(TRIM_VLSB_MASK, FIELD_GET(TRIM2_VLSB_MASK, trim[0])) |
249 TRIM_EN_CH,
250 tmu->base + TRIM);
251
252 writel(FIELD_PREP(TCALIV_SNSR25C_MASK,
253 FIELD_GET(TRIM3_TCA25_0_LSB_MASK, trim[1]) |
254 (FIELD_GET(TRIM4_TCA25_0_MSB_MASK, trim[2]) << 4)) |
255 FIELD_PREP(TCALIV_SNSR105C_MASK,
256 FIELD_GET(TRIM4_TCA105_0_MASK, trim[2])),
257 tmu->base + TCALIV(0));
258
259 writel(FIELD_PREP(TCALIV_SNSR25C_MASK,
260 FIELD_GET(TRIM5_TCA25_1_MASK, trim[3])) |
261 FIELD_PREP(TCALIV_SNSR105C_MASK,
262 FIELD_GET(TRIM5_TCA105_1_MASK, trim[3])),
263 tmu->base + TCALIV(1));
264
265 writel(FIELD_PREP(TCALIV_SNSR25C_MASK,
266 FIELD_GET(TRIM3_TCA40_0_MASK, trim[1])) |
267 FIELD_PREP(TCALIV_SNSR105C_MASK,
268 FIELD_GET(TRIM4_TCA40_1_MASK, trim[2])),
269 tmu->base + TCALIV(2));
270
271 return 0;
272 }
273
imx8mm_tmu_probe_set_calib(struct platform_device * pdev,struct imx8mm_tmu * tmu)274 static int imx8mm_tmu_probe_set_calib(struct platform_device *pdev,
275 struct imx8mm_tmu *tmu)
276 {
277 struct device *dev = &pdev->dev;
278
279 /*
280 * Lack of calibration data OCOTP reference is not considered
281 * fatal to retain compatibility with old DTs. It is however
282 * strongly recommended to update such old DTs to get correct
283 * temperature compensation values for each SoC.
284 */
285 if (!of_find_property(pdev->dev.of_node, "nvmem-cells", NULL)) {
286 dev_warn(dev,
287 "No OCOTP nvmem reference found, SoC-specific calibration not loaded. Please update your DT.\n");
288 return 0;
289 }
290
291 if (tmu->socdata->version == TMU_VER1)
292 return imx8mm_tmu_probe_set_calib_v1(pdev, tmu);
293
294 return imx8mm_tmu_probe_set_calib_v2(pdev, tmu);
295 }
296
imx8mm_tmu_probe(struct platform_device * pdev)297 static int imx8mm_tmu_probe(struct platform_device *pdev)
298 {
299 const struct thermal_soc_data *data;
300 struct imx8mm_tmu *tmu;
301 int ret;
302 int i;
303
304 data = of_device_get_match_data(&pdev->dev);
305
306 tmu = devm_kzalloc(&pdev->dev, struct_size(tmu, sensors,
307 data->num_sensors), GFP_KERNEL);
308 if (!tmu)
309 return -ENOMEM;
310
311 tmu->socdata = data;
312
313 tmu->base = devm_platform_ioremap_resource(pdev, 0);
314 if (IS_ERR(tmu->base))
315 return PTR_ERR(tmu->base);
316
317 tmu->clk = devm_clk_get(&pdev->dev, NULL);
318 if (IS_ERR(tmu->clk))
319 return dev_err_probe(&pdev->dev, PTR_ERR(tmu->clk),
320 "failed to get tmu clock\n");
321
322 ret = clk_prepare_enable(tmu->clk);
323 if (ret) {
324 dev_err(&pdev->dev, "failed to enable tmu clock: %d\n", ret);
325 return ret;
326 }
327
328 /* disable the monitor during initialization */
329 imx8mm_tmu_enable(tmu, false);
330
331 for (i = 0; i < data->num_sensors; i++) {
332 tmu->sensors[i].priv = tmu;
333 tmu->sensors[i].tzd =
334 devm_thermal_of_zone_register(&pdev->dev, i,
335 &tmu->sensors[i],
336 &tmu_tz_ops);
337 if (IS_ERR(tmu->sensors[i].tzd)) {
338 ret = PTR_ERR(tmu->sensors[i].tzd);
339 dev_err(&pdev->dev,
340 "failed to register thermal zone sensor[%d]: %d\n",
341 i, ret);
342 goto disable_clk;
343 }
344 tmu->sensors[i].hw_id = i;
345
346 if (devm_thermal_add_hwmon_sysfs(tmu->sensors[i].tzd))
347 dev_warn(&pdev->dev, "failed to add hwmon sysfs attributes\n");
348 }
349
350 platform_set_drvdata(pdev, tmu);
351
352 ret = imx8mm_tmu_probe_set_calib(pdev, tmu);
353 if (ret)
354 goto disable_clk;
355
356 /* enable all the probes for V2 TMU */
357 if (tmu->socdata->version == TMU_VER2)
358 imx8mm_tmu_probe_sel_all(tmu);
359
360 /* enable the monitor */
361 imx8mm_tmu_enable(tmu, true);
362
363 return 0;
364
365 disable_clk:
366 clk_disable_unprepare(tmu->clk);
367 return ret;
368 }
369
imx8mm_tmu_remove(struct platform_device * pdev)370 static int imx8mm_tmu_remove(struct platform_device *pdev)
371 {
372 struct imx8mm_tmu *tmu = platform_get_drvdata(pdev);
373
374 /* disable TMU */
375 imx8mm_tmu_enable(tmu, false);
376
377 clk_disable_unprepare(tmu->clk);
378 platform_set_drvdata(pdev, NULL);
379
380 return 0;
381 }
382
383 static struct thermal_soc_data imx8mm_tmu_data = {
384 .num_sensors = 1,
385 .version = TMU_VER1,
386 .get_temp = imx8mm_tmu_get_temp,
387 };
388
389 static struct thermal_soc_data imx8mp_tmu_data = {
390 .num_sensors = 2,
391 .version = TMU_VER2,
392 .get_temp = imx8mp_tmu_get_temp,
393 };
394
395 static const struct of_device_id imx8mm_tmu_table[] = {
396 { .compatible = "fsl,imx8mm-tmu", .data = &imx8mm_tmu_data, },
397 { .compatible = "fsl,imx8mp-tmu", .data = &imx8mp_tmu_data, },
398 { },
399 };
400 MODULE_DEVICE_TABLE(of, imx8mm_tmu_table);
401
402 static struct platform_driver imx8mm_tmu = {
403 .driver = {
404 .name = "i.mx8mm_thermal",
405 .of_match_table = imx8mm_tmu_table,
406 },
407 .probe = imx8mm_tmu_probe,
408 .remove = imx8mm_tmu_remove,
409 };
410 module_platform_driver(imx8mm_tmu);
411
412 MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
413 MODULE_DESCRIPTION("i.MX8MM Thermal Monitor Unit driver");
414 MODULE_LICENSE("GPL v2");
415