1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver core for Samsung SoC onboard UARTs.
4 *
5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
6 * http://armlinux.simtec.co.uk/
7 */
8
9 /* Note on 2410 error handling
10 *
11 * The s3c2410 manual has a love/hate affair with the contents of the
12 * UERSTAT register in the UART blocks, and keeps marking some of the
13 * error bits as reserved. Having checked with the s3c2410x01,
14 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
15 * feature from the latter versions of the manual.
16 *
17 * If it becomes aparrent that latter versions of the 2410 remove these
18 * bits, then action will have to be taken to differentiate the versions
19 * and change the policy on BREAK
20 *
21 * BJD, 04-Nov-2004
22 */
23
24 #include <linux/dmaengine.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/slab.h>
27 #include <linux/module.h>
28 #include <linux/ioport.h>
29 #include <linux/io.h>
30 #include <linux/platform_device.h>
31 #include <linux/init.h>
32 #include <linux/sysrq.h>
33 #include <linux/console.h>
34 #include <linux/tty.h>
35 #include <linux/tty_flip.h>
36 #include <linux/serial_core.h>
37 #include <linux/serial.h>
38 #include <linux/serial_s3c.h>
39 #include <linux/delay.h>
40 #include <linux/clk.h>
41 #include <linux/cpufreq.h>
42 #include <linux/of.h>
43 #include <asm/irq.h>
44
45 /* UART name and device definitions */
46
47 #define S3C24XX_SERIAL_NAME "ttySAC"
48 #define S3C24XX_SERIAL_MAJOR 204
49 #define S3C24XX_SERIAL_MINOR 64
50
51 #ifdef CONFIG_ARM64
52 #define UART_NR 12
53 #else
54 #define UART_NR CONFIG_SERIAL_SAMSUNG_UARTS
55 #endif
56
57 #define S3C24XX_TX_PIO 1
58 #define S3C24XX_TX_DMA 2
59 #define S3C24XX_RX_PIO 1
60 #define S3C24XX_RX_DMA 2
61
62 /* flag to ignore all characters coming in */
63 #define RXSTAT_DUMMY_READ (0x10000000)
64
65 enum s3c24xx_port_type {
66 TYPE_S3C24XX,
67 TYPE_S3C6400,
68 TYPE_APPLE_S5L,
69 };
70
71 struct s3c24xx_uart_info {
72 const char *name;
73 enum s3c24xx_port_type type;
74 unsigned int port_type;
75 unsigned int fifosize;
76 unsigned long rx_fifomask;
77 unsigned long rx_fifoshift;
78 unsigned long rx_fifofull;
79 unsigned long tx_fifomask;
80 unsigned long tx_fifoshift;
81 unsigned long tx_fifofull;
82 unsigned int def_clk_sel;
83 unsigned long num_clks;
84 unsigned long clksel_mask;
85 unsigned long clksel_shift;
86 unsigned long ucon_mask;
87
88 /* uart port features */
89
90 unsigned int has_divslot:1;
91 };
92
93 struct s3c24xx_serial_drv_data {
94 const struct s3c24xx_uart_info info;
95 const struct s3c2410_uartcfg def_cfg;
96 const unsigned int fifosize[UART_NR];
97 };
98
99 struct s3c24xx_uart_dma {
100 unsigned int rx_chan_id;
101 unsigned int tx_chan_id;
102
103 struct dma_slave_config rx_conf;
104 struct dma_slave_config tx_conf;
105
106 struct dma_chan *rx_chan;
107 struct dma_chan *tx_chan;
108
109 dma_addr_t rx_addr;
110 dma_addr_t tx_addr;
111
112 dma_cookie_t rx_cookie;
113 dma_cookie_t tx_cookie;
114
115 char *rx_buf;
116
117 dma_addr_t tx_transfer_addr;
118
119 size_t rx_size;
120 size_t tx_size;
121
122 struct dma_async_tx_descriptor *tx_desc;
123 struct dma_async_tx_descriptor *rx_desc;
124
125 int tx_bytes_requested;
126 int rx_bytes_requested;
127 };
128
129 struct s3c24xx_uart_port {
130 unsigned char rx_claimed;
131 unsigned char tx_claimed;
132 unsigned char rx_enabled;
133 unsigned char tx_enabled;
134 unsigned int pm_level;
135 unsigned long baudclk_rate;
136 unsigned int min_dma_size;
137
138 unsigned int rx_irq;
139 unsigned int tx_irq;
140
141 unsigned int tx_in_progress;
142 unsigned int tx_mode;
143 unsigned int rx_mode;
144
145 const struct s3c24xx_uart_info *info;
146 struct clk *clk;
147 struct clk *baudclk;
148 struct uart_port port;
149 const struct s3c24xx_serial_drv_data *drv_data;
150
151 /* reference to platform data */
152 const struct s3c2410_uartcfg *cfg;
153
154 struct s3c24xx_uart_dma *dma;
155 };
156
157 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport);
158
159 /* conversion functions */
160
161 #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
162
163 /* register access controls */
164
165 #define portaddr(port, reg) ((port)->membase + (reg))
166 #define portaddrl(port, reg) \
167 ((unsigned long *)(unsigned long)((port)->membase + (reg)))
168
rd_reg(const struct uart_port * port,u32 reg)169 static u32 rd_reg(const struct uart_port *port, u32 reg)
170 {
171 switch (port->iotype) {
172 case UPIO_MEM:
173 return readb_relaxed(portaddr(port, reg));
174 case UPIO_MEM32:
175 return readl_relaxed(portaddr(port, reg));
176 default:
177 return 0;
178 }
179 return 0;
180 }
181
182 #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
183
wr_reg(const struct uart_port * port,u32 reg,u32 val)184 static void wr_reg(const struct uart_port *port, u32 reg, u32 val)
185 {
186 switch (port->iotype) {
187 case UPIO_MEM:
188 writeb_relaxed(val, portaddr(port, reg));
189 break;
190 case UPIO_MEM32:
191 writel_relaxed(val, portaddr(port, reg));
192 break;
193 }
194 }
195
196 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
197
198 /* Byte-order aware bit setting/clearing functions. */
199
s3c24xx_set_bit(const struct uart_port * port,int idx,unsigned int reg)200 static inline void s3c24xx_set_bit(const struct uart_port *port, int idx,
201 unsigned int reg)
202 {
203 unsigned long flags;
204 u32 val;
205
206 local_irq_save(flags);
207 val = rd_regl(port, reg);
208 val |= (1 << idx);
209 wr_regl(port, reg, val);
210 local_irq_restore(flags);
211 }
212
s3c24xx_clear_bit(const struct uart_port * port,int idx,unsigned int reg)213 static inline void s3c24xx_clear_bit(const struct uart_port *port, int idx,
214 unsigned int reg)
215 {
216 unsigned long flags;
217 u32 val;
218
219 local_irq_save(flags);
220 val = rd_regl(port, reg);
221 val &= ~(1 << idx);
222 wr_regl(port, reg, val);
223 local_irq_restore(flags);
224 }
225
to_ourport(struct uart_port * port)226 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
227 {
228 return container_of(port, struct s3c24xx_uart_port, port);
229 }
230
231 /* translate a port to the device name */
232
s3c24xx_serial_portname(const struct uart_port * port)233 static inline const char *s3c24xx_serial_portname(const struct uart_port *port)
234 {
235 return to_platform_device(port->dev)->name;
236 }
237
s3c24xx_serial_txempty_nofifo(const struct uart_port * port)238 static int s3c24xx_serial_txempty_nofifo(const struct uart_port *port)
239 {
240 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
241 }
242
s3c24xx_serial_rx_enable(struct uart_port * port)243 static void s3c24xx_serial_rx_enable(struct uart_port *port)
244 {
245 struct s3c24xx_uart_port *ourport = to_ourport(port);
246 unsigned long flags;
247 unsigned int ucon, ufcon;
248 int count = 10000;
249
250 spin_lock_irqsave(&port->lock, flags);
251
252 while (--count && !s3c24xx_serial_txempty_nofifo(port))
253 udelay(100);
254
255 ufcon = rd_regl(port, S3C2410_UFCON);
256 ufcon |= S3C2410_UFCON_RESETRX;
257 wr_regl(port, S3C2410_UFCON, ufcon);
258
259 ucon = rd_regl(port, S3C2410_UCON);
260 ucon |= S3C2410_UCON_RXIRQMODE;
261 wr_regl(port, S3C2410_UCON, ucon);
262
263 ourport->rx_enabled = 1;
264 spin_unlock_irqrestore(&port->lock, flags);
265 }
266
s3c24xx_serial_rx_disable(struct uart_port * port)267 static void s3c24xx_serial_rx_disable(struct uart_port *port)
268 {
269 struct s3c24xx_uart_port *ourport = to_ourport(port);
270 unsigned long flags;
271 unsigned int ucon;
272
273 spin_lock_irqsave(&port->lock, flags);
274
275 ucon = rd_regl(port, S3C2410_UCON);
276 ucon &= ~S3C2410_UCON_RXIRQMODE;
277 wr_regl(port, S3C2410_UCON, ucon);
278
279 ourport->rx_enabled = 0;
280 spin_unlock_irqrestore(&port->lock, flags);
281 }
282
s3c24xx_serial_stop_tx(struct uart_port * port)283 static void s3c24xx_serial_stop_tx(struct uart_port *port)
284 {
285 struct s3c24xx_uart_port *ourport = to_ourport(port);
286 struct s3c24xx_uart_dma *dma = ourport->dma;
287 struct dma_tx_state state;
288 int count;
289
290 if (!ourport->tx_enabled)
291 return;
292
293 switch (ourport->info->type) {
294 case TYPE_S3C6400:
295 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
296 break;
297 case TYPE_APPLE_S5L:
298 s3c24xx_clear_bit(port, APPLE_S5L_UCON_TXTHRESH_ENA, S3C2410_UCON);
299 break;
300 default:
301 disable_irq_nosync(ourport->tx_irq);
302 break;
303 }
304
305 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
306 dmaengine_pause(dma->tx_chan);
307 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
308 dmaengine_terminate_all(dma->tx_chan);
309 dma_sync_single_for_cpu(dma->tx_chan->device->dev,
310 dma->tx_transfer_addr, dma->tx_size,
311 DMA_TO_DEVICE);
312 async_tx_ack(dma->tx_desc);
313 count = dma->tx_bytes_requested - state.residue;
314 uart_xmit_advance(port, count);
315 }
316
317 ourport->tx_enabled = 0;
318 ourport->tx_in_progress = 0;
319
320 if (port->flags & UPF_CONS_FLOW)
321 s3c24xx_serial_rx_enable(port);
322
323 ourport->tx_mode = 0;
324 }
325
326 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
327
s3c24xx_serial_tx_dma_complete(void * args)328 static void s3c24xx_serial_tx_dma_complete(void *args)
329 {
330 struct s3c24xx_uart_port *ourport = args;
331 struct uart_port *port = &ourport->port;
332 struct circ_buf *xmit = &port->state->xmit;
333 struct s3c24xx_uart_dma *dma = ourport->dma;
334 struct dma_tx_state state;
335 unsigned long flags;
336 int count;
337
338 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
339 count = dma->tx_bytes_requested - state.residue;
340 async_tx_ack(dma->tx_desc);
341
342 dma_sync_single_for_cpu(dma->tx_chan->device->dev,
343 dma->tx_transfer_addr, dma->tx_size,
344 DMA_TO_DEVICE);
345
346 spin_lock_irqsave(&port->lock, flags);
347
348 uart_xmit_advance(port, count);
349 ourport->tx_in_progress = 0;
350
351 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
352 uart_write_wakeup(port);
353
354 s3c24xx_serial_start_next_tx(ourport);
355 spin_unlock_irqrestore(&port->lock, flags);
356 }
357
enable_tx_dma(struct s3c24xx_uart_port * ourport)358 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
359 {
360 const struct uart_port *port = &ourport->port;
361 u32 ucon;
362
363 /* Mask Tx interrupt */
364 switch (ourport->info->type) {
365 case TYPE_S3C6400:
366 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
367 break;
368 case TYPE_APPLE_S5L:
369 WARN_ON(1); // No DMA
370 break;
371 default:
372 disable_irq_nosync(ourport->tx_irq);
373 break;
374 }
375
376 /* Enable tx dma mode */
377 ucon = rd_regl(port, S3C2410_UCON);
378 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
379 ucon |= S3C64XX_UCON_TXBURST_1;
380 ucon |= S3C64XX_UCON_TXMODE_DMA;
381 wr_regl(port, S3C2410_UCON, ucon);
382
383 ourport->tx_mode = S3C24XX_TX_DMA;
384 }
385
enable_tx_pio(struct s3c24xx_uart_port * ourport)386 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
387 {
388 const struct uart_port *port = &ourport->port;
389 u32 ucon, ufcon;
390
391 /* Set ufcon txtrig */
392 ourport->tx_in_progress = S3C24XX_TX_PIO;
393 ufcon = rd_regl(port, S3C2410_UFCON);
394 wr_regl(port, S3C2410_UFCON, ufcon);
395
396 /* Enable tx pio mode */
397 ucon = rd_regl(port, S3C2410_UCON);
398 ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
399 ucon |= S3C64XX_UCON_TXMODE_CPU;
400 wr_regl(port, S3C2410_UCON, ucon);
401
402 /* Unmask Tx interrupt */
403 switch (ourport->info->type) {
404 case TYPE_S3C6400:
405 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
406 S3C64XX_UINTM);
407 break;
408 case TYPE_APPLE_S5L:
409 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
410 wr_regl(port, S3C2410_UCON, ucon);
411 break;
412 default:
413 enable_irq(ourport->tx_irq);
414 break;
415 }
416
417 ourport->tx_mode = S3C24XX_TX_PIO;
418
419 /*
420 * The Apple version only has edge triggered TX IRQs, so we need
421 * to kick off the process by sending some characters here.
422 */
423 if (ourport->info->type == TYPE_APPLE_S5L)
424 s3c24xx_serial_tx_chars(ourport);
425 }
426
s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port * ourport)427 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
428 {
429 if (ourport->tx_mode != S3C24XX_TX_PIO)
430 enable_tx_pio(ourport);
431 }
432
s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port * ourport,unsigned int count)433 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
434 unsigned int count)
435 {
436 struct uart_port *port = &ourport->port;
437 struct circ_buf *xmit = &port->state->xmit;
438 struct s3c24xx_uart_dma *dma = ourport->dma;
439
440 if (ourport->tx_mode != S3C24XX_TX_DMA)
441 enable_tx_dma(ourport);
442
443 dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
444 dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
445
446 dma_sync_single_for_device(dma->tx_chan->device->dev,
447 dma->tx_transfer_addr, dma->tx_size,
448 DMA_TO_DEVICE);
449
450 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
451 dma->tx_transfer_addr, dma->tx_size,
452 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
453 if (!dma->tx_desc) {
454 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
455 return -EIO;
456 }
457
458 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
459 dma->tx_desc->callback_param = ourport;
460 dma->tx_bytes_requested = dma->tx_size;
461
462 ourport->tx_in_progress = S3C24XX_TX_DMA;
463 dma->tx_cookie = dmaengine_submit(dma->tx_desc);
464 dma_async_issue_pending(dma->tx_chan);
465 return 0;
466 }
467
s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port * ourport)468 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
469 {
470 struct uart_port *port = &ourport->port;
471 struct circ_buf *xmit = &port->state->xmit;
472 unsigned long count;
473
474 /* Get data size up to the end of buffer */
475 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
476
477 if (!count) {
478 s3c24xx_serial_stop_tx(port);
479 return;
480 }
481
482 if (!ourport->dma || !ourport->dma->tx_chan ||
483 count < ourport->min_dma_size ||
484 xmit->tail & (dma_get_cache_alignment() - 1))
485 s3c24xx_serial_start_tx_pio(ourport);
486 else
487 s3c24xx_serial_start_tx_dma(ourport, count);
488 }
489
s3c24xx_serial_start_tx(struct uart_port * port)490 static void s3c24xx_serial_start_tx(struct uart_port *port)
491 {
492 struct s3c24xx_uart_port *ourport = to_ourport(port);
493 struct circ_buf *xmit = &port->state->xmit;
494
495 if (!ourport->tx_enabled) {
496 if (port->flags & UPF_CONS_FLOW)
497 s3c24xx_serial_rx_disable(port);
498
499 ourport->tx_enabled = 1;
500 if (!ourport->dma || !ourport->dma->tx_chan)
501 s3c24xx_serial_start_tx_pio(ourport);
502 }
503
504 if (ourport->dma && ourport->dma->tx_chan) {
505 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
506 s3c24xx_serial_start_next_tx(ourport);
507 }
508 }
509
s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port * ourport,struct tty_port * tty,int count)510 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
511 struct tty_port *tty, int count)
512 {
513 struct s3c24xx_uart_dma *dma = ourport->dma;
514 int copied;
515
516 if (!count)
517 return;
518
519 dma_sync_single_for_cpu(dma->rx_chan->device->dev, dma->rx_addr,
520 dma->rx_size, DMA_FROM_DEVICE);
521
522 ourport->port.icount.rx += count;
523 if (!tty) {
524 dev_err(ourport->port.dev, "No tty port\n");
525 return;
526 }
527 copied = tty_insert_flip_string(tty,
528 ((unsigned char *)(ourport->dma->rx_buf)), count);
529 if (copied != count) {
530 WARN_ON(1);
531 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
532 }
533 }
534
s3c24xx_serial_stop_rx(struct uart_port * port)535 static void s3c24xx_serial_stop_rx(struct uart_port *port)
536 {
537 struct s3c24xx_uart_port *ourport = to_ourport(port);
538 struct s3c24xx_uart_dma *dma = ourport->dma;
539 struct tty_port *t = &port->state->port;
540 struct dma_tx_state state;
541 enum dma_status dma_status;
542 unsigned int received;
543
544 if (ourport->rx_enabled) {
545 dev_dbg(port->dev, "stopping rx\n");
546 switch (ourport->info->type) {
547 case TYPE_S3C6400:
548 s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
549 S3C64XX_UINTM);
550 break;
551 case TYPE_APPLE_S5L:
552 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
553 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
554 break;
555 default:
556 disable_irq_nosync(ourport->rx_irq);
557 break;
558 }
559 ourport->rx_enabled = 0;
560 }
561 if (dma && dma->rx_chan) {
562 dmaengine_pause(dma->tx_chan);
563 dma_status = dmaengine_tx_status(dma->rx_chan,
564 dma->rx_cookie, &state);
565 if (dma_status == DMA_IN_PROGRESS ||
566 dma_status == DMA_PAUSED) {
567 received = dma->rx_bytes_requested - state.residue;
568 dmaengine_terminate_all(dma->rx_chan);
569 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
570 }
571 }
572 }
573
574 static inline const struct s3c24xx_uart_info
s3c24xx_port_to_info(struct uart_port * port)575 *s3c24xx_port_to_info(struct uart_port *port)
576 {
577 return to_ourport(port)->info;
578 }
579
580 static inline const struct s3c2410_uartcfg
s3c24xx_port_to_cfg(const struct uart_port * port)581 *s3c24xx_port_to_cfg(const struct uart_port *port)
582 {
583 const struct s3c24xx_uart_port *ourport;
584
585 if (port->dev == NULL)
586 return NULL;
587
588 ourport = container_of(port, struct s3c24xx_uart_port, port);
589 return ourport->cfg;
590 }
591
s3c24xx_serial_rx_fifocnt(const struct s3c24xx_uart_port * ourport,unsigned long ufstat)592 static int s3c24xx_serial_rx_fifocnt(const struct s3c24xx_uart_port *ourport,
593 unsigned long ufstat)
594 {
595 const struct s3c24xx_uart_info *info = ourport->info;
596
597 if (ufstat & info->rx_fifofull)
598 return ourport->port.fifosize;
599
600 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
601 }
602
603 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
s3c24xx_serial_rx_dma_complete(void * args)604 static void s3c24xx_serial_rx_dma_complete(void *args)
605 {
606 struct s3c24xx_uart_port *ourport = args;
607 struct uart_port *port = &ourport->port;
608
609 struct s3c24xx_uart_dma *dma = ourport->dma;
610 struct tty_port *t = &port->state->port;
611 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
612
613 struct dma_tx_state state;
614 unsigned long flags;
615 int received;
616
617 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
618 received = dma->rx_bytes_requested - state.residue;
619 async_tx_ack(dma->rx_desc);
620
621 spin_lock_irqsave(&port->lock, flags);
622
623 if (received)
624 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
625
626 if (tty) {
627 tty_flip_buffer_push(t);
628 tty_kref_put(tty);
629 }
630
631 s3c64xx_start_rx_dma(ourport);
632
633 spin_unlock_irqrestore(&port->lock, flags);
634 }
635
s3c64xx_start_rx_dma(struct s3c24xx_uart_port * ourport)636 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
637 {
638 struct s3c24xx_uart_dma *dma = ourport->dma;
639
640 dma_sync_single_for_device(dma->rx_chan->device->dev, dma->rx_addr,
641 dma->rx_size, DMA_FROM_DEVICE);
642
643 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
644 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
645 DMA_PREP_INTERRUPT);
646 if (!dma->rx_desc) {
647 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
648 return;
649 }
650
651 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
652 dma->rx_desc->callback_param = ourport;
653 dma->rx_bytes_requested = dma->rx_size;
654
655 dma->rx_cookie = dmaengine_submit(dma->rx_desc);
656 dma_async_issue_pending(dma->rx_chan);
657 }
658
659 /* ? - where has parity gone?? */
660 #define S3C2410_UERSTAT_PARITY (0x1000)
661
enable_rx_dma(struct s3c24xx_uart_port * ourport)662 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
663 {
664 struct uart_port *port = &ourport->port;
665 unsigned int ucon;
666
667 /* set Rx mode to DMA mode */
668 ucon = rd_regl(port, S3C2410_UCON);
669 ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
670 S3C64XX_UCON_TIMEOUT_MASK |
671 S3C64XX_UCON_EMPTYINT_EN |
672 S3C64XX_UCON_DMASUS_EN |
673 S3C64XX_UCON_TIMEOUT_EN |
674 S3C64XX_UCON_RXMODE_MASK);
675 ucon |= S3C64XX_UCON_RXBURST_1 |
676 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
677 S3C64XX_UCON_EMPTYINT_EN |
678 S3C64XX_UCON_TIMEOUT_EN |
679 S3C64XX_UCON_RXMODE_DMA;
680 wr_regl(port, S3C2410_UCON, ucon);
681
682 ourport->rx_mode = S3C24XX_RX_DMA;
683 }
684
enable_rx_pio(struct s3c24xx_uart_port * ourport)685 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
686 {
687 struct uart_port *port = &ourport->port;
688 unsigned int ucon;
689
690 /* set Rx mode to DMA mode */
691 ucon = rd_regl(port, S3C2410_UCON);
692 ucon &= ~S3C64XX_UCON_RXMODE_MASK;
693 ucon |= S3C64XX_UCON_RXMODE_CPU;
694
695 /* Apple types use these bits for IRQ masks */
696 if (ourport->info->type != TYPE_APPLE_S5L) {
697 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
698 S3C64XX_UCON_EMPTYINT_EN |
699 S3C64XX_UCON_DMASUS_EN |
700 S3C64XX_UCON_TIMEOUT_EN);
701 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
702 S3C64XX_UCON_TIMEOUT_EN;
703 }
704 wr_regl(port, S3C2410_UCON, ucon);
705
706 ourport->rx_mode = S3C24XX_RX_PIO;
707 }
708
709 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
710
s3c24xx_serial_rx_chars_dma(void * dev_id)711 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
712 {
713 unsigned int utrstat, received;
714 struct s3c24xx_uart_port *ourport = dev_id;
715 struct uart_port *port = &ourport->port;
716 struct s3c24xx_uart_dma *dma = ourport->dma;
717 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
718 struct tty_port *t = &port->state->port;
719 struct dma_tx_state state;
720
721 utrstat = rd_regl(port, S3C2410_UTRSTAT);
722 rd_regl(port, S3C2410_UFSTAT);
723
724 spin_lock(&port->lock);
725
726 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
727 s3c64xx_start_rx_dma(ourport);
728 if (ourport->rx_mode == S3C24XX_RX_PIO)
729 enable_rx_dma(ourport);
730 goto finish;
731 }
732
733 if (ourport->rx_mode == S3C24XX_RX_DMA) {
734 dmaengine_pause(dma->rx_chan);
735 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
736 dmaengine_terminate_all(dma->rx_chan);
737 received = dma->rx_bytes_requested - state.residue;
738 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
739
740 enable_rx_pio(ourport);
741 }
742
743 s3c24xx_serial_rx_drain_fifo(ourport);
744
745 if (tty) {
746 tty_flip_buffer_push(t);
747 tty_kref_put(tty);
748 }
749
750 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
751
752 finish:
753 spin_unlock(&port->lock);
754
755 return IRQ_HANDLED;
756 }
757
s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port * ourport)758 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
759 {
760 struct uart_port *port = &ourport->port;
761 unsigned int ufcon, ch, flag, ufstat, uerstat;
762 unsigned int fifocnt = 0;
763 int max_count = port->fifosize;
764
765 while (max_count-- > 0) {
766 /*
767 * Receive all characters known to be in FIFO
768 * before reading FIFO level again
769 */
770 if (fifocnt == 0) {
771 ufstat = rd_regl(port, S3C2410_UFSTAT);
772 fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
773 if (fifocnt == 0)
774 break;
775 }
776 fifocnt--;
777
778 uerstat = rd_regl(port, S3C2410_UERSTAT);
779 ch = rd_reg(port, S3C2410_URXH);
780
781 if (port->flags & UPF_CONS_FLOW) {
782 int txe = s3c24xx_serial_txempty_nofifo(port);
783
784 if (ourport->rx_enabled) {
785 if (!txe) {
786 ourport->rx_enabled = 0;
787 continue;
788 }
789 } else {
790 if (txe) {
791 ufcon = rd_regl(port, S3C2410_UFCON);
792 ufcon |= S3C2410_UFCON_RESETRX;
793 wr_regl(port, S3C2410_UFCON, ufcon);
794 ourport->rx_enabled = 1;
795 return;
796 }
797 continue;
798 }
799 }
800
801 /* insert the character into the buffer */
802
803 flag = TTY_NORMAL;
804 port->icount.rx++;
805
806 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
807 dev_dbg(port->dev,
808 "rxerr: port ch=0x%02x, rxs=0x%08x\n",
809 ch, uerstat);
810
811 /* check for break */
812 if (uerstat & S3C2410_UERSTAT_BREAK) {
813 dev_dbg(port->dev, "break!\n");
814 port->icount.brk++;
815 if (uart_handle_break(port))
816 continue; /* Ignore character */
817 }
818
819 if (uerstat & S3C2410_UERSTAT_FRAME)
820 port->icount.frame++;
821 if (uerstat & S3C2410_UERSTAT_OVERRUN)
822 port->icount.overrun++;
823
824 uerstat &= port->read_status_mask;
825
826 if (uerstat & S3C2410_UERSTAT_BREAK)
827 flag = TTY_BREAK;
828 else if (uerstat & S3C2410_UERSTAT_PARITY)
829 flag = TTY_PARITY;
830 else if (uerstat & (S3C2410_UERSTAT_FRAME |
831 S3C2410_UERSTAT_OVERRUN))
832 flag = TTY_FRAME;
833 }
834
835 if (uart_handle_sysrq_char(port, ch))
836 continue; /* Ignore character */
837
838 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
839 ch, flag);
840 }
841
842 tty_flip_buffer_push(&port->state->port);
843 }
844
s3c24xx_serial_rx_chars_pio(void * dev_id)845 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
846 {
847 struct s3c24xx_uart_port *ourport = dev_id;
848 struct uart_port *port = &ourport->port;
849
850 spin_lock(&port->lock);
851 s3c24xx_serial_rx_drain_fifo(ourport);
852 spin_unlock(&port->lock);
853
854 return IRQ_HANDLED;
855 }
856
s3c24xx_serial_rx_irq(int irq,void * dev_id)857 static irqreturn_t s3c24xx_serial_rx_irq(int irq, void *dev_id)
858 {
859 struct s3c24xx_uart_port *ourport = dev_id;
860
861 if (ourport->dma && ourport->dma->rx_chan)
862 return s3c24xx_serial_rx_chars_dma(dev_id);
863 return s3c24xx_serial_rx_chars_pio(dev_id);
864 }
865
s3c24xx_serial_tx_chars(struct s3c24xx_uart_port * ourport)866 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport)
867 {
868 struct uart_port *port = &ourport->port;
869 struct circ_buf *xmit = &port->state->xmit;
870 int count, dma_count = 0;
871
872 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
873
874 if (ourport->dma && ourport->dma->tx_chan &&
875 count >= ourport->min_dma_size) {
876 int align = dma_get_cache_alignment() -
877 (xmit->tail & (dma_get_cache_alignment() - 1));
878 if (count - align >= ourport->min_dma_size) {
879 dma_count = count - align;
880 count = align;
881 }
882 }
883
884 if (port->x_char) {
885 wr_reg(port, S3C2410_UTXH, port->x_char);
886 port->icount.tx++;
887 port->x_char = 0;
888 return;
889 }
890
891 /* if there isn't anything more to transmit, or the uart is now
892 * stopped, disable the uart and exit
893 */
894
895 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
896 s3c24xx_serial_stop_tx(port);
897 return;
898 }
899
900 /* try and drain the buffer... */
901
902 if (count > port->fifosize) {
903 count = port->fifosize;
904 dma_count = 0;
905 }
906
907 while (!uart_circ_empty(xmit) && count > 0) {
908 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
909 break;
910
911 wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
912 uart_xmit_advance(port, 1);
913 count--;
914 }
915
916 if (!count && dma_count) {
917 s3c24xx_serial_start_tx_dma(ourport, dma_count);
918 return;
919 }
920
921 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
922 uart_write_wakeup(port);
923
924 if (uart_circ_empty(xmit))
925 s3c24xx_serial_stop_tx(port);
926 }
927
s3c24xx_serial_tx_irq(int irq,void * id)928 static irqreturn_t s3c24xx_serial_tx_irq(int irq, void *id)
929 {
930 struct s3c24xx_uart_port *ourport = id;
931 struct uart_port *port = &ourport->port;
932
933 spin_lock(&port->lock);
934
935 s3c24xx_serial_tx_chars(ourport);
936
937 spin_unlock(&port->lock);
938 return IRQ_HANDLED;
939 }
940
941 /* interrupt handler for s3c64xx and later SoC's.*/
s3c64xx_serial_handle_irq(int irq,void * id)942 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
943 {
944 const struct s3c24xx_uart_port *ourport = id;
945 const struct uart_port *port = &ourport->port;
946 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
947 irqreturn_t ret = IRQ_HANDLED;
948
949 if (pend & S3C64XX_UINTM_RXD_MSK) {
950 ret = s3c24xx_serial_rx_irq(irq, id);
951 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
952 }
953 if (pend & S3C64XX_UINTM_TXD_MSK) {
954 ret = s3c24xx_serial_tx_irq(irq, id);
955 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
956 }
957 return ret;
958 }
959
960 /* interrupt handler for Apple SoC's.*/
apple_serial_handle_irq(int irq,void * id)961 static irqreturn_t apple_serial_handle_irq(int irq, void *id)
962 {
963 const struct s3c24xx_uart_port *ourport = id;
964 const struct uart_port *port = &ourport->port;
965 unsigned int pend = rd_regl(port, S3C2410_UTRSTAT);
966 irqreturn_t ret = IRQ_NONE;
967
968 if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO)) {
969 wr_regl(port, S3C2410_UTRSTAT,
970 APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO);
971 ret = s3c24xx_serial_rx_irq(irq, id);
972 }
973 if (pend & APPLE_S5L_UTRSTAT_TXTHRESH) {
974 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_TXTHRESH);
975 ret = s3c24xx_serial_tx_irq(irq, id);
976 }
977
978 return ret;
979 }
980
s3c24xx_serial_tx_empty(struct uart_port * port)981 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
982 {
983 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
984 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
985 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
986
987 if (ufcon & S3C2410_UFCON_FIFOMODE) {
988 if ((ufstat & info->tx_fifomask) != 0 ||
989 (ufstat & info->tx_fifofull))
990 return 0;
991
992 return 1;
993 }
994
995 return s3c24xx_serial_txempty_nofifo(port);
996 }
997
998 /* no modem control lines */
s3c24xx_serial_get_mctrl(struct uart_port * port)999 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
1000 {
1001 unsigned int umstat = rd_reg(port, S3C2410_UMSTAT);
1002
1003 if (umstat & S3C2410_UMSTAT_CTS)
1004 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
1005 else
1006 return TIOCM_CAR | TIOCM_DSR;
1007 }
1008
s3c24xx_serial_set_mctrl(struct uart_port * port,unsigned int mctrl)1009 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
1010 {
1011 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
1012 unsigned int ucon = rd_regl(port, S3C2410_UCON);
1013
1014 if (mctrl & TIOCM_RTS)
1015 umcon |= S3C2410_UMCOM_RTS_LOW;
1016 else
1017 umcon &= ~S3C2410_UMCOM_RTS_LOW;
1018
1019 wr_regl(port, S3C2410_UMCON, umcon);
1020
1021 if (mctrl & TIOCM_LOOP)
1022 ucon |= S3C2410_UCON_LOOPBACK;
1023 else
1024 ucon &= ~S3C2410_UCON_LOOPBACK;
1025
1026 wr_regl(port, S3C2410_UCON, ucon);
1027 }
1028
s3c24xx_serial_break_ctl(struct uart_port * port,int break_state)1029 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
1030 {
1031 unsigned long flags;
1032 unsigned int ucon;
1033
1034 spin_lock_irqsave(&port->lock, flags);
1035
1036 ucon = rd_regl(port, S3C2410_UCON);
1037
1038 if (break_state)
1039 ucon |= S3C2410_UCON_SBREAK;
1040 else
1041 ucon &= ~S3C2410_UCON_SBREAK;
1042
1043 wr_regl(port, S3C2410_UCON, ucon);
1044
1045 spin_unlock_irqrestore(&port->lock, flags);
1046 }
1047
s3c24xx_serial_request_dma(struct s3c24xx_uart_port * p)1048 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
1049 {
1050 struct s3c24xx_uart_dma *dma = p->dma;
1051 struct dma_slave_caps dma_caps;
1052 const char *reason = NULL;
1053 int ret;
1054
1055 /* Default slave configuration parameters */
1056 dma->rx_conf.direction = DMA_DEV_TO_MEM;
1057 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1058 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH;
1059 dma->rx_conf.src_maxburst = 1;
1060
1061 dma->tx_conf.direction = DMA_MEM_TO_DEV;
1062 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1063 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH;
1064 dma->tx_conf.dst_maxburst = 1;
1065
1066 dma->rx_chan = dma_request_chan(p->port.dev, "rx");
1067
1068 if (IS_ERR(dma->rx_chan)) {
1069 reason = "DMA RX channel request failed";
1070 ret = PTR_ERR(dma->rx_chan);
1071 goto err_warn;
1072 }
1073
1074 ret = dma_get_slave_caps(dma->rx_chan, &dma_caps);
1075 if (ret < 0 ||
1076 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1077 reason = "insufficient DMA RX engine capabilities";
1078 ret = -EOPNOTSUPP;
1079 goto err_release_rx;
1080 }
1081
1082 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
1083
1084 dma->tx_chan = dma_request_chan(p->port.dev, "tx");
1085 if (IS_ERR(dma->tx_chan)) {
1086 reason = "DMA TX channel request failed";
1087 ret = PTR_ERR(dma->tx_chan);
1088 goto err_release_rx;
1089 }
1090
1091 ret = dma_get_slave_caps(dma->tx_chan, &dma_caps);
1092 if (ret < 0 ||
1093 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1094 reason = "insufficient DMA TX engine capabilities";
1095 ret = -EOPNOTSUPP;
1096 goto err_release_tx;
1097 }
1098
1099 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
1100
1101 /* RX buffer */
1102 dma->rx_size = PAGE_SIZE;
1103
1104 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
1105 if (!dma->rx_buf) {
1106 ret = -ENOMEM;
1107 goto err_release_tx;
1108 }
1109
1110 dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf,
1111 dma->rx_size, DMA_FROM_DEVICE);
1112 if (dma_mapping_error(dma->rx_chan->device->dev, dma->rx_addr)) {
1113 reason = "DMA mapping error for RX buffer";
1114 ret = -EIO;
1115 goto err_free_rx;
1116 }
1117
1118 /* TX buffer */
1119 dma->tx_addr = dma_map_single(dma->tx_chan->device->dev,
1120 p->port.state->xmit.buf, UART_XMIT_SIZE,
1121 DMA_TO_DEVICE);
1122 if (dma_mapping_error(dma->tx_chan->device->dev, dma->tx_addr)) {
1123 reason = "DMA mapping error for TX buffer";
1124 ret = -EIO;
1125 goto err_unmap_rx;
1126 }
1127
1128 return 0;
1129
1130 err_unmap_rx:
1131 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
1132 dma->rx_size, DMA_FROM_DEVICE);
1133 err_free_rx:
1134 kfree(dma->rx_buf);
1135 err_release_tx:
1136 dma_release_channel(dma->tx_chan);
1137 err_release_rx:
1138 dma_release_channel(dma->rx_chan);
1139 err_warn:
1140 if (reason)
1141 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason);
1142 return ret;
1143 }
1144
s3c24xx_serial_release_dma(struct s3c24xx_uart_port * p)1145 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
1146 {
1147 struct s3c24xx_uart_dma *dma = p->dma;
1148
1149 if (dma->rx_chan) {
1150 dmaengine_terminate_all(dma->rx_chan);
1151 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
1152 dma->rx_size, DMA_FROM_DEVICE);
1153 kfree(dma->rx_buf);
1154 dma_release_channel(dma->rx_chan);
1155 dma->rx_chan = NULL;
1156 }
1157
1158 if (dma->tx_chan) {
1159 dmaengine_terminate_all(dma->tx_chan);
1160 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr,
1161 UART_XMIT_SIZE, DMA_TO_DEVICE);
1162 dma_release_channel(dma->tx_chan);
1163 dma->tx_chan = NULL;
1164 }
1165 }
1166
s3c24xx_serial_shutdown(struct uart_port * port)1167 static void s3c24xx_serial_shutdown(struct uart_port *port)
1168 {
1169 struct s3c24xx_uart_port *ourport = to_ourport(port);
1170
1171 if (ourport->tx_claimed) {
1172 free_irq(ourport->tx_irq, ourport);
1173 ourport->tx_enabled = 0;
1174 ourport->tx_claimed = 0;
1175 ourport->tx_mode = 0;
1176 }
1177
1178 if (ourport->rx_claimed) {
1179 free_irq(ourport->rx_irq, ourport);
1180 ourport->rx_claimed = 0;
1181 ourport->rx_enabled = 0;
1182 }
1183
1184 if (ourport->dma)
1185 s3c24xx_serial_release_dma(ourport);
1186
1187 ourport->tx_in_progress = 0;
1188 }
1189
s3c64xx_serial_shutdown(struct uart_port * port)1190 static void s3c64xx_serial_shutdown(struct uart_port *port)
1191 {
1192 struct s3c24xx_uart_port *ourport = to_ourport(port);
1193
1194 ourport->tx_enabled = 0;
1195 ourport->tx_mode = 0;
1196 ourport->rx_enabled = 0;
1197
1198 free_irq(port->irq, ourport);
1199
1200 wr_regl(port, S3C64XX_UINTP, 0xf);
1201 wr_regl(port, S3C64XX_UINTM, 0xf);
1202
1203 if (ourport->dma)
1204 s3c24xx_serial_release_dma(ourport);
1205
1206 ourport->tx_in_progress = 0;
1207 }
1208
apple_s5l_serial_shutdown(struct uart_port * port)1209 static void apple_s5l_serial_shutdown(struct uart_port *port)
1210 {
1211 struct s3c24xx_uart_port *ourport = to_ourport(port);
1212
1213 unsigned int ucon;
1214
1215 ucon = rd_regl(port, S3C2410_UCON);
1216 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
1217 APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
1218 APPLE_S5L_UCON_RXTO_ENA_MSK);
1219 wr_regl(port, S3C2410_UCON, ucon);
1220
1221 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1222
1223 free_irq(port->irq, ourport);
1224
1225 ourport->tx_enabled = 0;
1226 ourport->tx_mode = 0;
1227 ourport->rx_enabled = 0;
1228
1229 if (ourport->dma)
1230 s3c24xx_serial_release_dma(ourport);
1231
1232 ourport->tx_in_progress = 0;
1233 }
1234
s3c24xx_serial_startup(struct uart_port * port)1235 static int s3c24xx_serial_startup(struct uart_port *port)
1236 {
1237 struct s3c24xx_uart_port *ourport = to_ourport(port);
1238 int ret;
1239
1240 ourport->rx_enabled = 1;
1241
1242 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_irq, 0,
1243 s3c24xx_serial_portname(port), ourport);
1244
1245 if (ret != 0) {
1246 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
1247 return ret;
1248 }
1249
1250 ourport->rx_claimed = 1;
1251
1252 dev_dbg(port->dev, "requesting tx irq...\n");
1253
1254 ourport->tx_enabled = 1;
1255
1256 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_irq, 0,
1257 s3c24xx_serial_portname(port), ourport);
1258
1259 if (ret) {
1260 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1261 goto err;
1262 }
1263
1264 ourport->tx_claimed = 1;
1265
1266 /* the port reset code should have done the correct
1267 * register setup for the port controls
1268 */
1269
1270 return ret;
1271
1272 err:
1273 s3c24xx_serial_shutdown(port);
1274 return ret;
1275 }
1276
s3c64xx_serial_startup(struct uart_port * port)1277 static int s3c64xx_serial_startup(struct uart_port *port)
1278 {
1279 struct s3c24xx_uart_port *ourport = to_ourport(port);
1280 unsigned long flags;
1281 unsigned int ufcon;
1282 int ret;
1283
1284 wr_regl(port, S3C64XX_UINTM, 0xf);
1285 if (ourport->dma) {
1286 ret = s3c24xx_serial_request_dma(ourport);
1287 if (ret < 0) {
1288 devm_kfree(port->dev, ourport->dma);
1289 ourport->dma = NULL;
1290 }
1291 }
1292
1293 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1294 s3c24xx_serial_portname(port), ourport);
1295 if (ret) {
1296 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1297 return ret;
1298 }
1299
1300 /* For compatibility with s3c24xx Soc's */
1301 ourport->rx_enabled = 1;
1302 ourport->tx_enabled = 0;
1303
1304 spin_lock_irqsave(&port->lock, flags);
1305
1306 ufcon = rd_regl(port, S3C2410_UFCON);
1307 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1308 if (!uart_console(port))
1309 ufcon |= S3C2410_UFCON_RESETTX;
1310 wr_regl(port, S3C2410_UFCON, ufcon);
1311
1312 enable_rx_pio(ourport);
1313
1314 spin_unlock_irqrestore(&port->lock, flags);
1315
1316 /* Enable Rx Interrupt */
1317 s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1318
1319 return ret;
1320 }
1321
apple_s5l_serial_startup(struct uart_port * port)1322 static int apple_s5l_serial_startup(struct uart_port *port)
1323 {
1324 struct s3c24xx_uart_port *ourport = to_ourport(port);
1325 unsigned long flags;
1326 unsigned int ufcon;
1327 int ret;
1328
1329 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1330
1331 ret = request_irq(port->irq, apple_serial_handle_irq, 0,
1332 s3c24xx_serial_portname(port), ourport);
1333 if (ret) {
1334 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1335 return ret;
1336 }
1337
1338 /* For compatibility with s3c24xx Soc's */
1339 ourport->rx_enabled = 1;
1340 ourport->tx_enabled = 0;
1341
1342 spin_lock_irqsave(&port->lock, flags);
1343
1344 ufcon = rd_regl(port, S3C2410_UFCON);
1345 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1346 if (!uart_console(port))
1347 ufcon |= S3C2410_UFCON_RESETTX;
1348 wr_regl(port, S3C2410_UFCON, ufcon);
1349
1350 enable_rx_pio(ourport);
1351
1352 spin_unlock_irqrestore(&port->lock, flags);
1353
1354 /* Enable Rx Interrupt */
1355 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
1356 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
1357
1358 return ret;
1359 }
1360
1361 /* power power management control */
1362
s3c24xx_serial_pm(struct uart_port * port,unsigned int level,unsigned int old)1363 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1364 unsigned int old)
1365 {
1366 struct s3c24xx_uart_port *ourport = to_ourport(port);
1367 int timeout = 10000;
1368
1369 ourport->pm_level = level;
1370
1371 switch (level) {
1372 case 3:
1373 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1374 udelay(100);
1375
1376 if (!IS_ERR(ourport->baudclk))
1377 clk_disable_unprepare(ourport->baudclk);
1378
1379 clk_disable_unprepare(ourport->clk);
1380 break;
1381
1382 case 0:
1383 clk_prepare_enable(ourport->clk);
1384
1385 if (!IS_ERR(ourport->baudclk))
1386 clk_prepare_enable(ourport->baudclk);
1387 break;
1388 default:
1389 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1390 }
1391 }
1392
1393 /* baud rate calculation
1394 *
1395 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1396 * of different sources, including the peripheral clock ("pclk") and an
1397 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1398 * with a programmable extra divisor.
1399 *
1400 * The following code goes through the clock sources, and calculates the
1401 * baud clocks (and the resultant actual baud rates) and then tries to
1402 * pick the closest one and select that.
1403 *
1404 */
1405
1406 #define MAX_CLK_NAME_LENGTH 15
1407
s3c24xx_serial_getsource(struct uart_port * port)1408 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1409 {
1410 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1411 unsigned int ucon;
1412
1413 if (info->num_clks == 1)
1414 return 0;
1415
1416 ucon = rd_regl(port, S3C2410_UCON);
1417 ucon &= info->clksel_mask;
1418 return ucon >> info->clksel_shift;
1419 }
1420
s3c24xx_serial_setsource(struct uart_port * port,unsigned int clk_sel)1421 static void s3c24xx_serial_setsource(struct uart_port *port,
1422 unsigned int clk_sel)
1423 {
1424 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1425 unsigned int ucon;
1426
1427 if (info->num_clks == 1)
1428 return;
1429
1430 ucon = rd_regl(port, S3C2410_UCON);
1431 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1432 return;
1433
1434 ucon &= ~info->clksel_mask;
1435 ucon |= clk_sel << info->clksel_shift;
1436 wr_regl(port, S3C2410_UCON, ucon);
1437 }
1438
s3c24xx_serial_getclk(struct s3c24xx_uart_port * ourport,unsigned int req_baud,struct clk ** best_clk,unsigned int * clk_num)1439 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1440 unsigned int req_baud, struct clk **best_clk,
1441 unsigned int *clk_num)
1442 {
1443 const struct s3c24xx_uart_info *info = ourport->info;
1444 struct clk *clk;
1445 unsigned long rate;
1446 unsigned int cnt, baud, quot, best_quot = 0;
1447 char clkname[MAX_CLK_NAME_LENGTH];
1448 int calc_deviation, deviation = (1 << 30) - 1;
1449
1450 for (cnt = 0; cnt < info->num_clks; cnt++) {
1451 /* Keep selected clock if provided */
1452 if (ourport->cfg->clk_sel &&
1453 !(ourport->cfg->clk_sel & (1 << cnt)))
1454 continue;
1455
1456 sprintf(clkname, "clk_uart_baud%d", cnt);
1457 clk = clk_get(ourport->port.dev, clkname);
1458 if (IS_ERR(clk))
1459 continue;
1460
1461 rate = clk_get_rate(clk);
1462 if (!rate)
1463 continue;
1464
1465 if (ourport->info->has_divslot) {
1466 unsigned long div = rate / req_baud;
1467
1468 /* The UDIVSLOT register on the newer UARTs allows us to
1469 * get a divisor adjustment of 1/16th on the baud clock.
1470 *
1471 * We don't keep the UDIVSLOT value (the 16ths we
1472 * calculated by not multiplying the baud by 16) as it
1473 * is easy enough to recalculate.
1474 */
1475
1476 quot = div / 16;
1477 baud = rate / div;
1478 } else {
1479 quot = (rate + (8 * req_baud)) / (16 * req_baud);
1480 baud = rate / (quot * 16);
1481 }
1482 quot--;
1483
1484 calc_deviation = req_baud - baud;
1485 if (calc_deviation < 0)
1486 calc_deviation = -calc_deviation;
1487
1488 if (calc_deviation < deviation) {
1489 *best_clk = clk;
1490 best_quot = quot;
1491 *clk_num = cnt;
1492 deviation = calc_deviation;
1493 }
1494 }
1495
1496 return best_quot;
1497 }
1498
1499 /* udivslot_table[]
1500 *
1501 * This table takes the fractional value of the baud divisor and gives
1502 * the recommended setting for the UDIVSLOT register.
1503 */
1504 static const u16 udivslot_table[16] = {
1505 [0] = 0x0000,
1506 [1] = 0x0080,
1507 [2] = 0x0808,
1508 [3] = 0x0888,
1509 [4] = 0x2222,
1510 [5] = 0x4924,
1511 [6] = 0x4A52,
1512 [7] = 0x54AA,
1513 [8] = 0x5555,
1514 [9] = 0xD555,
1515 [10] = 0xD5D5,
1516 [11] = 0xDDD5,
1517 [12] = 0xDDDD,
1518 [13] = 0xDFDD,
1519 [14] = 0xDFDF,
1520 [15] = 0xFFDF,
1521 };
1522
s3c24xx_serial_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)1523 static void s3c24xx_serial_set_termios(struct uart_port *port,
1524 struct ktermios *termios,
1525 const struct ktermios *old)
1526 {
1527 const struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1528 struct s3c24xx_uart_port *ourport = to_ourport(port);
1529 struct clk *clk = ERR_PTR(-EINVAL);
1530 unsigned long flags;
1531 unsigned int baud, quot, clk_sel = 0;
1532 unsigned int ulcon;
1533 unsigned int umcon;
1534 unsigned int udivslot = 0;
1535
1536 /*
1537 * We don't support modem control lines.
1538 */
1539 termios->c_cflag &= ~(HUPCL | CMSPAR);
1540 termios->c_cflag |= CLOCAL;
1541
1542 /*
1543 * Ask the core to calculate the divisor for us.
1544 */
1545
1546 baud = uart_get_baud_rate(port, termios, old, 0, 3000000);
1547 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1548 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1549 quot = port->custom_divisor;
1550 if (IS_ERR(clk))
1551 return;
1552
1553 /* check to see if we need to change clock source */
1554
1555 if (ourport->baudclk != clk) {
1556 clk_prepare_enable(clk);
1557
1558 s3c24xx_serial_setsource(port, clk_sel);
1559
1560 if (!IS_ERR(ourport->baudclk)) {
1561 clk_disable_unprepare(ourport->baudclk);
1562 ourport->baudclk = ERR_PTR(-EINVAL);
1563 }
1564
1565 ourport->baudclk = clk;
1566 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1567 }
1568
1569 if (ourport->info->has_divslot) {
1570 unsigned int div = ourport->baudclk_rate / baud;
1571
1572 if (cfg->has_fracval) {
1573 udivslot = (div & 15);
1574 dev_dbg(port->dev, "fracval = %04x\n", udivslot);
1575 } else {
1576 udivslot = udivslot_table[div & 15];
1577 dev_dbg(port->dev, "udivslot = %04x (div %d)\n",
1578 udivslot, div & 15);
1579 }
1580 }
1581
1582 switch (termios->c_cflag & CSIZE) {
1583 case CS5:
1584 dev_dbg(port->dev, "config: 5bits/char\n");
1585 ulcon = S3C2410_LCON_CS5;
1586 break;
1587 case CS6:
1588 dev_dbg(port->dev, "config: 6bits/char\n");
1589 ulcon = S3C2410_LCON_CS6;
1590 break;
1591 case CS7:
1592 dev_dbg(port->dev, "config: 7bits/char\n");
1593 ulcon = S3C2410_LCON_CS7;
1594 break;
1595 case CS8:
1596 default:
1597 dev_dbg(port->dev, "config: 8bits/char\n");
1598 ulcon = S3C2410_LCON_CS8;
1599 break;
1600 }
1601
1602 /* preserve original lcon IR settings */
1603 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1604
1605 if (termios->c_cflag & CSTOPB)
1606 ulcon |= S3C2410_LCON_STOPB;
1607
1608 if (termios->c_cflag & PARENB) {
1609 if (termios->c_cflag & PARODD)
1610 ulcon |= S3C2410_LCON_PODD;
1611 else
1612 ulcon |= S3C2410_LCON_PEVEN;
1613 } else {
1614 ulcon |= S3C2410_LCON_PNONE;
1615 }
1616
1617 spin_lock_irqsave(&port->lock, flags);
1618
1619 dev_dbg(port->dev,
1620 "setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1621 ulcon, quot, udivslot);
1622
1623 wr_regl(port, S3C2410_ULCON, ulcon);
1624 wr_regl(port, S3C2410_UBRDIV, quot);
1625
1626 port->status &= ~UPSTAT_AUTOCTS;
1627
1628 umcon = rd_regl(port, S3C2410_UMCON);
1629 if (termios->c_cflag & CRTSCTS) {
1630 umcon |= S3C2410_UMCOM_AFC;
1631 /* Disable RTS when RX FIFO contains 63 bytes */
1632 umcon &= ~S3C2412_UMCON_AFC_8;
1633 port->status = UPSTAT_AUTOCTS;
1634 } else {
1635 umcon &= ~S3C2410_UMCOM_AFC;
1636 }
1637 wr_regl(port, S3C2410_UMCON, umcon);
1638
1639 if (ourport->info->has_divslot)
1640 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1641
1642 dev_dbg(port->dev,
1643 "uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1644 rd_regl(port, S3C2410_ULCON),
1645 rd_regl(port, S3C2410_UCON),
1646 rd_regl(port, S3C2410_UFCON));
1647
1648 /*
1649 * Update the per-port timeout.
1650 */
1651 uart_update_timeout(port, termios->c_cflag, baud);
1652
1653 /*
1654 * Which character status flags are we interested in?
1655 */
1656 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1657 if (termios->c_iflag & INPCK)
1658 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1659 S3C2410_UERSTAT_PARITY;
1660 /*
1661 * Which character status flags should we ignore?
1662 */
1663 port->ignore_status_mask = 0;
1664 if (termios->c_iflag & IGNPAR)
1665 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1666 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1667 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1668
1669 /*
1670 * Ignore all characters if CREAD is not set.
1671 */
1672 if ((termios->c_cflag & CREAD) == 0)
1673 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1674
1675 spin_unlock_irqrestore(&port->lock, flags);
1676 }
1677
s3c24xx_serial_type(struct uart_port * port)1678 static const char *s3c24xx_serial_type(struct uart_port *port)
1679 {
1680 const struct s3c24xx_uart_port *ourport = to_ourport(port);
1681
1682 switch (ourport->info->type) {
1683 case TYPE_S3C24XX:
1684 return "S3C24XX";
1685 case TYPE_S3C6400:
1686 return "S3C6400/10";
1687 case TYPE_APPLE_S5L:
1688 return "APPLE S5L";
1689 default:
1690 return NULL;
1691 }
1692 }
1693
s3c24xx_serial_config_port(struct uart_port * port,int flags)1694 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1695 {
1696 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1697
1698 if (flags & UART_CONFIG_TYPE)
1699 port->type = info->port_type;
1700 }
1701
1702 /*
1703 * verify the new serial_struct (for TIOCSSERIAL).
1704 */
1705 static int
s3c24xx_serial_verify_port(struct uart_port * port,struct serial_struct * ser)1706 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1707 {
1708 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1709
1710 if (ser->type != PORT_UNKNOWN && ser->type != info->port_type)
1711 return -EINVAL;
1712
1713 return 0;
1714 }
1715
1716 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1717
1718 static struct console s3c24xx_serial_console;
1719
s3c24xx_serial_register_console(void)1720 static void __init s3c24xx_serial_register_console(void)
1721 {
1722 register_console(&s3c24xx_serial_console);
1723 }
1724
s3c24xx_serial_unregister_console(void)1725 static void s3c24xx_serial_unregister_console(void)
1726 {
1727 if (console_is_registered(&s3c24xx_serial_console))
1728 unregister_console(&s3c24xx_serial_console);
1729 }
1730
1731 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1732 #else
s3c24xx_serial_register_console(void)1733 static inline void s3c24xx_serial_register_console(void) { }
s3c24xx_serial_unregister_console(void)1734 static inline void s3c24xx_serial_unregister_console(void) { }
1735 #define S3C24XX_SERIAL_CONSOLE NULL
1736 #endif
1737
1738 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1739 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1740 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1741 unsigned char c);
1742 #endif
1743
1744 static const struct uart_ops s3c24xx_serial_ops = {
1745 .pm = s3c24xx_serial_pm,
1746 .tx_empty = s3c24xx_serial_tx_empty,
1747 .get_mctrl = s3c24xx_serial_get_mctrl,
1748 .set_mctrl = s3c24xx_serial_set_mctrl,
1749 .stop_tx = s3c24xx_serial_stop_tx,
1750 .start_tx = s3c24xx_serial_start_tx,
1751 .stop_rx = s3c24xx_serial_stop_rx,
1752 .break_ctl = s3c24xx_serial_break_ctl,
1753 .startup = s3c24xx_serial_startup,
1754 .shutdown = s3c24xx_serial_shutdown,
1755 .set_termios = s3c24xx_serial_set_termios,
1756 .type = s3c24xx_serial_type,
1757 .config_port = s3c24xx_serial_config_port,
1758 .verify_port = s3c24xx_serial_verify_port,
1759 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1760 .poll_get_char = s3c24xx_serial_get_poll_char,
1761 .poll_put_char = s3c24xx_serial_put_poll_char,
1762 #endif
1763 };
1764
1765 static const struct uart_ops s3c64xx_serial_ops = {
1766 .pm = s3c24xx_serial_pm,
1767 .tx_empty = s3c24xx_serial_tx_empty,
1768 .get_mctrl = s3c24xx_serial_get_mctrl,
1769 .set_mctrl = s3c24xx_serial_set_mctrl,
1770 .stop_tx = s3c24xx_serial_stop_tx,
1771 .start_tx = s3c24xx_serial_start_tx,
1772 .stop_rx = s3c24xx_serial_stop_rx,
1773 .break_ctl = s3c24xx_serial_break_ctl,
1774 .startup = s3c64xx_serial_startup,
1775 .shutdown = s3c64xx_serial_shutdown,
1776 .set_termios = s3c24xx_serial_set_termios,
1777 .type = s3c24xx_serial_type,
1778 .config_port = s3c24xx_serial_config_port,
1779 .verify_port = s3c24xx_serial_verify_port,
1780 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1781 .poll_get_char = s3c24xx_serial_get_poll_char,
1782 .poll_put_char = s3c24xx_serial_put_poll_char,
1783 #endif
1784 };
1785
1786 static const struct uart_ops apple_s5l_serial_ops = {
1787 .pm = s3c24xx_serial_pm,
1788 .tx_empty = s3c24xx_serial_tx_empty,
1789 .get_mctrl = s3c24xx_serial_get_mctrl,
1790 .set_mctrl = s3c24xx_serial_set_mctrl,
1791 .stop_tx = s3c24xx_serial_stop_tx,
1792 .start_tx = s3c24xx_serial_start_tx,
1793 .stop_rx = s3c24xx_serial_stop_rx,
1794 .break_ctl = s3c24xx_serial_break_ctl,
1795 .startup = apple_s5l_serial_startup,
1796 .shutdown = apple_s5l_serial_shutdown,
1797 .set_termios = s3c24xx_serial_set_termios,
1798 .type = s3c24xx_serial_type,
1799 .config_port = s3c24xx_serial_config_port,
1800 .verify_port = s3c24xx_serial_verify_port,
1801 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1802 .poll_get_char = s3c24xx_serial_get_poll_char,
1803 .poll_put_char = s3c24xx_serial_put_poll_char,
1804 #endif
1805 };
1806
1807 static struct uart_driver s3c24xx_uart_drv = {
1808 .owner = THIS_MODULE,
1809 .driver_name = "s3c2410_serial",
1810 .nr = UART_NR,
1811 .cons = S3C24XX_SERIAL_CONSOLE,
1812 .dev_name = S3C24XX_SERIAL_NAME,
1813 .major = S3C24XX_SERIAL_MAJOR,
1814 .minor = S3C24XX_SERIAL_MINOR,
1815 };
1816
1817 static struct s3c24xx_uart_port s3c24xx_serial_ports[UART_NR];
1818
s3c24xx_serial_init_port_default(int index)1819 static void s3c24xx_serial_init_port_default(int index) {
1820 struct uart_port *port = &s3c24xx_serial_ports[index].port;
1821
1822 spin_lock_init(&port->lock);
1823
1824 port->iotype = UPIO_MEM;
1825 port->uartclk = 0;
1826 port->fifosize = 16;
1827 port->ops = &s3c24xx_serial_ops;
1828 port->flags = UPF_BOOT_AUTOCONF;
1829 port->line = index;
1830 }
1831
1832 /* s3c24xx_serial_resetport
1833 *
1834 * reset the fifos and other the settings.
1835 */
1836
s3c24xx_serial_resetport(struct uart_port * port,const struct s3c2410_uartcfg * cfg)1837 static void s3c24xx_serial_resetport(struct uart_port *port,
1838 const struct s3c2410_uartcfg *cfg)
1839 {
1840 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1841 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1842
1843 ucon &= (info->clksel_mask | info->ucon_mask);
1844 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1845
1846 /* reset both fifos */
1847 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1848 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1849
1850 /* some delay is required after fifo reset */
1851 udelay(1);
1852 }
1853
s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port * ourport)1854 static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport)
1855 {
1856 struct device *dev = ourport->port.dev;
1857 const struct s3c24xx_uart_info *info = ourport->info;
1858 char clk_name[MAX_CLK_NAME_LENGTH];
1859 unsigned int clk_sel;
1860 struct clk *clk;
1861 int clk_num;
1862 int ret;
1863
1864 clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel;
1865 for (clk_num = 0; clk_num < info->num_clks; clk_num++) {
1866 if (!(clk_sel & (1 << clk_num)))
1867 continue;
1868
1869 sprintf(clk_name, "clk_uart_baud%d", clk_num);
1870 clk = clk_get(dev, clk_name);
1871 if (IS_ERR(clk))
1872 continue;
1873
1874 ret = clk_prepare_enable(clk);
1875 if (ret) {
1876 clk_put(clk);
1877 continue;
1878 }
1879
1880 ourport->baudclk = clk;
1881 ourport->baudclk_rate = clk_get_rate(clk);
1882 s3c24xx_serial_setsource(&ourport->port, clk_num);
1883
1884 return 0;
1885 }
1886
1887 return -EINVAL;
1888 }
1889
1890 /* s3c24xx_serial_init_port
1891 *
1892 * initialise a single serial port from the platform device given
1893 */
1894
s3c24xx_serial_init_port(struct s3c24xx_uart_port * ourport,struct platform_device * platdev)1895 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1896 struct platform_device *platdev)
1897 {
1898 struct uart_port *port = &ourport->port;
1899 const struct s3c2410_uartcfg *cfg = ourport->cfg;
1900 struct resource *res;
1901 int ret;
1902
1903 if (platdev == NULL)
1904 return -ENODEV;
1905
1906 if (port->mapbase != 0)
1907 return -EINVAL;
1908
1909 /* setup info for port */
1910 port->dev = &platdev->dev;
1911
1912 port->uartclk = 1;
1913
1914 if (cfg->uart_flags & UPF_CONS_FLOW) {
1915 dev_dbg(port->dev, "enabling flow control\n");
1916 port->flags |= UPF_CONS_FLOW;
1917 }
1918
1919 /* sort our the physical and virtual addresses for each UART */
1920
1921 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1922 if (res == NULL) {
1923 dev_err(port->dev, "failed to find memory resource for uart\n");
1924 return -EINVAL;
1925 }
1926
1927 dev_dbg(port->dev, "resource %pR)\n", res);
1928
1929 port->membase = devm_ioremap_resource(port->dev, res);
1930 if (IS_ERR(port->membase)) {
1931 dev_err(port->dev, "failed to remap controller address\n");
1932 return -EBUSY;
1933 }
1934
1935 port->mapbase = res->start;
1936 ret = platform_get_irq(platdev, 0);
1937 if (ret < 0) {
1938 port->irq = 0;
1939 } else {
1940 port->irq = ret;
1941 ourport->rx_irq = ret;
1942 ourport->tx_irq = ret + 1;
1943 }
1944
1945 switch (ourport->info->type) {
1946 case TYPE_S3C24XX:
1947 ret = platform_get_irq(platdev, 1);
1948 if (ret > 0)
1949 ourport->tx_irq = ret;
1950 break;
1951 default:
1952 break;
1953 }
1954
1955 /*
1956 * DMA is currently supported only on DT platforms, if DMA properties
1957 * are specified.
1958 */
1959 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1960 "dmas", NULL)) {
1961 ourport->dma = devm_kzalloc(port->dev,
1962 sizeof(*ourport->dma),
1963 GFP_KERNEL);
1964 if (!ourport->dma) {
1965 ret = -ENOMEM;
1966 goto err;
1967 }
1968 }
1969
1970 ourport->clk = clk_get(&platdev->dev, "uart");
1971 if (IS_ERR(ourport->clk)) {
1972 pr_err("%s: Controller clock not found\n",
1973 dev_name(&platdev->dev));
1974 ret = PTR_ERR(ourport->clk);
1975 goto err;
1976 }
1977
1978 ret = clk_prepare_enable(ourport->clk);
1979 if (ret) {
1980 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1981 clk_put(ourport->clk);
1982 goto err;
1983 }
1984
1985 ret = s3c24xx_serial_enable_baudclk(ourport);
1986 if (ret)
1987 pr_warn("uart: failed to enable baudclk\n");
1988
1989 /* Keep all interrupts masked and cleared */
1990 switch (ourport->info->type) {
1991 case TYPE_S3C6400:
1992 wr_regl(port, S3C64XX_UINTM, 0xf);
1993 wr_regl(port, S3C64XX_UINTP, 0xf);
1994 wr_regl(port, S3C64XX_UINTSP, 0xf);
1995 break;
1996 case TYPE_APPLE_S5L: {
1997 unsigned int ucon;
1998
1999 ucon = rd_regl(port, S3C2410_UCON);
2000 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
2001 APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2002 APPLE_S5L_UCON_RXTO_ENA_MSK);
2003 wr_regl(port, S3C2410_UCON, ucon);
2004
2005 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
2006 break;
2007 }
2008 default:
2009 break;
2010 }
2011
2012 dev_dbg(port->dev, "port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
2013 &port->mapbase, port->membase, port->irq,
2014 ourport->rx_irq, ourport->tx_irq, port->uartclk);
2015
2016 /* reset the fifos (and setup the uart) */
2017 s3c24xx_serial_resetport(port, cfg);
2018
2019 return 0;
2020
2021 err:
2022 port->mapbase = 0;
2023 return ret;
2024 }
2025
2026 /* Device driver serial port probe */
2027
2028 static int probe_index;
2029
2030 static inline const struct s3c24xx_serial_drv_data *
s3c24xx_get_driver_data(struct platform_device * pdev)2031 s3c24xx_get_driver_data(struct platform_device *pdev)
2032 {
2033 if (dev_of_node(&pdev->dev))
2034 return of_device_get_match_data(&pdev->dev);
2035
2036 return (struct s3c24xx_serial_drv_data *)
2037 platform_get_device_id(pdev)->driver_data;
2038 }
2039
s3c24xx_serial_probe(struct platform_device * pdev)2040 static int s3c24xx_serial_probe(struct platform_device *pdev)
2041 {
2042 struct device_node *np = pdev->dev.of_node;
2043 struct s3c24xx_uart_port *ourport;
2044 int index = probe_index;
2045 int ret, prop = 0;
2046
2047 if (np) {
2048 ret = of_alias_get_id(np, "serial");
2049 if (ret >= 0)
2050 index = ret;
2051 }
2052
2053 if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
2054 dev_err(&pdev->dev, "serial%d out of range\n", index);
2055 return -EINVAL;
2056 }
2057 ourport = &s3c24xx_serial_ports[index];
2058
2059 s3c24xx_serial_init_port_default(index);
2060
2061 ourport->drv_data = s3c24xx_get_driver_data(pdev);
2062 if (!ourport->drv_data) {
2063 dev_err(&pdev->dev, "could not find driver data\n");
2064 return -ENODEV;
2065 }
2066
2067 ourport->baudclk = ERR_PTR(-EINVAL);
2068 ourport->info = &ourport->drv_data->info;
2069 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
2070 dev_get_platdata(&pdev->dev) :
2071 &ourport->drv_data->def_cfg;
2072
2073 switch (ourport->info->type) {
2074 case TYPE_S3C24XX:
2075 ourport->port.ops = &s3c24xx_serial_ops;
2076 break;
2077 case TYPE_S3C6400:
2078 ourport->port.ops = &s3c64xx_serial_ops;
2079 break;
2080 case TYPE_APPLE_S5L:
2081 ourport->port.ops = &apple_s5l_serial_ops;
2082 break;
2083 }
2084
2085 if (np) {
2086 of_property_read_u32(np,
2087 "samsung,uart-fifosize", &ourport->port.fifosize);
2088
2089 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
2090 switch (prop) {
2091 case 1:
2092 ourport->port.iotype = UPIO_MEM;
2093 break;
2094 case 4:
2095 ourport->port.iotype = UPIO_MEM32;
2096 break;
2097 default:
2098 dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n",
2099 prop);
2100 return -EINVAL;
2101 }
2102 }
2103 }
2104
2105 if (ourport->drv_data->fifosize[index])
2106 ourport->port.fifosize = ourport->drv_data->fifosize[index];
2107 else if (ourport->info->fifosize)
2108 ourport->port.fifosize = ourport->info->fifosize;
2109 ourport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SAMSUNG_CONSOLE);
2110
2111 /*
2112 * DMA transfers must be aligned at least to cache line size,
2113 * so find minimal transfer size suitable for DMA mode
2114 */
2115 ourport->min_dma_size = max_t(int, ourport->port.fifosize,
2116 dma_get_cache_alignment());
2117
2118 dev_dbg(&pdev->dev, "%s: initialising port %p...\n", __func__, ourport);
2119
2120 ret = s3c24xx_serial_init_port(ourport, pdev);
2121 if (ret < 0)
2122 return ret;
2123
2124 if (!s3c24xx_uart_drv.state) {
2125 ret = uart_register_driver(&s3c24xx_uart_drv);
2126 if (ret < 0) {
2127 pr_err("Failed to register Samsung UART driver\n");
2128 return ret;
2129 }
2130 }
2131
2132 dev_dbg(&pdev->dev, "%s: adding port\n", __func__);
2133 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
2134 platform_set_drvdata(pdev, &ourport->port);
2135
2136 /*
2137 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
2138 * so that a potential re-enablement through the pm-callback overlaps
2139 * and keeps the clock enabled in this case.
2140 */
2141 clk_disable_unprepare(ourport->clk);
2142 if (!IS_ERR(ourport->baudclk))
2143 clk_disable_unprepare(ourport->baudclk);
2144
2145 probe_index++;
2146
2147 return 0;
2148 }
2149
s3c24xx_serial_remove(struct platform_device * dev)2150 static int s3c24xx_serial_remove(struct platform_device *dev)
2151 {
2152 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
2153
2154 if (port) {
2155 uart_remove_one_port(&s3c24xx_uart_drv, port);
2156 }
2157
2158 uart_unregister_driver(&s3c24xx_uart_drv);
2159
2160 return 0;
2161 }
2162
2163 /* UART power management code */
2164 #ifdef CONFIG_PM_SLEEP
s3c24xx_serial_suspend(struct device * dev)2165 static int s3c24xx_serial_suspend(struct device *dev)
2166 {
2167 struct uart_port *port = s3c24xx_dev_to_port(dev);
2168
2169 if (port)
2170 uart_suspend_port(&s3c24xx_uart_drv, port);
2171
2172 return 0;
2173 }
2174
s3c24xx_serial_resume(struct device * dev)2175 static int s3c24xx_serial_resume(struct device *dev)
2176 {
2177 struct uart_port *port = s3c24xx_dev_to_port(dev);
2178 struct s3c24xx_uart_port *ourport = to_ourport(port);
2179
2180 if (port) {
2181 clk_prepare_enable(ourport->clk);
2182 if (!IS_ERR(ourport->baudclk))
2183 clk_prepare_enable(ourport->baudclk);
2184 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
2185 if (!IS_ERR(ourport->baudclk))
2186 clk_disable_unprepare(ourport->baudclk);
2187 clk_disable_unprepare(ourport->clk);
2188
2189 uart_resume_port(&s3c24xx_uart_drv, port);
2190 }
2191
2192 return 0;
2193 }
2194
s3c24xx_serial_resume_noirq(struct device * dev)2195 static int s3c24xx_serial_resume_noirq(struct device *dev)
2196 {
2197 struct uart_port *port = s3c24xx_dev_to_port(dev);
2198 struct s3c24xx_uart_port *ourport = to_ourport(port);
2199
2200 if (port) {
2201 /* restore IRQ mask */
2202 switch (ourport->info->type) {
2203 case TYPE_S3C6400: {
2204 unsigned int uintm = 0xf;
2205
2206 if (ourport->tx_enabled)
2207 uintm &= ~S3C64XX_UINTM_TXD_MSK;
2208 if (ourport->rx_enabled)
2209 uintm &= ~S3C64XX_UINTM_RXD_MSK;
2210 clk_prepare_enable(ourport->clk);
2211 if (!IS_ERR(ourport->baudclk))
2212 clk_prepare_enable(ourport->baudclk);
2213 wr_regl(port, S3C64XX_UINTM, uintm);
2214 if (!IS_ERR(ourport->baudclk))
2215 clk_disable_unprepare(ourport->baudclk);
2216 clk_disable_unprepare(ourport->clk);
2217 break;
2218 }
2219 case TYPE_APPLE_S5L: {
2220 unsigned int ucon;
2221 int ret;
2222
2223 ret = clk_prepare_enable(ourport->clk);
2224 if (ret) {
2225 dev_err(dev, "clk_enable clk failed: %d\n", ret);
2226 return ret;
2227 }
2228 if (!IS_ERR(ourport->baudclk)) {
2229 ret = clk_prepare_enable(ourport->baudclk);
2230 if (ret) {
2231 dev_err(dev, "clk_enable baudclk failed: %d\n", ret);
2232 clk_disable_unprepare(ourport->clk);
2233 return ret;
2234 }
2235 }
2236
2237 ucon = rd_regl(port, S3C2410_UCON);
2238
2239 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
2240 APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2241 APPLE_S5L_UCON_RXTO_ENA_MSK);
2242
2243 if (ourport->tx_enabled)
2244 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
2245 if (ourport->rx_enabled)
2246 ucon |= APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2247 APPLE_S5L_UCON_RXTO_ENA_MSK;
2248
2249 wr_regl(port, S3C2410_UCON, ucon);
2250
2251 if (!IS_ERR(ourport->baudclk))
2252 clk_disable_unprepare(ourport->baudclk);
2253 clk_disable_unprepare(ourport->clk);
2254 break;
2255 }
2256 default:
2257 break;
2258 }
2259 }
2260
2261 return 0;
2262 }
2263
2264 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
2265 .suspend = s3c24xx_serial_suspend,
2266 .resume = s3c24xx_serial_resume,
2267 .resume_noirq = s3c24xx_serial_resume_noirq,
2268 };
2269 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
2270
2271 #else /* !CONFIG_PM_SLEEP */
2272
2273 #define SERIAL_SAMSUNG_PM_OPS NULL
2274 #endif /* CONFIG_PM_SLEEP */
2275
2276 /* Console code */
2277
2278 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2279
2280 static struct uart_port *cons_uart;
2281
2282 static int
s3c24xx_serial_console_txrdy(struct uart_port * port,unsigned int ufcon)2283 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
2284 {
2285 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
2286 unsigned long ufstat, utrstat;
2287
2288 if (ufcon & S3C2410_UFCON_FIFOMODE) {
2289 /* fifo mode - check amount of data in fifo registers... */
2290
2291 ufstat = rd_regl(port, S3C2410_UFSTAT);
2292 return (ufstat & info->tx_fifofull) ? 0 : 1;
2293 }
2294
2295 /* in non-fifo mode, we go and use the tx buffer empty */
2296
2297 utrstat = rd_regl(port, S3C2410_UTRSTAT);
2298 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
2299 }
2300
2301 static bool
s3c24xx_port_configured(unsigned int ucon)2302 s3c24xx_port_configured(unsigned int ucon)
2303 {
2304 /* consider the serial port configured if the tx/rx mode set */
2305 return (ucon & 0xf) != 0;
2306 }
2307
2308 #ifdef CONFIG_CONSOLE_POLL
2309 /*
2310 * Console polling routines for writing and reading from the uart while
2311 * in an interrupt or debug context.
2312 */
2313
s3c24xx_serial_get_poll_char(struct uart_port * port)2314 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2315 {
2316 const struct s3c24xx_uart_port *ourport = to_ourport(port);
2317 unsigned int ufstat;
2318
2319 ufstat = rd_regl(port, S3C2410_UFSTAT);
2320 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2321 return NO_POLL_CHAR;
2322
2323 return rd_reg(port, S3C2410_URXH);
2324 }
2325
s3c24xx_serial_put_poll_char(struct uart_port * port,unsigned char c)2326 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2327 unsigned char c)
2328 {
2329 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2330 unsigned int ucon = rd_regl(port, S3C2410_UCON);
2331
2332 /* not possible to xmit on unconfigured port */
2333 if (!s3c24xx_port_configured(ucon))
2334 return;
2335
2336 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2337 cpu_relax();
2338 wr_reg(port, S3C2410_UTXH, c);
2339 }
2340
2341 #endif /* CONFIG_CONSOLE_POLL */
2342
2343 static void
s3c24xx_serial_console_putchar(struct uart_port * port,unsigned char ch)2344 s3c24xx_serial_console_putchar(struct uart_port *port, unsigned char ch)
2345 {
2346 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2347
2348 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2349 cpu_relax();
2350 wr_reg(port, S3C2410_UTXH, ch);
2351 }
2352
2353 static void
s3c24xx_serial_console_write(struct console * co,const char * s,unsigned int count)2354 s3c24xx_serial_console_write(struct console *co, const char *s,
2355 unsigned int count)
2356 {
2357 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2358 unsigned long flags;
2359 bool locked = true;
2360
2361 /* not possible to xmit on unconfigured port */
2362 if (!s3c24xx_port_configured(ucon))
2363 return;
2364
2365 if (cons_uart->sysrq)
2366 locked = false;
2367 else if (oops_in_progress)
2368 locked = spin_trylock_irqsave(&cons_uart->lock, flags);
2369 else
2370 spin_lock_irqsave(&cons_uart->lock, flags);
2371
2372 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2373
2374 if (locked)
2375 spin_unlock_irqrestore(&cons_uart->lock, flags);
2376 }
2377
2378 /* Shouldn't be __init, as it can be instantiated from other module */
2379 static void
s3c24xx_serial_get_options(struct uart_port * port,int * baud,int * parity,int * bits)2380 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2381 int *parity, int *bits)
2382 {
2383 struct clk *clk;
2384 unsigned int ulcon;
2385 unsigned int ucon;
2386 unsigned int ubrdiv;
2387 unsigned long rate;
2388 unsigned int clk_sel;
2389 char clk_name[MAX_CLK_NAME_LENGTH];
2390
2391 ulcon = rd_regl(port, S3C2410_ULCON);
2392 ucon = rd_regl(port, S3C2410_UCON);
2393 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2394
2395 if (s3c24xx_port_configured(ucon)) {
2396 switch (ulcon & S3C2410_LCON_CSMASK) {
2397 case S3C2410_LCON_CS5:
2398 *bits = 5;
2399 break;
2400 case S3C2410_LCON_CS6:
2401 *bits = 6;
2402 break;
2403 case S3C2410_LCON_CS7:
2404 *bits = 7;
2405 break;
2406 case S3C2410_LCON_CS8:
2407 default:
2408 *bits = 8;
2409 break;
2410 }
2411
2412 switch (ulcon & S3C2410_LCON_PMASK) {
2413 case S3C2410_LCON_PEVEN:
2414 *parity = 'e';
2415 break;
2416
2417 case S3C2410_LCON_PODD:
2418 *parity = 'o';
2419 break;
2420
2421 case S3C2410_LCON_PNONE:
2422 default:
2423 *parity = 'n';
2424 }
2425
2426 /* now calculate the baud rate */
2427
2428 clk_sel = s3c24xx_serial_getsource(port);
2429 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2430
2431 clk = clk_get(port->dev, clk_name);
2432 if (!IS_ERR(clk))
2433 rate = clk_get_rate(clk);
2434 else
2435 rate = 1;
2436
2437 *baud = rate / (16 * (ubrdiv + 1));
2438 dev_dbg(port->dev, "calculated baud %d\n", *baud);
2439 }
2440 }
2441
2442 /* Shouldn't be __init, as it can be instantiated from other module */
2443 static int
s3c24xx_serial_console_setup(struct console * co,char * options)2444 s3c24xx_serial_console_setup(struct console *co, char *options)
2445 {
2446 struct uart_port *port;
2447 int baud = 9600;
2448 int bits = 8;
2449 int parity = 'n';
2450 int flow = 'n';
2451
2452 /* is this a valid port */
2453
2454 if (co->index == -1 || co->index >= UART_NR)
2455 co->index = 0;
2456
2457 port = &s3c24xx_serial_ports[co->index].port;
2458
2459 /* is the port configured? */
2460
2461 if (port->mapbase == 0x0)
2462 return -ENODEV;
2463
2464 cons_uart = port;
2465
2466 /*
2467 * Check whether an invalid uart number has been specified, and
2468 * if so, search for the first available port that does have
2469 * console support.
2470 */
2471 if (options)
2472 uart_parse_options(options, &baud, &parity, &bits, &flow);
2473 else
2474 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2475
2476 dev_dbg(port->dev, "baud %d\n", baud);
2477
2478 return uart_set_options(port, co, baud, parity, bits, flow);
2479 }
2480
2481 static struct console s3c24xx_serial_console = {
2482 .name = S3C24XX_SERIAL_NAME,
2483 .device = uart_console_device,
2484 .flags = CON_PRINTBUFFER,
2485 .index = -1,
2486 .write = s3c24xx_serial_console_write,
2487 .setup = s3c24xx_serial_console_setup,
2488 .data = &s3c24xx_uart_drv,
2489 };
2490 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2491
2492 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2493 static const struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2494 .info = {
2495 .name = "Samsung S3C6400 UART",
2496 .type = TYPE_S3C6400,
2497 .port_type = PORT_S3C6400,
2498 .fifosize = 64,
2499 .has_divslot = 1,
2500 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2501 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2502 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2503 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2504 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2505 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2506 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2507 .num_clks = 4,
2508 .clksel_mask = S3C6400_UCON_CLKMASK,
2509 .clksel_shift = S3C6400_UCON_CLKSHIFT,
2510 },
2511 .def_cfg = {
2512 .ucon = S3C2410_UCON_DEFAULT,
2513 .ufcon = S3C2410_UFCON_DEFAULT,
2514 },
2515 };
2516 #define S3C6400_SERIAL_DRV_DATA (&s3c6400_serial_drv_data)
2517 #else
2518 #define S3C6400_SERIAL_DRV_DATA NULL
2519 #endif
2520
2521 #ifdef CONFIG_CPU_S5PV210
2522 static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2523 .info = {
2524 .name = "Samsung S5PV210 UART",
2525 .type = TYPE_S3C6400,
2526 .port_type = PORT_S3C6400,
2527 .has_divslot = 1,
2528 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2529 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2530 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2531 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2532 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2533 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2534 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2535 .num_clks = 2,
2536 .clksel_mask = S5PV210_UCON_CLKMASK,
2537 .clksel_shift = S5PV210_UCON_CLKSHIFT,
2538 },
2539 .def_cfg = {
2540 .ucon = S5PV210_UCON_DEFAULT,
2541 .ufcon = S5PV210_UFCON_DEFAULT,
2542 },
2543 .fifosize = { 256, 64, 16, 16 },
2544 };
2545 #define S5PV210_SERIAL_DRV_DATA (&s5pv210_serial_drv_data)
2546 #else
2547 #define S5PV210_SERIAL_DRV_DATA NULL
2548 #endif
2549
2550 #if defined(CONFIG_ARCH_EXYNOS)
2551 #define EXYNOS_COMMON_SERIAL_DRV_DATA() \
2552 .info = { \
2553 .name = "Samsung Exynos UART", \
2554 .type = TYPE_S3C6400, \
2555 .port_type = PORT_S3C6400, \
2556 .has_divslot = 1, \
2557 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
2558 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
2559 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
2560 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
2561 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
2562 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
2563 .def_clk_sel = S3C2410_UCON_CLKSEL0, \
2564 .num_clks = 1, \
2565 .clksel_mask = 0, \
2566 .clksel_shift = 0, \
2567 }, \
2568 .def_cfg = { \
2569 .ucon = S5PV210_UCON_DEFAULT, \
2570 .ufcon = S5PV210_UFCON_DEFAULT, \
2571 .has_fracval = 1, \
2572 } \
2573
2574 static const struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2575 EXYNOS_COMMON_SERIAL_DRV_DATA(),
2576 .fifosize = { 256, 64, 16, 16 },
2577 };
2578
2579 static const struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2580 EXYNOS_COMMON_SERIAL_DRV_DATA(),
2581 .fifosize = { 64, 256, 16, 256 },
2582 };
2583
2584 static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = {
2585 EXYNOS_COMMON_SERIAL_DRV_DATA(),
2586 .fifosize = { 256, 64, 64, 64 },
2587 };
2588
2589 #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data)
2590 #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data)
2591 #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data)
2592
2593 #else
2594 #define EXYNOS4210_SERIAL_DRV_DATA NULL
2595 #define EXYNOS5433_SERIAL_DRV_DATA NULL
2596 #define EXYNOS850_SERIAL_DRV_DATA NULL
2597 #endif
2598
2599 #ifdef CONFIG_ARCH_APPLE
2600 static const struct s3c24xx_serial_drv_data s5l_serial_drv_data = {
2601 .info = {
2602 .name = "Apple S5L UART",
2603 .type = TYPE_APPLE_S5L,
2604 .port_type = PORT_8250,
2605 .fifosize = 16,
2606 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
2607 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
2608 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
2609 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
2610 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
2611 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
2612 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2613 .num_clks = 1,
2614 .clksel_mask = 0,
2615 .clksel_shift = 0,
2616 .ucon_mask = APPLE_S5L_UCON_MASK,
2617 },
2618 .def_cfg = {
2619 .ucon = APPLE_S5L_UCON_DEFAULT,
2620 .ufcon = S3C2410_UFCON_DEFAULT,
2621 },
2622 };
2623 #define S5L_SERIAL_DRV_DATA (&s5l_serial_drv_data)
2624 #else
2625 #define S5L_SERIAL_DRV_DATA NULL
2626 #endif
2627
2628 #if defined(CONFIG_ARCH_ARTPEC)
2629 static const struct s3c24xx_serial_drv_data artpec8_serial_drv_data = {
2630 .info = {
2631 .name = "Axis ARTPEC-8 UART",
2632 .type = TYPE_S3C6400,
2633 .port_type = PORT_S3C6400,
2634 .fifosize = 64,
2635 .has_divslot = 1,
2636 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2637 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2638 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2639 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2640 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2641 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2642 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2643 .num_clks = 1,
2644 .clksel_mask = 0,
2645 .clksel_shift = 0,
2646 },
2647 .def_cfg = {
2648 .ucon = S5PV210_UCON_DEFAULT,
2649 .ufcon = S5PV210_UFCON_DEFAULT,
2650 .has_fracval = 1,
2651 }
2652 };
2653 #define ARTPEC8_SERIAL_DRV_DATA (&artpec8_serial_drv_data)
2654 #else
2655 #define ARTPEC8_SERIAL_DRV_DATA (NULL)
2656 #endif
2657
2658 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2659 {
2660 .name = "s3c6400-uart",
2661 .driver_data = (kernel_ulong_t)S3C6400_SERIAL_DRV_DATA,
2662 }, {
2663 .name = "s5pv210-uart",
2664 .driver_data = (kernel_ulong_t)S5PV210_SERIAL_DRV_DATA,
2665 }, {
2666 .name = "exynos4210-uart",
2667 .driver_data = (kernel_ulong_t)EXYNOS4210_SERIAL_DRV_DATA,
2668 }, {
2669 .name = "exynos5433-uart",
2670 .driver_data = (kernel_ulong_t)EXYNOS5433_SERIAL_DRV_DATA,
2671 }, {
2672 .name = "s5l-uart",
2673 .driver_data = (kernel_ulong_t)S5L_SERIAL_DRV_DATA,
2674 }, {
2675 .name = "exynos850-uart",
2676 .driver_data = (kernel_ulong_t)EXYNOS850_SERIAL_DRV_DATA,
2677 }, {
2678 .name = "artpec8-uart",
2679 .driver_data = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA,
2680 },
2681 { },
2682 };
2683 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2684
2685 #ifdef CONFIG_OF
2686 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2687 { .compatible = "samsung,s3c6400-uart",
2688 .data = S3C6400_SERIAL_DRV_DATA },
2689 { .compatible = "samsung,s5pv210-uart",
2690 .data = S5PV210_SERIAL_DRV_DATA },
2691 { .compatible = "samsung,exynos4210-uart",
2692 .data = EXYNOS4210_SERIAL_DRV_DATA },
2693 { .compatible = "samsung,exynos5433-uart",
2694 .data = EXYNOS5433_SERIAL_DRV_DATA },
2695 { .compatible = "apple,s5l-uart",
2696 .data = S5L_SERIAL_DRV_DATA },
2697 { .compatible = "samsung,exynos850-uart",
2698 .data = EXYNOS850_SERIAL_DRV_DATA },
2699 { .compatible = "axis,artpec8-uart",
2700 .data = ARTPEC8_SERIAL_DRV_DATA },
2701 {},
2702 };
2703 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2704 #endif
2705
2706 static struct platform_driver samsung_serial_driver = {
2707 .probe = s3c24xx_serial_probe,
2708 .remove = s3c24xx_serial_remove,
2709 .id_table = s3c24xx_serial_driver_ids,
2710 .driver = {
2711 .name = "samsung-uart",
2712 .pm = SERIAL_SAMSUNG_PM_OPS,
2713 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2714 },
2715 };
2716
samsung_serial_init(void)2717 static int __init samsung_serial_init(void)
2718 {
2719 int ret;
2720
2721 s3c24xx_serial_register_console();
2722
2723 ret = platform_driver_register(&samsung_serial_driver);
2724 if (ret) {
2725 s3c24xx_serial_unregister_console();
2726 return ret;
2727 }
2728
2729 return 0;
2730 }
2731
samsung_serial_exit(void)2732 static void __exit samsung_serial_exit(void)
2733 {
2734 platform_driver_unregister(&samsung_serial_driver);
2735 s3c24xx_serial_unregister_console();
2736 }
2737
2738 module_init(samsung_serial_init);
2739 module_exit(samsung_serial_exit);
2740
2741 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2742 /*
2743 * Early console.
2744 */
2745
wr_reg_barrier(const struct uart_port * port,u32 reg,u32 val)2746 static void wr_reg_barrier(const struct uart_port *port, u32 reg, u32 val)
2747 {
2748 switch (port->iotype) {
2749 case UPIO_MEM:
2750 writeb(val, portaddr(port, reg));
2751 break;
2752 case UPIO_MEM32:
2753 writel(val, portaddr(port, reg));
2754 break;
2755 }
2756 }
2757
2758 struct samsung_early_console_data {
2759 u32 txfull_mask;
2760 u32 rxfifo_mask;
2761 };
2762
samsung_early_busyuart(const struct uart_port * port)2763 static void samsung_early_busyuart(const struct uart_port *port)
2764 {
2765 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2766 ;
2767 }
2768
samsung_early_busyuart_fifo(const struct uart_port * port)2769 static void samsung_early_busyuart_fifo(const struct uart_port *port)
2770 {
2771 const struct samsung_early_console_data *data = port->private_data;
2772
2773 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2774 ;
2775 }
2776
samsung_early_putc(struct uart_port * port,unsigned char c)2777 static void samsung_early_putc(struct uart_port *port, unsigned char c)
2778 {
2779 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2780 samsung_early_busyuart_fifo(port);
2781 else
2782 samsung_early_busyuart(port);
2783
2784 wr_reg_barrier(port, S3C2410_UTXH, c);
2785 }
2786
samsung_early_write(struct console * con,const char * s,unsigned int n)2787 static void samsung_early_write(struct console *con, const char *s,
2788 unsigned int n)
2789 {
2790 struct earlycon_device *dev = con->data;
2791
2792 uart_console_write(&dev->port, s, n, samsung_early_putc);
2793 }
2794
samsung_early_read(struct console * con,char * s,unsigned int n)2795 static int samsung_early_read(struct console *con, char *s, unsigned int n)
2796 {
2797 struct earlycon_device *dev = con->data;
2798 const struct samsung_early_console_data *data = dev->port.private_data;
2799 int ch, ufstat, num_read = 0;
2800
2801 while (num_read < n) {
2802 ufstat = rd_regl(&dev->port, S3C2410_UFSTAT);
2803 if (!(ufstat & data->rxfifo_mask))
2804 break;
2805 ch = rd_reg(&dev->port, S3C2410_URXH);
2806 if (ch == NO_POLL_CHAR)
2807 break;
2808
2809 s[num_read++] = ch;
2810 }
2811
2812 return num_read;
2813 }
2814
samsung_early_console_setup(struct earlycon_device * device,const char * opt)2815 static int __init samsung_early_console_setup(struct earlycon_device *device,
2816 const char *opt)
2817 {
2818 if (!device->port.membase)
2819 return -ENODEV;
2820
2821 device->con->write = samsung_early_write;
2822 device->con->read = samsung_early_read;
2823 return 0;
2824 }
2825
2826 /* S3C2410 */
2827 static struct samsung_early_console_data s3c2410_early_console_data = {
2828 .txfull_mask = S3C2410_UFSTAT_TXFULL,
2829 .rxfifo_mask = S3C2410_UFSTAT_RXFULL | S3C2410_UFSTAT_RXMASK,
2830 };
2831
s3c2410_early_console_setup(struct earlycon_device * device,const char * opt)2832 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2833 const char *opt)
2834 {
2835 device->port.private_data = &s3c2410_early_console_data;
2836 return samsung_early_console_setup(device, opt);
2837 }
2838
2839 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2840 s3c2410_early_console_setup);
2841
2842 /* S3C2412, S3C2440, S3C64xx */
2843 static struct samsung_early_console_data s3c2440_early_console_data = {
2844 .txfull_mask = S3C2440_UFSTAT_TXFULL,
2845 .rxfifo_mask = S3C2440_UFSTAT_RXFULL | S3C2440_UFSTAT_RXMASK,
2846 };
2847
s3c2440_early_console_setup(struct earlycon_device * device,const char * opt)2848 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2849 const char *opt)
2850 {
2851 device->port.private_data = &s3c2440_early_console_data;
2852 return samsung_early_console_setup(device, opt);
2853 }
2854
2855 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2856 s3c2440_early_console_setup);
2857 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2858 s3c2440_early_console_setup);
2859 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2860 s3c2440_early_console_setup);
2861
2862 /* S5PV210, Exynos */
2863 static struct samsung_early_console_data s5pv210_early_console_data = {
2864 .txfull_mask = S5PV210_UFSTAT_TXFULL,
2865 .rxfifo_mask = S5PV210_UFSTAT_RXFULL | S5PV210_UFSTAT_RXMASK,
2866 };
2867
s5pv210_early_console_setup(struct earlycon_device * device,const char * opt)2868 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2869 const char *opt)
2870 {
2871 device->port.private_data = &s5pv210_early_console_data;
2872 return samsung_early_console_setup(device, opt);
2873 }
2874
2875 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2876 s5pv210_early_console_setup);
2877 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2878 s5pv210_early_console_setup);
2879 OF_EARLYCON_DECLARE(artpec8, "axis,artpec8-uart",
2880 s5pv210_early_console_setup);
2881
2882 /* Apple S5L */
apple_s5l_early_console_setup(struct earlycon_device * device,const char * opt)2883 static int __init apple_s5l_early_console_setup(struct earlycon_device *device,
2884 const char *opt)
2885 {
2886 /* Close enough to S3C2410 for earlycon... */
2887 device->port.private_data = &s3c2410_early_console_data;
2888
2889 #ifdef CONFIG_ARM64
2890 /* ... but we need to override the existing fixmap entry as nGnRnE */
2891 __set_fixmap(FIX_EARLYCON_MEM_BASE, device->port.mapbase,
2892 __pgprot(PROT_DEVICE_nGnRnE));
2893 #endif
2894 return samsung_early_console_setup(device, opt);
2895 }
2896
2897 OF_EARLYCON_DECLARE(s5l, "apple,s5l-uart", apple_s5l_early_console_setup);
2898 #endif
2899
2900 MODULE_ALIAS("platform:samsung-uart");
2901 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2902 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2903 MODULE_LICENSE("GPL v2");
2904