1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * dwc3-pci.c - PCI Specific glue layer
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/slab.h>
14 #include <linux/pci.h>
15 #include <linux/workqueue.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/platform_device.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/gpio/machine.h>
20 #include <linux/acpi.h>
21 #include <linux/delay.h>
22
23 #define PCI_DEVICE_ID_INTEL_BYT 0x0f37
24 #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
25 #define PCI_DEVICE_ID_INTEL_BSW 0x22b7
26 #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
27 #define PCI_DEVICE_ID_INTEL_SPTH 0xa130
28 #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
29 #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
30 #define PCI_DEVICE_ID_INTEL_APL 0x5aaa
31 #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0
32 #define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee
33 #define PCI_DEVICE_ID_INTEL_CMLH 0x06ee
34 #define PCI_DEVICE_ID_INTEL_GLK 0x31aa
35 #define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee
36 #define PCI_DEVICE_ID_INTEL_CNPH 0xa36e
37 #define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0
38 #define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee
39 #define PCI_DEVICE_ID_INTEL_EHL 0x4b7e
40 #define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee
41 #define PCI_DEVICE_ID_INTEL_TGPH 0x43ee
42 #define PCI_DEVICE_ID_INTEL_JSP 0x4dee
43 #define PCI_DEVICE_ID_INTEL_ADL 0x460e
44 #define PCI_DEVICE_ID_INTEL_ADL_PCH 0x51ee
45 #define PCI_DEVICE_ID_INTEL_ADLN 0x465e
46 #define PCI_DEVICE_ID_INTEL_ADLN_PCH 0x54ee
47 #define PCI_DEVICE_ID_INTEL_ADLS 0x7ae1
48 #define PCI_DEVICE_ID_INTEL_RPL 0xa70e
49 #define PCI_DEVICE_ID_INTEL_RPLS 0x7a61
50 #define PCI_DEVICE_ID_INTEL_MTLM 0x7eb1
51 #define PCI_DEVICE_ID_INTEL_MTLP 0x7ec1
52 #define PCI_DEVICE_ID_INTEL_MTL 0x7e7e
53 #define PCI_DEVICE_ID_INTEL_TGL 0x9a15
54 #define PCI_DEVICE_ID_AMD_MR 0x163a
55
56 #define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
57 #define PCI_INTEL_BXT_FUNC_PMU_PWR 4
58 #define PCI_INTEL_BXT_STATE_D0 0
59 #define PCI_INTEL_BXT_STATE_D3 3
60
61 #define GP_RWBAR 1
62 #define GP_RWREG1 0xa0
63 #define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17)
64
65 /**
66 * struct dwc3_pci - Driver private structure
67 * @dwc3: child dwc3 platform_device
68 * @pci: our link to PCI bus
69 * @guid: _DSM GUID
70 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
71 * @wakeup_work: work for asynchronous resume
72 */
73 struct dwc3_pci {
74 struct platform_device *dwc3;
75 struct pci_dev *pci;
76
77 guid_t guid;
78
79 unsigned int has_dsm_for_pm:1;
80 struct work_struct wakeup_work;
81 };
82
83 static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
84 static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
85
86 static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
87 { "reset-gpios", &reset_gpios, 1 },
88 { "cs-gpios", &cs_gpios, 1 },
89 { },
90 };
91
92 static struct gpiod_lookup_table platform_bytcr_gpios = {
93 .dev_id = "0000:00:16.0",
94 .table = {
95 GPIO_LOOKUP("INT33FC:00", 54, "cs", GPIO_ACTIVE_HIGH),
96 GPIO_LOOKUP("INT33FC:02", 14, "reset", GPIO_ACTIVE_HIGH),
97 {}
98 },
99 };
100
dwc3_byt_enable_ulpi_refclock(struct pci_dev * pci)101 static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
102 {
103 void __iomem *reg;
104 u32 value;
105
106 reg = pcim_iomap(pci, GP_RWBAR, 0);
107 if (!reg)
108 return -ENOMEM;
109
110 value = readl(reg + GP_RWREG1);
111 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
112 goto unmap; /* ULPI refclk already enabled */
113
114 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
115 writel(value, reg + GP_RWREG1);
116 /* This comes from the Intel Android x86 tree w/o any explanation */
117 msleep(100);
118 unmap:
119 pcim_iounmap(pci, reg);
120 return 0;
121 }
122
123 static const struct property_entry dwc3_pci_intel_properties[] = {
124 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
125 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
126 {}
127 };
128
129 static const struct property_entry dwc3_pci_intel_phy_charger_detect_properties[] = {
130 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
131 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
132 PROPERTY_ENTRY_BOOL("linux,phy_charger_detect"),
133 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
134 {}
135 };
136
137 static const struct property_entry dwc3_pci_intel_byt_properties[] = {
138 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
139 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
140 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
141 {}
142 };
143
144 static const struct property_entry dwc3_pci_mrfld_properties[] = {
145 PROPERTY_ENTRY_STRING("dr_mode", "otg"),
146 PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"),
147 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
148 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
149 PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"),
150 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
151 {}
152 };
153
154 static const struct property_entry dwc3_pci_amd_properties[] = {
155 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
156 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
157 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
158 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
159 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
160 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
161 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
162 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
163 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
164 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
165 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
166 /* FIXME these quirks should be removed when AMD NL tapes out */
167 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
168 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
169 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
170 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
171 {}
172 };
173
174 static const struct property_entry dwc3_pci_mr_properties[] = {
175 PROPERTY_ENTRY_STRING("dr_mode", "otg"),
176 PROPERTY_ENTRY_BOOL("usb-role-switch"),
177 PROPERTY_ENTRY_STRING("role-switch-default-mode", "host"),
178 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
179 {}
180 };
181
182 static const struct software_node dwc3_pci_intel_swnode = {
183 .properties = dwc3_pci_intel_properties,
184 };
185
186 static const struct software_node dwc3_pci_intel_phy_charger_detect_swnode = {
187 .properties = dwc3_pci_intel_phy_charger_detect_properties,
188 };
189
190 static const struct software_node dwc3_pci_intel_byt_swnode = {
191 .properties = dwc3_pci_intel_byt_properties,
192 };
193
194 static const struct software_node dwc3_pci_intel_mrfld_swnode = {
195 .properties = dwc3_pci_mrfld_properties,
196 };
197
198 static const struct software_node dwc3_pci_amd_swnode = {
199 .properties = dwc3_pci_amd_properties,
200 };
201
202 static const struct software_node dwc3_pci_amd_mr_swnode = {
203 .properties = dwc3_pci_mr_properties,
204 };
205
dwc3_pci_quirks(struct dwc3_pci * dwc,const struct software_node * swnode)206 static int dwc3_pci_quirks(struct dwc3_pci *dwc,
207 const struct software_node *swnode)
208 {
209 struct pci_dev *pdev = dwc->pci;
210
211 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
212 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
213 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M ||
214 pdev->device == PCI_DEVICE_ID_INTEL_EHL) {
215 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
216 dwc->has_dsm_for_pm = true;
217 }
218
219 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
220 struct gpio_desc *gpio;
221 int ret;
222
223 /* On BYT the FW does not always enable the refclock */
224 ret = dwc3_byt_enable_ulpi_refclock(pdev);
225 if (ret)
226 return ret;
227
228 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
229 acpi_dwc3_byt_gpios);
230 if (ret)
231 dev_dbg(&pdev->dev, "failed to add mapping table\n");
232
233 /*
234 * A lot of BYT devices lack ACPI resource entries for
235 * the GPIOs, add a fallback mapping to the reference
236 * design GPIOs which all boards seem to use.
237 */
238 gpiod_add_lookup_table(&platform_bytcr_gpios);
239
240 /*
241 * These GPIOs will turn on the USB2 PHY. Note that we have to
242 * put the gpio descriptors again here because the phy driver
243 * might want to grab them, too.
244 */
245 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
246 if (IS_ERR(gpio))
247 return PTR_ERR(gpio);
248
249 gpiod_set_value_cansleep(gpio, 1);
250 gpiod_put(gpio);
251
252 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
253 if (IS_ERR(gpio))
254 return PTR_ERR(gpio);
255
256 if (gpio) {
257 gpiod_set_value_cansleep(gpio, 1);
258 gpiod_put(gpio);
259 usleep_range(10000, 11000);
260 }
261
262 /*
263 * Make the pdev name predictable (only 1 DWC3 on BYT)
264 * and patch the phy dev-name into the lookup table so
265 * that the phy-driver can get the GPIOs.
266 */
267 dwc->dwc3->id = PLATFORM_DEVID_NONE;
268 platform_bytcr_gpios.dev_id = "dwc3.ulpi";
269
270 /*
271 * Some Android tablets with a Crystal Cove PMIC
272 * (INT33FD), rely on the TUSB1211 phy for charger
273 * detection. These can be identified by them _not_
274 * using the standard ACPI battery and ac drivers.
275 */
276 if (acpi_dev_present("INT33FD", "1", 2) &&
277 acpi_quirk_skip_acpi_ac_and_battery()) {
278 dev_info(&pdev->dev, "Using TUSB1211 phy for charger detection\n");
279 swnode = &dwc3_pci_intel_phy_charger_detect_swnode;
280 }
281 }
282 }
283
284 return device_add_software_node(&dwc->dwc3->dev, swnode);
285 }
286
287 #ifdef CONFIG_PM
dwc3_pci_resume_work(struct work_struct * work)288 static void dwc3_pci_resume_work(struct work_struct *work)
289 {
290 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
291 struct platform_device *dwc3 = dwc->dwc3;
292 int ret;
293
294 ret = pm_runtime_get_sync(&dwc3->dev);
295 if (ret < 0) {
296 pm_runtime_put_sync_autosuspend(&dwc3->dev);
297 return;
298 }
299
300 pm_runtime_mark_last_busy(&dwc3->dev);
301 pm_runtime_put_sync_autosuspend(&dwc3->dev);
302 }
303 #endif
304
dwc3_pci_probe(struct pci_dev * pci,const struct pci_device_id * id)305 static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
306 {
307 struct dwc3_pci *dwc;
308 struct resource res[2];
309 int ret;
310 struct device *dev = &pci->dev;
311
312 ret = pcim_enable_device(pci);
313 if (ret) {
314 dev_err(dev, "failed to enable pci device\n");
315 return -ENODEV;
316 }
317
318 pci_set_master(pci);
319
320 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
321 if (!dwc)
322 return -ENOMEM;
323
324 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
325 if (!dwc->dwc3)
326 return -ENOMEM;
327
328 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
329
330 res[0].start = pci_resource_start(pci, 0);
331 res[0].end = pci_resource_end(pci, 0);
332 res[0].name = "dwc_usb3";
333 res[0].flags = IORESOURCE_MEM;
334
335 res[1].start = pci->irq;
336 res[1].name = "dwc_usb3";
337 res[1].flags = IORESOURCE_IRQ;
338
339 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
340 if (ret) {
341 dev_err(dev, "couldn't add resources to dwc3 device\n");
342 goto err;
343 }
344
345 dwc->pci = pci;
346 dwc->dwc3->dev.parent = dev;
347 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
348
349 ret = dwc3_pci_quirks(dwc, (void *)id->driver_data);
350 if (ret)
351 goto err;
352
353 ret = platform_device_add(dwc->dwc3);
354 if (ret) {
355 dev_err(dev, "failed to register dwc3 device\n");
356 goto err;
357 }
358
359 device_init_wakeup(dev, true);
360 pci_set_drvdata(pci, dwc);
361 pm_runtime_put(dev);
362 #ifdef CONFIG_PM
363 INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
364 #endif
365
366 return 0;
367 err:
368 device_remove_software_node(&dwc->dwc3->dev);
369 platform_device_put(dwc->dwc3);
370 return ret;
371 }
372
dwc3_pci_remove(struct pci_dev * pci)373 static void dwc3_pci_remove(struct pci_dev *pci)
374 {
375 struct dwc3_pci *dwc = pci_get_drvdata(pci);
376 struct pci_dev *pdev = dwc->pci;
377
378 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT)
379 gpiod_remove_lookup_table(&platform_bytcr_gpios);
380 #ifdef CONFIG_PM
381 cancel_work_sync(&dwc->wakeup_work);
382 #endif
383 device_init_wakeup(&pci->dev, false);
384 pm_runtime_get(&pci->dev);
385 device_remove_software_node(&dwc->dwc3->dev);
386 platform_device_unregister(dwc->dwc3);
387 }
388
389 static const struct pci_device_id dwc3_pci_id_table[] = {
390 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW),
391 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
392
393 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT),
394 (kernel_ulong_t) &dwc3_pci_intel_byt_swnode, },
395
396 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD),
397 (kernel_ulong_t) &dwc3_pci_intel_mrfld_swnode, },
398
399 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP),
400 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
401
402 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH),
403 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
404
405 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP),
406 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
407
408 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH),
409 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
410
411 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT),
412 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
413
414 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M),
415 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
416
417 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL),
418 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
419
420 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP),
421 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
422
423 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK),
424 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
425
426 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP),
427 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
428
429 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH),
430 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
431
432 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV),
433 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
434
435 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP),
436 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
437
438 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHL),
439 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
440
441 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP),
442 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
443
444 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPH),
445 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
446
447 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP),
448 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
449
450 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL),
451 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
452
453 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_PCH),
454 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
455
456 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLN),
457 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
458
459 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLN_PCH),
460 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
461
462 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLS),
463 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
464
465 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPL),
466 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
467
468 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPLS),
469 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
470
471 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTLM),
472 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
473
474 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTLP),
475 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
476
477 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL),
478 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
479
480 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL),
481 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
482
483 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB),
484 (kernel_ulong_t) &dwc3_pci_amd_swnode, },
485
486 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_MR),
487 (kernel_ulong_t)&dwc3_pci_amd_mr_swnode, },
488
489 { } /* Terminating Entry */
490 };
491 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
492
493 #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
dwc3_pci_dsm(struct dwc3_pci * dwc,int param)494 static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
495 {
496 union acpi_object *obj;
497 union acpi_object tmp;
498 union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
499
500 if (!dwc->has_dsm_for_pm)
501 return 0;
502
503 tmp.type = ACPI_TYPE_INTEGER;
504 tmp.integer.value = param;
505
506 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
507 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
508 if (!obj) {
509 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
510 return -EIO;
511 }
512
513 ACPI_FREE(obj);
514
515 return 0;
516 }
517 #endif /* CONFIG_PM || CONFIG_PM_SLEEP */
518
519 #ifdef CONFIG_PM
dwc3_pci_runtime_suspend(struct device * dev)520 static int dwc3_pci_runtime_suspend(struct device *dev)
521 {
522 struct dwc3_pci *dwc = dev_get_drvdata(dev);
523
524 if (device_can_wakeup(dev))
525 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
526
527 return -EBUSY;
528 }
529
dwc3_pci_runtime_resume(struct device * dev)530 static int dwc3_pci_runtime_resume(struct device *dev)
531 {
532 struct dwc3_pci *dwc = dev_get_drvdata(dev);
533 int ret;
534
535 ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
536 if (ret)
537 return ret;
538
539 queue_work(pm_wq, &dwc->wakeup_work);
540
541 return 0;
542 }
543 #endif /* CONFIG_PM */
544
545 #ifdef CONFIG_PM_SLEEP
dwc3_pci_suspend(struct device * dev)546 static int dwc3_pci_suspend(struct device *dev)
547 {
548 struct dwc3_pci *dwc = dev_get_drvdata(dev);
549
550 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
551 }
552
dwc3_pci_resume(struct device * dev)553 static int dwc3_pci_resume(struct device *dev)
554 {
555 struct dwc3_pci *dwc = dev_get_drvdata(dev);
556
557 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
558 }
559 #endif /* CONFIG_PM_SLEEP */
560
561 static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
562 SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
563 SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
564 NULL)
565 };
566
567 static struct pci_driver dwc3_pci_driver = {
568 .name = "dwc3-pci",
569 .id_table = dwc3_pci_id_table,
570 .probe = dwc3_pci_probe,
571 .remove = dwc3_pci_remove,
572 .driver = {
573 .pm = &dwc3_pci_dev_pm_ops,
574 }
575 };
576
577 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
578 MODULE_LICENSE("GPL v2");
579 MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
580
581 module_pci_driver(dwc3_pci_driver);
582