1 // SPDX-License-Identifier: GPL-1.0+
2 /*
3 * OHCI HCD (Host Controller Driver) for USB.
4 *
5 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
6 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
7 * (C) Copyright 2002 Hewlett-Packard Company
8 *
9 * Bus Glue for pxa27x
10 *
11 * Written by Christopher Hoover <ch@hpl.hp.com>
12 * Based on fragments of previous driver by Russell King et al.
13 *
14 * Modified for LH7A404 from ohci-sa1111.c
15 * by Durgesh Pattamatta <pattamattad@sharpsec.com>
16 *
17 * Modified for pxa27x from ohci-lh7a404.c
18 * by Nick Bane <nick@cecomputing.co.uk> 26-8-2004
19 *
20 * This file is licenced under the GPL.
21 */
22
23 #include <linux/clk.h>
24 #include <linux/device.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/io.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/of_platform.h>
30 #include <linux/of_gpio.h>
31 #include <linux/platform_data/usb-ohci-pxa27x.h>
32 #include <linux/platform_device.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/signal.h>
35 #include <linux/usb.h>
36 #include <linux/usb/hcd.h>
37 #include <linux/usb/otg.h>
38 #include <linux/soc/pxa/cpu.h>
39
40 #include "ohci.h"
41
42 #define DRIVER_DESC "OHCI PXA27x/PXA3x driver"
43
44 /*
45 * UHC: USB Host Controller (OHCI-like) register definitions
46 */
47 #define UHCREV (0x0000) /* UHC HCI Spec Revision */
48 #define UHCHCON (0x0004) /* UHC Host Control Register */
49 #define UHCCOMS (0x0008) /* UHC Command Status Register */
50 #define UHCINTS (0x000C) /* UHC Interrupt Status Register */
51 #define UHCINTE (0x0010) /* UHC Interrupt Enable */
52 #define UHCINTD (0x0014) /* UHC Interrupt Disable */
53 #define UHCHCCA (0x0018) /* UHC Host Controller Comm. Area */
54 #define UHCPCED (0x001C) /* UHC Period Current Endpt Descr */
55 #define UHCCHED (0x0020) /* UHC Control Head Endpt Descr */
56 #define UHCCCED (0x0024) /* UHC Control Current Endpt Descr */
57 #define UHCBHED (0x0028) /* UHC Bulk Head Endpt Descr */
58 #define UHCBCED (0x002C) /* UHC Bulk Current Endpt Descr */
59 #define UHCDHEAD (0x0030) /* UHC Done Head */
60 #define UHCFMI (0x0034) /* UHC Frame Interval */
61 #define UHCFMR (0x0038) /* UHC Frame Remaining */
62 #define UHCFMN (0x003C) /* UHC Frame Number */
63 #define UHCPERS (0x0040) /* UHC Periodic Start */
64 #define UHCLS (0x0044) /* UHC Low Speed Threshold */
65
66 #define UHCRHDA (0x0048) /* UHC Root Hub Descriptor A */
67 #define UHCRHDA_NOCP (1 << 12) /* No over current protection */
68 #define UHCRHDA_OCPM (1 << 11) /* Over Current Protection Mode */
69 #define UHCRHDA_POTPGT(x) \
70 (((x) & 0xff) << 24) /* Power On To Power Good Time */
71
72 #define UHCRHDB (0x004C) /* UHC Root Hub Descriptor B */
73 #define UHCRHS (0x0050) /* UHC Root Hub Status */
74 #define UHCRHPS1 (0x0054) /* UHC Root Hub Port 1 Status */
75 #define UHCRHPS2 (0x0058) /* UHC Root Hub Port 2 Status */
76 #define UHCRHPS3 (0x005C) /* UHC Root Hub Port 3 Status */
77
78 #define UHCSTAT (0x0060) /* UHC Status Register */
79 #define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
80 #define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
81 #define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
82 #define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
83 #define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
84 #define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
85 #define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
86 #define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
87 #define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
88
89 #define UHCHR (0x0064) /* UHC Reset Register */
90 #define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
91 #define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
92 #define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
93 #define UHCHR_PCPL (1 << 7) /* Power control polarity low */
94 #define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
95 #define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
96 #define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
97 #define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
98 #define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
99 #define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
100 #define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
101
102 #define UHCHIE (0x0068) /* UHC Interrupt Enable Register*/
103 #define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
104 #define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
105 #define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
106 #define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
107 #define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
108 Interrupt Enable*/
109 #define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
110 #define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
111
112 #define UHCHIT (0x006C) /* UHC Interrupt Test register */
113
114 #define PXA_UHC_MAX_PORTNUM 3
115
116 static struct hc_driver __read_mostly ohci_pxa27x_hc_driver;
117
118 struct pxa27x_ohci {
119 struct clk *clk;
120 void __iomem *mmio_base;
121 struct regulator *vbus[3];
122 bool vbus_enabled[3];
123 };
124
125 #define to_pxa27x_ohci(hcd) (struct pxa27x_ohci *)(hcd_to_ohci(hcd)->priv)
126
127 /*
128 PMM_NPS_MODE -- PMM Non-power switching mode
129 Ports are powered continuously.
130
131 PMM_GLOBAL_MODE -- PMM global switching mode
132 All ports are powered at the same time.
133
134 PMM_PERPORT_MODE -- PMM per port switching mode
135 Ports are powered individually.
136 */
pxa27x_ohci_select_pmm(struct pxa27x_ohci * pxa_ohci,int mode)137 static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *pxa_ohci, int mode)
138 {
139 uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);
140 uint32_t uhcrhdb = __raw_readl(pxa_ohci->mmio_base + UHCRHDB);
141
142 switch (mode) {
143 case PMM_NPS_MODE:
144 uhcrhda |= RH_A_NPS;
145 break;
146 case PMM_GLOBAL_MODE:
147 uhcrhda &= ~(RH_A_NPS | RH_A_PSM);
148 break;
149 case PMM_PERPORT_MODE:
150 uhcrhda &= ~(RH_A_NPS);
151 uhcrhda |= RH_A_PSM;
152
153 /* Set port power control mask bits, only 3 ports. */
154 uhcrhdb |= (0x7<<17);
155 break;
156 default:
157 printk( KERN_ERR
158 "Invalid mode %d, set to non-power switch mode.\n",
159 mode );
160
161 uhcrhda |= RH_A_NPS;
162 }
163
164 __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);
165 __raw_writel(uhcrhdb, pxa_ohci->mmio_base + UHCRHDB);
166 return 0;
167 }
168
pxa27x_ohci_set_vbus_power(struct pxa27x_ohci * pxa_ohci,unsigned int port,bool enable)169 static int pxa27x_ohci_set_vbus_power(struct pxa27x_ohci *pxa_ohci,
170 unsigned int port, bool enable)
171 {
172 struct regulator *vbus = pxa_ohci->vbus[port];
173 int ret = 0;
174
175 if (IS_ERR_OR_NULL(vbus))
176 return 0;
177
178 if (enable && !pxa_ohci->vbus_enabled[port])
179 ret = regulator_enable(vbus);
180 else if (!enable && pxa_ohci->vbus_enabled[port])
181 ret = regulator_disable(vbus);
182
183 if (ret < 0)
184 return ret;
185
186 pxa_ohci->vbus_enabled[port] = enable;
187
188 return 0;
189 }
190
pxa27x_ohci_hub_control(struct usb_hcd * hcd,u16 typeReq,u16 wValue,u16 wIndex,char * buf,u16 wLength)191 static int pxa27x_ohci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
192 u16 wIndex, char *buf, u16 wLength)
193 {
194 struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
195 int ret;
196
197 switch (typeReq) {
198 case SetPortFeature:
199 case ClearPortFeature:
200 if (!wIndex || wIndex > 3)
201 return -EPIPE;
202
203 if (wValue != USB_PORT_FEAT_POWER)
204 break;
205
206 ret = pxa27x_ohci_set_vbus_power(pxa_ohci, wIndex - 1,
207 typeReq == SetPortFeature);
208 if (ret)
209 return ret;
210 break;
211 }
212
213 return ohci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
214 }
215 /*-------------------------------------------------------------------------*/
216
pxa27x_setup_hc(struct pxa27x_ohci * pxa_ohci,struct pxaohci_platform_data * inf)217 static inline void pxa27x_setup_hc(struct pxa27x_ohci *pxa_ohci,
218 struct pxaohci_platform_data *inf)
219 {
220 uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);
221 uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);
222
223 if (inf->flags & ENABLE_PORT1)
224 uhchr &= ~UHCHR_SSEP1;
225
226 if (inf->flags & ENABLE_PORT2)
227 uhchr &= ~UHCHR_SSEP2;
228
229 if (inf->flags & ENABLE_PORT3)
230 uhchr &= ~UHCHR_SSEP3;
231
232 if (inf->flags & POWER_CONTROL_LOW)
233 uhchr |= UHCHR_PCPL;
234
235 if (inf->flags & POWER_SENSE_LOW)
236 uhchr |= UHCHR_PSPL;
237
238 if (inf->flags & NO_OC_PROTECTION)
239 uhcrhda |= UHCRHDA_NOCP;
240 else
241 uhcrhda &= ~UHCRHDA_NOCP;
242
243 if (inf->flags & OC_MODE_PERPORT)
244 uhcrhda |= UHCRHDA_OCPM;
245 else
246 uhcrhda &= ~UHCRHDA_OCPM;
247
248 if (inf->power_on_delay) {
249 uhcrhda &= ~UHCRHDA_POTPGT(0xff);
250 uhcrhda |= UHCRHDA_POTPGT(inf->power_on_delay / 2);
251 }
252
253 __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
254 __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);
255 }
256
pxa27x_reset_hc(struct pxa27x_ohci * pxa_ohci)257 static inline void pxa27x_reset_hc(struct pxa27x_ohci *pxa_ohci)
258 {
259 uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);
260
261 __raw_writel(uhchr | UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);
262 udelay(11);
263 __raw_writel(uhchr & ~UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);
264 }
265
266 #ifdef CONFIG_PXA27x
267 extern void pxa27x_clear_otgph(void);
268 #else
269 #define pxa27x_clear_otgph() do {} while (0)
270 #endif
271
pxa27x_start_hc(struct pxa27x_ohci * pxa_ohci,struct device * dev)272 static int pxa27x_start_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev)
273 {
274 int retval;
275 struct pxaohci_platform_data *inf;
276 uint32_t uhchr;
277
278 inf = dev_get_platdata(dev);
279
280 retval = clk_prepare_enable(pxa_ohci->clk);
281 if (retval)
282 return retval;
283
284 pxa27x_reset_hc(pxa_ohci);
285
286 uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) | UHCHR_FSBIR;
287 __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
288
289 while (__raw_readl(pxa_ohci->mmio_base + UHCHR) & UHCHR_FSBIR)
290 cpu_relax();
291
292 pxa27x_setup_hc(pxa_ohci, inf);
293
294 if (inf->init)
295 retval = inf->init(dev);
296
297 if (retval < 0) {
298 clk_disable_unprepare(pxa_ohci->clk);
299 return retval;
300 }
301
302 uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
303 __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
304 __raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, pxa_ohci->mmio_base + UHCHIE);
305
306 /* Clear any OTG Pin Hold */
307 pxa27x_clear_otgph();
308 return 0;
309 }
310
pxa27x_stop_hc(struct pxa27x_ohci * pxa_ohci,struct device * dev)311 static void pxa27x_stop_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev)
312 {
313 struct pxaohci_platform_data *inf;
314 uint32_t uhccoms;
315
316 inf = dev_get_platdata(dev);
317
318 if (inf->exit)
319 inf->exit(dev);
320
321 pxa27x_reset_hc(pxa_ohci);
322
323 /* Host Controller Reset */
324 uhccoms = __raw_readl(pxa_ohci->mmio_base + UHCCOMS) | 0x01;
325 __raw_writel(uhccoms, pxa_ohci->mmio_base + UHCCOMS);
326 udelay(10);
327
328 clk_disable_unprepare(pxa_ohci->clk);
329 }
330
331 #ifdef CONFIG_OF
332 static const struct of_device_id pxa_ohci_dt_ids[] = {
333 { .compatible = "marvell,pxa-ohci" },
334 { }
335 };
336
337 MODULE_DEVICE_TABLE(of, pxa_ohci_dt_ids);
338
ohci_pxa_of_init(struct platform_device * pdev)339 static int ohci_pxa_of_init(struct platform_device *pdev)
340 {
341 struct device_node *np = pdev->dev.of_node;
342 struct pxaohci_platform_data *pdata;
343 u32 tmp;
344 int ret;
345
346 if (!np)
347 return 0;
348
349 /* Right now device-tree probed devices don't get dma_mask set.
350 * Since shared usb code relies on it, set it here for now.
351 * Once we have dma capability bindings this can go away.
352 */
353 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
354 if (ret)
355 return ret;
356
357 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
358 if (!pdata)
359 return -ENOMEM;
360
361 if (of_property_read_bool(np, "marvell,enable-port1"))
362 pdata->flags |= ENABLE_PORT1;
363 if (of_property_read_bool(np, "marvell,enable-port2"))
364 pdata->flags |= ENABLE_PORT2;
365 if (of_property_read_bool(np, "marvell,enable-port3"))
366 pdata->flags |= ENABLE_PORT3;
367 if (of_property_read_bool(np, "marvell,port-sense-low"))
368 pdata->flags |= POWER_SENSE_LOW;
369 if (of_property_read_bool(np, "marvell,power-control-low"))
370 pdata->flags |= POWER_CONTROL_LOW;
371 if (of_property_read_bool(np, "marvell,no-oc-protection"))
372 pdata->flags |= NO_OC_PROTECTION;
373 if (of_property_read_bool(np, "marvell,oc-mode-perport"))
374 pdata->flags |= OC_MODE_PERPORT;
375 if (!of_property_read_u32(np, "marvell,power-on-delay", &tmp))
376 pdata->power_on_delay = tmp;
377 if (!of_property_read_u32(np, "marvell,port-mode", &tmp))
378 pdata->port_mode = tmp;
379 if (!of_property_read_u32(np, "marvell,power-budget", &tmp))
380 pdata->power_budget = tmp;
381
382 pdev->dev.platform_data = pdata;
383
384 return 0;
385 }
386 #else
ohci_pxa_of_init(struct platform_device * pdev)387 static int ohci_pxa_of_init(struct platform_device *pdev)
388 {
389 return 0;
390 }
391 #endif
392
393 /*-------------------------------------------------------------------------*/
394
395 /* configure so an HC device and id are always provided */
396 /* always called with process context; sleeping is OK */
397
398
399 /**
400 * ohci_hcd_pxa27x_probe - initialize pxa27x-based HCDs
401 * @pdev: USB Host controller to probe
402 *
403 * Context: task context, might sleep
404 *
405 * Allocates basic resources for this USB host controller, and
406 * then invokes the start() method for the HCD associated with it
407 * through the hotplug entry's driver_data.
408 */
ohci_hcd_pxa27x_probe(struct platform_device * pdev)409 static int ohci_hcd_pxa27x_probe(struct platform_device *pdev)
410 {
411 int retval, irq;
412 struct usb_hcd *hcd;
413 struct pxaohci_platform_data *inf;
414 struct pxa27x_ohci *pxa_ohci;
415 struct ohci_hcd *ohci;
416 struct resource *r;
417 struct clk *usb_clk;
418 unsigned int i;
419
420 retval = ohci_pxa_of_init(pdev);
421 if (retval)
422 return retval;
423
424 inf = dev_get_platdata(&pdev->dev);
425
426 if (!inf)
427 return -ENODEV;
428
429 irq = platform_get_irq(pdev, 0);
430 if (irq < 0) {
431 pr_err("no resource of IORESOURCE_IRQ");
432 return irq;
433 }
434
435 usb_clk = devm_clk_get(&pdev->dev, NULL);
436 if (IS_ERR(usb_clk))
437 return PTR_ERR(usb_clk);
438
439 hcd = usb_create_hcd(&ohci_pxa27x_hc_driver, &pdev->dev, "pxa27x");
440 if (!hcd)
441 return -ENOMEM;
442
443 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
444 hcd->regs = devm_ioremap_resource(&pdev->dev, r);
445 if (IS_ERR(hcd->regs)) {
446 retval = PTR_ERR(hcd->regs);
447 goto err;
448 }
449 hcd->rsrc_start = r->start;
450 hcd->rsrc_len = resource_size(r);
451
452 /* initialize "struct pxa27x_ohci" */
453 pxa_ohci = to_pxa27x_ohci(hcd);
454 pxa_ohci->clk = usb_clk;
455 pxa_ohci->mmio_base = (void __iomem *)hcd->regs;
456
457 for (i = 0; i < 3; ++i) {
458 char name[6];
459
460 if (!(inf->flags & (ENABLE_PORT1 << i)))
461 continue;
462
463 sprintf(name, "vbus%u", i + 1);
464 pxa_ohci->vbus[i] = devm_regulator_get(&pdev->dev, name);
465 }
466
467 retval = pxa27x_start_hc(pxa_ohci, &pdev->dev);
468 if (retval < 0) {
469 pr_debug("pxa27x_start_hc failed");
470 goto err;
471 }
472
473 /* Select Power Management Mode */
474 pxa27x_ohci_select_pmm(pxa_ohci, inf->port_mode);
475
476 if (inf->power_budget)
477 hcd->power_budget = inf->power_budget;
478
479 /* The value of NDP in roothub_a is incorrect on this hardware */
480 ohci = hcd_to_ohci(hcd);
481 ohci->num_ports = 3;
482
483 retval = usb_add_hcd(hcd, irq, 0);
484 if (retval == 0) {
485 device_wakeup_enable(hcd->self.controller);
486 return retval;
487 }
488
489 pxa27x_stop_hc(pxa_ohci, &pdev->dev);
490 err:
491 usb_put_hcd(hcd);
492 return retval;
493 }
494
495
496 /* may be called without controller electrically present */
497 /* may be called with controller, bus, and devices active */
498
499 /**
500 * ohci_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs
501 * @pdev: USB Host Controller being removed
502 *
503 * Context: task context, might sleep
504 *
505 * Reverses the effect of ohci_hcd_pxa27x_probe(), first invoking
506 * the HCD's stop() method. It is always called from a thread
507 * context, normally "rmmod", "apmd", or something similar.
508 */
ohci_hcd_pxa27x_remove(struct platform_device * pdev)509 static int ohci_hcd_pxa27x_remove(struct platform_device *pdev)
510 {
511 struct usb_hcd *hcd = platform_get_drvdata(pdev);
512 struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
513 unsigned int i;
514
515 usb_remove_hcd(hcd);
516 pxa27x_stop_hc(pxa_ohci, &pdev->dev);
517
518 for (i = 0; i < 3; ++i)
519 pxa27x_ohci_set_vbus_power(pxa_ohci, i, false);
520
521 usb_put_hcd(hcd);
522 return 0;
523 }
524
525 /*-------------------------------------------------------------------------*/
526
527 #ifdef CONFIG_PM
ohci_hcd_pxa27x_drv_suspend(struct device * dev)528 static int ohci_hcd_pxa27x_drv_suspend(struct device *dev)
529 {
530 struct usb_hcd *hcd = dev_get_drvdata(dev);
531 struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
532 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
533 bool do_wakeup = device_may_wakeup(dev);
534 int ret;
535
536
537 if (time_before(jiffies, ohci->next_statechange))
538 msleep(5);
539 ohci->next_statechange = jiffies;
540
541 ret = ohci_suspend(hcd, do_wakeup);
542 if (ret)
543 return ret;
544
545 pxa27x_stop_hc(pxa_ohci, dev);
546 return ret;
547 }
548
ohci_hcd_pxa27x_drv_resume(struct device * dev)549 static int ohci_hcd_pxa27x_drv_resume(struct device *dev)
550 {
551 struct usb_hcd *hcd = dev_get_drvdata(dev);
552 struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
553 struct pxaohci_platform_data *inf = dev_get_platdata(dev);
554 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
555 int status;
556
557 if (time_before(jiffies, ohci->next_statechange))
558 msleep(5);
559 ohci->next_statechange = jiffies;
560
561 status = pxa27x_start_hc(pxa_ohci, dev);
562 if (status < 0)
563 return status;
564
565 /* Select Power Management Mode */
566 pxa27x_ohci_select_pmm(pxa_ohci, inf->port_mode);
567
568 ohci_resume(hcd, false);
569 return 0;
570 }
571
572 static const struct dev_pm_ops ohci_hcd_pxa27x_pm_ops = {
573 .suspend = ohci_hcd_pxa27x_drv_suspend,
574 .resume = ohci_hcd_pxa27x_drv_resume,
575 };
576 #endif
577
578 static struct platform_driver ohci_hcd_pxa27x_driver = {
579 .probe = ohci_hcd_pxa27x_probe,
580 .remove = ohci_hcd_pxa27x_remove,
581 .shutdown = usb_hcd_platform_shutdown,
582 .driver = {
583 .name = "pxa27x-ohci",
584 .of_match_table = of_match_ptr(pxa_ohci_dt_ids),
585 #ifdef CONFIG_PM
586 .pm = &ohci_hcd_pxa27x_pm_ops,
587 #endif
588 },
589 };
590
591 static const struct ohci_driver_overrides pxa27x_overrides __initconst = {
592 .extra_priv_size = sizeof(struct pxa27x_ohci),
593 };
594
ohci_pxa27x_init(void)595 static int __init ohci_pxa27x_init(void)
596 {
597 if (usb_disabled())
598 return -ENODEV;
599
600 ohci_init_driver(&ohci_pxa27x_hc_driver, &pxa27x_overrides);
601 ohci_pxa27x_hc_driver.hub_control = pxa27x_ohci_hub_control;
602
603 return platform_driver_register(&ohci_hcd_pxa27x_driver);
604 }
605 module_init(ohci_pxa27x_init);
606
ohci_pxa27x_cleanup(void)607 static void __exit ohci_pxa27x_cleanup(void)
608 {
609 platform_driver_unregister(&ohci_hcd_pxa27x_driver);
610 }
611 module_exit(ohci_pxa27x_cleanup);
612
613 MODULE_DESCRIPTION(DRIVER_DESC);
614 MODULE_LICENSE("GPL");
615 MODULE_ALIAS("platform:pxa27x-ohci");
616