1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * AMD ALSA SoC PDM Driver
4 *
5 * Copyright (C) 2022 Advanced Micro Devices, Inc. All rights reserved.
6 */
7
8 #include <sound/acp63_chip_offset_byte.h>
9
10 #define ACP_DEVICE_ID 0x15E2
11 #define ACP63_REG_START 0x1240000
12 #define ACP63_REG_END 0x1250200
13 #define ACP63_DEVS 3
14
15 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001
16 #define ACP_PGFSM_CNTL_POWER_ON_MASK 1
17 #define ACP_PGFSM_CNTL_POWER_OFF_MASK 0
18 #define ACP_PGFSM_STATUS_MASK 3
19 #define ACP_POWERED_ON 0
20 #define ACP_POWER_ON_IN_PROGRESS 1
21 #define ACP_POWERED_OFF 2
22 #define ACP_POWER_OFF_IN_PROGRESS 3
23
24 #define ACP_ERROR_MASK 0x20000000
25 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
26 #define PDM_DMA_STAT 0x10
27
28 #define PDM_DMA_INTR_MASK 0x10000
29 #define ACP_ERROR_STAT 29
30 #define PDM_DECIMATION_FACTOR 2
31 #define ACP_PDM_CLK_FREQ_MASK 7
32 #define ACP_WOV_GAIN_CONTROL GENMASK(4, 3)
33 #define ACP_PDM_ENABLE 1
34 #define ACP_PDM_DISABLE 0
35 #define ACP_PDM_DMA_EN_STATUS 2
36 #define TWO_CH 2
37 #define DELAY_US 5
38 #define ACP_COUNTER 20000
39
40 #define ACP_SRAM_PTE_OFFSET 0x03800000
41 #define PAGE_SIZE_4K_ENABLE 2
42 #define PDM_PTE_OFFSET 0
43 #define PDM_MEM_WINDOW_START 0x4000000
44
45 #define CAPTURE_MIN_NUM_PERIODS 4
46 #define CAPTURE_MAX_NUM_PERIODS 4
47 #define CAPTURE_MAX_PERIOD_SIZE 8192
48 #define CAPTURE_MIN_PERIOD_SIZE 4096
49
50 #define MAX_BUFFER (CAPTURE_MAX_PERIOD_SIZE * CAPTURE_MAX_NUM_PERIODS)
51 #define MIN_BUFFER MAX_BUFFER
52
53 /* time in ms for runtime suspend delay */
54 #define ACP_SUSPEND_DELAY_MS 2000
55
56 #define ACP63_DMIC_ADDR 2
57 #define ACP63_PDM_MODE_DEVS 3
58 #define ACP63_PDM_DEV_MASK 1
59 #define ACP_DMIC_DEV 2
60
61 enum acp_config {
62 ACP_CONFIG_0 = 0,
63 ACP_CONFIG_1,
64 ACP_CONFIG_2,
65 ACP_CONFIG_3,
66 ACP_CONFIG_4,
67 ACP_CONFIG_5,
68 ACP_CONFIG_6,
69 ACP_CONFIG_7,
70 ACP_CONFIG_8,
71 ACP_CONFIG_9,
72 ACP_CONFIG_10,
73 ACP_CONFIG_11,
74 ACP_CONFIG_12,
75 ACP_CONFIG_13,
76 ACP_CONFIG_14,
77 ACP_CONFIG_15,
78 };
79
80 struct pdm_stream_instance {
81 u16 num_pages;
82 u16 channels;
83 dma_addr_t dma_addr;
84 u64 bytescount;
85 void __iomem *acp63_base;
86 };
87
88 struct pdm_dev_data {
89 u32 pdm_irq;
90 void __iomem *acp63_base;
91 struct mutex *acp_lock;
92 struct snd_pcm_substream *capture_stream;
93 };
94
acp63_readl(void __iomem * base_addr)95 static inline u32 acp63_readl(void __iomem *base_addr)
96 {
97 return readl(base_addr);
98 }
99
acp63_writel(u32 val,void __iomem * base_addr)100 static inline void acp63_writel(u32 val, void __iomem *base_addr)
101 {
102 writel(val, base_addr);
103 }
104
105 struct acp63_dev_data {
106 void __iomem *acp63_base;
107 struct resource *res;
108 struct platform_device *pdev[ACP63_DEVS];
109 struct mutex acp_lock; /* protect shared registers */
110 u16 pdev_mask;
111 u16 pdev_count;
112 u16 pdm_dev_index;
113 };
114