1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // rt5682s.c -- RT5682I-VS ALSA SoC audio component driver
4 //
5 // Copyright 2021 Realtek Semiconductor Corp.
6 // Author: Derek Fang <derek.fang@realtek.com>
7 //
8
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/pm.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/i2c.h>
16 #include <linux/platform_device.h>
17 #include <linux/spi/spi.h>
18 #include <linux/acpi.h>
19 #include <linux/gpio.h>
20 #include <linux/of_gpio.h>
21 #include <linux/mutex.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/jack.h>
26 #include <sound/soc.h>
27 #include <sound/soc-dapm.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
30 #include <sound/rt5682s.h>
31
32 #include "rt5682s.h"
33
34 #define DEVICE_ID 0x6749
35
36 static const struct rt5682s_platform_data i2s_default_platform_data = {
37 .dmic1_data_pin = RT5682S_DMIC1_DATA_GPIO2,
38 .dmic1_clk_pin = RT5682S_DMIC1_CLK_GPIO3,
39 .jd_src = RT5682S_JD1,
40 .dai_clk_names[RT5682S_DAI_WCLK_IDX] = "rt5682-dai-wclk",
41 .dai_clk_names[RT5682S_DAI_BCLK_IDX] = "rt5682-dai-bclk",
42 };
43
44 static const char *rt5682s_supply_names[RT5682S_NUM_SUPPLIES] = {
45 [RT5682S_SUPPLY_AVDD] = "AVDD",
46 [RT5682S_SUPPLY_MICVDD] = "MICVDD",
47 [RT5682S_SUPPLY_DBVDD] = "DBVDD",
48 [RT5682S_SUPPLY_LDO1_IN] = "LDO1-IN",
49 };
50
51 static const struct reg_sequence patch_list[] = {
52 {RT5682S_I2C_CTRL, 0x0007},
53 {RT5682S_DIG_IN_CTRL_1, 0x0000},
54 {RT5682S_CHOP_DAC_2, 0x2020},
55 {RT5682S_VREF_REC_OP_FB_CAP_CTRL_2, 0x0101},
56 {RT5682S_VREF_REC_OP_FB_CAP_CTRL_1, 0x80c0},
57 {RT5682S_HP_CALIB_CTRL_9, 0x0002},
58 {RT5682S_DEPOP_1, 0x0000},
59 {RT5682S_HP_CHARGE_PUMP_2, 0x3c15},
60 {RT5682S_DAC1_DIG_VOL, 0xfefe},
61 {RT5682S_SAR_IL_CMD_2, 0xac00},
62 {RT5682S_SAR_IL_CMD_3, 0x024c},
63 {RT5682S_CBJ_CTRL_6, 0x0804},
64 };
65
rt5682s_apply_patch_list(struct rt5682s_priv * rt5682s,struct device * dev)66 static void rt5682s_apply_patch_list(struct rt5682s_priv *rt5682s,
67 struct device *dev)
68 {
69 int ret;
70
71 ret = regmap_multi_reg_write(rt5682s->regmap, patch_list, ARRAY_SIZE(patch_list));
72 if (ret)
73 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);
74 }
75
76 static const struct reg_default rt5682s_reg[] = {
77 {0x0002, 0x8080},
78 {0x0003, 0x0001},
79 {0x0005, 0x0000},
80 {0x0006, 0x0000},
81 {0x0008, 0x8007},
82 {0x000b, 0x0000},
83 {0x000f, 0x4000},
84 {0x0010, 0x4040},
85 {0x0011, 0x0000},
86 {0x0012, 0x0000},
87 {0x0013, 0x1200},
88 {0x0014, 0x200a},
89 {0x0015, 0x0404},
90 {0x0016, 0x0404},
91 {0x0017, 0x05a4},
92 {0x0019, 0xffff},
93 {0x001c, 0x2f2f},
94 {0x001f, 0x0000},
95 {0x0022, 0x5757},
96 {0x0023, 0x0039},
97 {0x0024, 0x000b},
98 {0x0026, 0xc0c4},
99 {0x0029, 0x8080},
100 {0x002a, 0xa0a0},
101 {0x002b, 0x0300},
102 {0x0030, 0x0000},
103 {0x003c, 0x08c0},
104 {0x0044, 0x1818},
105 {0x004b, 0x00c0},
106 {0x004c, 0x0000},
107 {0x004d, 0x0000},
108 {0x0061, 0x00c0},
109 {0x0062, 0x008a},
110 {0x0063, 0x0800},
111 {0x0064, 0x0000},
112 {0x0065, 0x0000},
113 {0x0066, 0x0030},
114 {0x0067, 0x000c},
115 {0x0068, 0x0000},
116 {0x0069, 0x0000},
117 {0x006a, 0x0000},
118 {0x006b, 0x0000},
119 {0x006c, 0x0000},
120 {0x006d, 0x2200},
121 {0x006e, 0x0810},
122 {0x006f, 0xe4de},
123 {0x0070, 0x3320},
124 {0x0071, 0x0000},
125 {0x0073, 0x0000},
126 {0x0074, 0x0000},
127 {0x0075, 0x0002},
128 {0x0076, 0x0001},
129 {0x0079, 0x0000},
130 {0x007a, 0x0000},
131 {0x007b, 0x0000},
132 {0x007c, 0x0100},
133 {0x007e, 0x0000},
134 {0x007f, 0x0000},
135 {0x0080, 0x0000},
136 {0x0083, 0x0000},
137 {0x0084, 0x0000},
138 {0x0085, 0x0000},
139 {0x0086, 0x0005},
140 {0x0087, 0x0000},
141 {0x0088, 0x0000},
142 {0x008c, 0x0003},
143 {0x008e, 0x0060},
144 {0x008f, 0x4da1},
145 {0x0091, 0x1c15},
146 {0x0092, 0x0425},
147 {0x0093, 0x0000},
148 {0x0094, 0x0080},
149 {0x0095, 0x008f},
150 {0x0096, 0x0000},
151 {0x0097, 0x0000},
152 {0x0098, 0x0000},
153 {0x0099, 0x0000},
154 {0x009a, 0x0000},
155 {0x009b, 0x0000},
156 {0x009c, 0x0000},
157 {0x009d, 0x0000},
158 {0x009e, 0x0000},
159 {0x009f, 0x0009},
160 {0x00a0, 0x0000},
161 {0x00a3, 0x0002},
162 {0x00a4, 0x0001},
163 {0x00b6, 0x0000},
164 {0x00b7, 0x0000},
165 {0x00b8, 0x0000},
166 {0x00b9, 0x0002},
167 {0x00be, 0x0000},
168 {0x00c0, 0x0160},
169 {0x00c1, 0x82a0},
170 {0x00c2, 0x0000},
171 {0x00d0, 0x0000},
172 {0x00d2, 0x3300},
173 {0x00d3, 0x2200},
174 {0x00d4, 0x0000},
175 {0x00d9, 0x0000},
176 {0x00da, 0x0000},
177 {0x00db, 0x0000},
178 {0x00dc, 0x00c0},
179 {0x00dd, 0x2220},
180 {0x00de, 0x3131},
181 {0x00df, 0x3131},
182 {0x00e0, 0x3131},
183 {0x00e2, 0x0000},
184 {0x00e3, 0x4000},
185 {0x00e4, 0x0aa0},
186 {0x00e5, 0x3131},
187 {0x00e6, 0x3131},
188 {0x00e7, 0x3131},
189 {0x00e8, 0x3131},
190 {0x00ea, 0xb320},
191 {0x00eb, 0x0000},
192 {0x00f0, 0x0000},
193 {0x00f6, 0x0000},
194 {0x00fa, 0x0000},
195 {0x00fb, 0x0000},
196 {0x00fc, 0x0000},
197 {0x00fd, 0x0000},
198 {0x00fe, 0x10ec},
199 {0x00ff, 0x6749},
200 {0x0100, 0xa000},
201 {0x010b, 0x0066},
202 {0x010c, 0x6666},
203 {0x010d, 0x2202},
204 {0x010e, 0x6666},
205 {0x010f, 0xa800},
206 {0x0110, 0x0006},
207 {0x0111, 0x0460},
208 {0x0112, 0x2000},
209 {0x0113, 0x0200},
210 {0x0117, 0x8000},
211 {0x0118, 0x0303},
212 {0x0125, 0x0020},
213 {0x0132, 0x5026},
214 {0x0136, 0x8000},
215 {0x0139, 0x0005},
216 {0x013a, 0x3030},
217 {0x013b, 0xa000},
218 {0x013c, 0x4110},
219 {0x013f, 0x0000},
220 {0x0145, 0x0022},
221 {0x0146, 0x0000},
222 {0x0147, 0x0000},
223 {0x0148, 0x0000},
224 {0x0156, 0x0022},
225 {0x0157, 0x0303},
226 {0x0158, 0x2222},
227 {0x0159, 0x0000},
228 {0x0160, 0x4ec0},
229 {0x0161, 0x0080},
230 {0x0162, 0x0200},
231 {0x0163, 0x0800},
232 {0x0164, 0x0000},
233 {0x0165, 0x0000},
234 {0x0166, 0x0000},
235 {0x0167, 0x000f},
236 {0x0168, 0x000f},
237 {0x0169, 0x0001},
238 {0x0190, 0x4131},
239 {0x0194, 0x0000},
240 {0x0195, 0x0000},
241 {0x0197, 0x0022},
242 {0x0198, 0x0000},
243 {0x0199, 0x0000},
244 {0x01ac, 0x0000},
245 {0x01ad, 0x0000},
246 {0x01ae, 0x0000},
247 {0x01af, 0x2000},
248 {0x01b0, 0x0000},
249 {0x01b1, 0x0000},
250 {0x01b2, 0x0000},
251 {0x01b3, 0x0017},
252 {0x01b4, 0x004b},
253 {0x01b5, 0x0000},
254 {0x01b6, 0x03e8},
255 {0x01b7, 0x0000},
256 {0x01b8, 0x0000},
257 {0x01b9, 0x0400},
258 {0x01ba, 0xb5b6},
259 {0x01bb, 0x9124},
260 {0x01bc, 0x4924},
261 {0x01bd, 0x0009},
262 {0x01be, 0x0018},
263 {0x01bf, 0x002a},
264 {0x01c0, 0x004c},
265 {0x01c1, 0x0097},
266 {0x01c2, 0x01c3},
267 {0x01c3, 0x03e9},
268 {0x01c4, 0x1389},
269 {0x01c5, 0xc351},
270 {0x01c6, 0x02a0},
271 {0x01c7, 0x0b0f},
272 {0x01c8, 0x402f},
273 {0x01c9, 0x0702},
274 {0x01ca, 0x0000},
275 {0x01cb, 0x0000},
276 {0x01cc, 0x5757},
277 {0x01cd, 0x5757},
278 {0x01ce, 0x5757},
279 {0x01cf, 0x5757},
280 {0x01d0, 0x5757},
281 {0x01d1, 0x5757},
282 {0x01d2, 0x5757},
283 {0x01d3, 0x5757},
284 {0x01d4, 0x5757},
285 {0x01d5, 0x5757},
286 {0x01d6, 0x0000},
287 {0x01d7, 0x0000},
288 {0x01d8, 0x0162},
289 {0x01d9, 0x0007},
290 {0x01da, 0x0000},
291 {0x01db, 0x0004},
292 {0x01dc, 0x0000},
293 {0x01de, 0x7c00},
294 {0x01df, 0x0020},
295 {0x01e0, 0x04c1},
296 {0x01e1, 0x0000},
297 {0x01e2, 0x0000},
298 {0x01e3, 0x0000},
299 {0x01e4, 0x0000},
300 {0x01e5, 0x0000},
301 {0x01e6, 0x0001},
302 {0x01e7, 0x0000},
303 {0x01e8, 0x0000},
304 {0x01eb, 0x0000},
305 {0x01ec, 0x0000},
306 {0x01ed, 0x0000},
307 {0x01ee, 0x0000},
308 {0x01ef, 0x0000},
309 {0x01f0, 0x0000},
310 {0x01f1, 0x0000},
311 {0x01f2, 0x0000},
312 {0x01f3, 0x0000},
313 {0x01f4, 0x0000},
314 {0x0210, 0x6297},
315 {0x0211, 0xa004},
316 {0x0212, 0x0365},
317 {0x0213, 0xf7ff},
318 {0x0214, 0xf24c},
319 {0x0215, 0x0102},
320 {0x0216, 0x00a3},
321 {0x0217, 0x0048},
322 {0x0218, 0xa2c0},
323 {0x0219, 0x0400},
324 {0x021a, 0x00c8},
325 {0x021b, 0x00c0},
326 {0x021c, 0x0000},
327 {0x021d, 0x024c},
328 {0x02fa, 0x0000},
329 {0x02fb, 0x0000},
330 {0x02fc, 0x0000},
331 {0x03fe, 0x0000},
332 {0x03ff, 0x0000},
333 {0x0500, 0x0000},
334 {0x0600, 0x0000},
335 {0x0610, 0x6666},
336 {0x0611, 0xa9aa},
337 {0x0620, 0x6666},
338 {0x0621, 0xa9aa},
339 {0x0630, 0x6666},
340 {0x0631, 0xa9aa},
341 {0x0640, 0x6666},
342 {0x0641, 0xa9aa},
343 {0x07fa, 0x0000},
344 {0x08fa, 0x0000},
345 {0x08fb, 0x0000},
346 {0x0d00, 0x0000},
347 {0x1100, 0x0000},
348 {0x1101, 0x0000},
349 {0x1102, 0x0000},
350 {0x1103, 0x0000},
351 {0x1104, 0x0000},
352 {0x1105, 0x0000},
353 {0x1106, 0x0000},
354 {0x1107, 0x0000},
355 {0x1108, 0x0000},
356 {0x1109, 0x0000},
357 {0x110a, 0x0000},
358 {0x110b, 0x0000},
359 {0x110c, 0x0000},
360 {0x1111, 0x0000},
361 {0x1112, 0x0000},
362 {0x1113, 0x0000},
363 {0x1114, 0x0000},
364 {0x1115, 0x0000},
365 {0x1116, 0x0000},
366 {0x1117, 0x0000},
367 {0x1118, 0x0000},
368 {0x1119, 0x0000},
369 {0x111a, 0x0000},
370 {0x111b, 0x0000},
371 {0x111c, 0x0000},
372 {0x1401, 0x0404},
373 {0x1402, 0x0007},
374 {0x1403, 0x0365},
375 {0x1404, 0x0210},
376 {0x1405, 0x0365},
377 {0x1406, 0x0210},
378 {0x1407, 0x0000},
379 {0x1408, 0x0000},
380 {0x1409, 0x0000},
381 {0x140a, 0x0000},
382 {0x140b, 0x0000},
383 {0x140c, 0x0000},
384 {0x140d, 0x0000},
385 {0x140e, 0x0000},
386 {0x140f, 0x0000},
387 {0x1410, 0x0000},
388 {0x1411, 0x0000},
389 {0x1801, 0x0004},
390 {0x1802, 0x0000},
391 {0x1803, 0x0000},
392 {0x1804, 0x0000},
393 {0x1805, 0x00ff},
394 {0x2c00, 0x0000},
395 {0x3400, 0x0200},
396 {0x3404, 0x0000},
397 {0x3405, 0x0000},
398 {0x3406, 0x0000},
399 {0x3407, 0x0000},
400 {0x3408, 0x0000},
401 {0x3409, 0x0000},
402 {0x340a, 0x0000},
403 {0x340b, 0x0000},
404 {0x340c, 0x0000},
405 {0x340d, 0x0000},
406 {0x340e, 0x0000},
407 {0x340f, 0x0000},
408 {0x3410, 0x0000},
409 {0x3411, 0x0000},
410 {0x3412, 0x0000},
411 {0x3413, 0x0000},
412 {0x3414, 0x0000},
413 {0x3415, 0x0000},
414 {0x3424, 0x0000},
415 {0x3425, 0x0000},
416 {0x3426, 0x0000},
417 {0x3427, 0x0000},
418 {0x3428, 0x0000},
419 {0x3429, 0x0000},
420 {0x342a, 0x0000},
421 {0x342b, 0x0000},
422 {0x342c, 0x0000},
423 {0x342d, 0x0000},
424 {0x342e, 0x0000},
425 {0x342f, 0x0000},
426 {0x3430, 0x0000},
427 {0x3431, 0x0000},
428 {0x3432, 0x0000},
429 {0x3433, 0x0000},
430 {0x3434, 0x0000},
431 {0x3435, 0x0000},
432 {0x3440, 0x6319},
433 {0x3441, 0x3771},
434 {0x3500, 0x0002},
435 {0x3501, 0x5728},
436 {0x3b00, 0x3010},
437 {0x3b01, 0x3300},
438 {0x3b02, 0x2200},
439 {0x3b03, 0x0100},
440 };
441
rt5682s_volatile_register(struct device * dev,unsigned int reg)442 static bool rt5682s_volatile_register(struct device *dev, unsigned int reg)
443 {
444 switch (reg) {
445 case RT5682S_RESET:
446 case RT5682S_CBJ_CTRL_2:
447 case RT5682S_I2S1_F_DIV_CTRL_2:
448 case RT5682S_I2S2_F_DIV_CTRL_2:
449 case RT5682S_INT_ST_1:
450 case RT5682S_GPIO_ST:
451 case RT5682S_IL_CMD_1:
452 case RT5682S_4BTN_IL_CMD_1:
453 case RT5682S_AJD1_CTRL:
454 case RT5682S_VERSION_ID...RT5682S_DEVICE_ID:
455 case RT5682S_STO_NG2_CTRL_1:
456 case RT5682S_STO_NG2_CTRL_5...RT5682S_STO_NG2_CTRL_7:
457 case RT5682S_STO1_DAC_SIL_DET:
458 case RT5682S_HP_IMP_SENS_CTRL_1...RT5682S_HP_IMP_SENS_CTRL_4:
459 case RT5682S_HP_IMP_SENS_CTRL_13:
460 case RT5682S_HP_IMP_SENS_CTRL_14:
461 case RT5682S_HP_IMP_SENS_CTRL_43...RT5682S_HP_IMP_SENS_CTRL_46:
462 case RT5682S_HP_CALIB_CTRL_1:
463 case RT5682S_HP_CALIB_CTRL_10:
464 case RT5682S_HP_CALIB_ST_1...RT5682S_HP_CALIB_ST_11:
465 case RT5682S_SAR_IL_CMD_2...RT5682S_SAR_IL_CMD_5:
466 case RT5682S_SAR_IL_CMD_10:
467 case RT5682S_SAR_IL_CMD_11:
468 case RT5682S_VERSION_ID_HIDE:
469 case RT5682S_VERSION_ID_CUS:
470 case RT5682S_I2C_TRANS_CTRL:
471 case RT5682S_DMIC_FLOAT_DET:
472 case RT5682S_HA_CMP_OP_1:
473 case RT5682S_NEW_CBJ_DET_CTL_10...RT5682S_NEW_CBJ_DET_CTL_16:
474 case RT5682S_CLK_SW_TEST_1:
475 case RT5682S_CLK_SW_TEST_2:
476 case RT5682S_EFUSE_READ_1...RT5682S_EFUSE_READ_18:
477 case RT5682S_PILOT_DIG_CTL_1:
478 return true;
479 default:
480 return false;
481 }
482 }
483
rt5682s_readable_register(struct device * dev,unsigned int reg)484 static bool rt5682s_readable_register(struct device *dev, unsigned int reg)
485 {
486 switch (reg) {
487 case RT5682S_RESET:
488 case RT5682S_VERSION_ID:
489 case RT5682S_VENDOR_ID:
490 case RT5682S_DEVICE_ID:
491 case RT5682S_HP_CTRL_1:
492 case RT5682S_HP_CTRL_2:
493 case RT5682S_HPL_GAIN:
494 case RT5682S_HPR_GAIN:
495 case RT5682S_I2C_CTRL:
496 case RT5682S_CBJ_BST_CTRL:
497 case RT5682S_CBJ_DET_CTRL:
498 case RT5682S_CBJ_CTRL_1...RT5682S_CBJ_CTRL_8:
499 case RT5682S_DAC1_DIG_VOL:
500 case RT5682S_STO1_ADC_DIG_VOL:
501 case RT5682S_STO1_ADC_BOOST:
502 case RT5682S_HP_IMP_GAIN_1:
503 case RT5682S_HP_IMP_GAIN_2:
504 case RT5682S_SIDETONE_CTRL:
505 case RT5682S_STO1_ADC_MIXER:
506 case RT5682S_AD_DA_MIXER:
507 case RT5682S_STO1_DAC_MIXER:
508 case RT5682S_A_DAC1_MUX:
509 case RT5682S_DIG_INF2_DATA:
510 case RT5682S_REC_MIXER:
511 case RT5682S_CAL_REC:
512 case RT5682S_HP_ANA_OST_CTRL_1...RT5682S_HP_ANA_OST_CTRL_3:
513 case RT5682S_PWR_DIG_1...RT5682S_PWR_MIXER:
514 case RT5682S_MB_CTRL:
515 case RT5682S_CLK_GATE_TCON_1...RT5682S_CLK_GATE_TCON_3:
516 case RT5682S_CLK_DET...RT5682S_LPF_AD_DMIC:
517 case RT5682S_I2S1_SDP:
518 case RT5682S_I2S2_SDP:
519 case RT5682S_ADDA_CLK_1:
520 case RT5682S_ADDA_CLK_2:
521 case RT5682S_I2S1_F_DIV_CTRL_1:
522 case RT5682S_I2S1_F_DIV_CTRL_2:
523 case RT5682S_TDM_CTRL:
524 case RT5682S_TDM_ADDA_CTRL_1:
525 case RT5682S_TDM_ADDA_CTRL_2:
526 case RT5682S_DATA_SEL_CTRL_1:
527 case RT5682S_TDM_TCON_CTRL_1:
528 case RT5682S_TDM_TCON_CTRL_2:
529 case RT5682S_GLB_CLK:
530 case RT5682S_PLL_TRACK_1...RT5682S_PLL_TRACK_6:
531 case RT5682S_PLL_TRACK_11:
532 case RT5682S_DEPOP_1:
533 case RT5682S_HP_CHARGE_PUMP_1:
534 case RT5682S_HP_CHARGE_PUMP_2:
535 case RT5682S_HP_CHARGE_PUMP_3:
536 case RT5682S_MICBIAS_1...RT5682S_MICBIAS_3:
537 case RT5682S_PLL_TRACK_12...RT5682S_PLL_CTRL_7:
538 case RT5682S_RC_CLK_CTRL:
539 case RT5682S_I2S2_M_CLK_CTRL_1:
540 case RT5682S_I2S2_F_DIV_CTRL_1:
541 case RT5682S_I2S2_F_DIV_CTRL_2:
542 case RT5682S_IRQ_CTRL_1...RT5682S_IRQ_CTRL_4:
543 case RT5682S_INT_ST_1:
544 case RT5682S_GPIO_CTRL_1:
545 case RT5682S_GPIO_CTRL_2:
546 case RT5682S_GPIO_ST:
547 case RT5682S_HP_AMP_DET_CTRL_1:
548 case RT5682S_MID_HP_AMP_DET:
549 case RT5682S_LOW_HP_AMP_DET:
550 case RT5682S_DELAY_BUF_CTRL:
551 case RT5682S_SV_ZCD_1:
552 case RT5682S_SV_ZCD_2:
553 case RT5682S_IL_CMD_1...RT5682S_IL_CMD_6:
554 case RT5682S_4BTN_IL_CMD_1...RT5682S_4BTN_IL_CMD_7:
555 case RT5682S_ADC_STO1_HP_CTRL_1:
556 case RT5682S_ADC_STO1_HP_CTRL_2:
557 case RT5682S_AJD1_CTRL:
558 case RT5682S_JD_CTRL_1:
559 case RT5682S_DUMMY_1...RT5682S_DUMMY_3:
560 case RT5682S_DAC_ADC_DIG_VOL1:
561 case RT5682S_BIAS_CUR_CTRL_2...RT5682S_BIAS_CUR_CTRL_10:
562 case RT5682S_VREF_REC_OP_FB_CAP_CTRL_1:
563 case RT5682S_VREF_REC_OP_FB_CAP_CTRL_2:
564 case RT5682S_CHARGE_PUMP_1:
565 case RT5682S_DIG_IN_CTRL_1:
566 case RT5682S_PAD_DRIVING_CTRL:
567 case RT5682S_CHOP_DAC_1:
568 case RT5682S_CHOP_DAC_2:
569 case RT5682S_CHOP_ADC:
570 case RT5682S_CALIB_ADC_CTRL:
571 case RT5682S_VOL_TEST:
572 case RT5682S_SPKVDD_DET_ST:
573 case RT5682S_TEST_MODE_CTRL_1...RT5682S_TEST_MODE_CTRL_4:
574 case RT5682S_PLL_INTERNAL_1...RT5682S_PLL_INTERNAL_4:
575 case RT5682S_STO_NG2_CTRL_1...RT5682S_STO_NG2_CTRL_10:
576 case RT5682S_STO1_DAC_SIL_DET:
577 case RT5682S_SIL_PSV_CTRL1:
578 case RT5682S_SIL_PSV_CTRL2:
579 case RT5682S_SIL_PSV_CTRL3:
580 case RT5682S_SIL_PSV_CTRL4:
581 case RT5682S_SIL_PSV_CTRL5:
582 case RT5682S_HP_IMP_SENS_CTRL_1...RT5682S_HP_IMP_SENS_CTRL_46:
583 case RT5682S_HP_LOGIC_CTRL_1...RT5682S_HP_LOGIC_CTRL_3:
584 case RT5682S_HP_CALIB_CTRL_1...RT5682S_HP_CALIB_CTRL_11:
585 case RT5682S_HP_CALIB_ST_1...RT5682S_HP_CALIB_ST_11:
586 case RT5682S_SAR_IL_CMD_1...RT5682S_SAR_IL_CMD_14:
587 case RT5682S_DUMMY_4...RT5682S_DUMMY_6:
588 case RT5682S_VERSION_ID_HIDE:
589 case RT5682S_VERSION_ID_CUS:
590 case RT5682S_SCAN_CTL:
591 case RT5682S_HP_AMP_DET:
592 case RT5682S_BIAS_CUR_CTRL_11:
593 case RT5682S_BIAS_CUR_CTRL_12:
594 case RT5682S_BIAS_CUR_CTRL_13:
595 case RT5682S_BIAS_CUR_CTRL_14:
596 case RT5682S_BIAS_CUR_CTRL_15:
597 case RT5682S_BIAS_CUR_CTRL_16:
598 case RT5682S_BIAS_CUR_CTRL_17:
599 case RT5682S_BIAS_CUR_CTRL_18:
600 case RT5682S_I2C_TRANS_CTRL:
601 case RT5682S_DUMMY_7:
602 case RT5682S_DUMMY_8:
603 case RT5682S_DMIC_FLOAT_DET:
604 case RT5682S_HA_CMP_OP_1...RT5682S_HA_CMP_OP_13:
605 case RT5682S_HA_CMP_OP_14...RT5682S_HA_CMP_OP_25:
606 case RT5682S_NEW_CBJ_DET_CTL_1...RT5682S_NEW_CBJ_DET_CTL_16:
607 case RT5682S_DA_FILTER_1...RT5682S_DA_FILTER_5:
608 case RT5682S_CLK_SW_TEST_1:
609 case RT5682S_CLK_SW_TEST_2:
610 case RT5682S_CLK_SW_TEST_3...RT5682S_CLK_SW_TEST_14:
611 case RT5682S_EFUSE_MANU_WRITE_1...RT5682S_EFUSE_MANU_WRITE_6:
612 case RT5682S_EFUSE_READ_1...RT5682S_EFUSE_READ_18:
613 case RT5682S_EFUSE_TIMING_CTL_1:
614 case RT5682S_EFUSE_TIMING_CTL_2:
615 case RT5682S_PILOT_DIG_CTL_1:
616 case RT5682S_PILOT_DIG_CTL_2:
617 case RT5682S_HP_AMP_DET_CTL_1...RT5682S_HP_AMP_DET_CTL_4:
618 return true;
619 default:
620 return false;
621 }
622 }
623
rt5682s_reset(struct rt5682s_priv * rt5682s)624 static void rt5682s_reset(struct rt5682s_priv *rt5682s)
625 {
626 regmap_write(rt5682s->regmap, RT5682S_RESET, 0);
627 }
628
rt5682s_button_detect(struct snd_soc_component * component)629 static int rt5682s_button_detect(struct snd_soc_component *component)
630 {
631 int btn_type, val;
632
633 val = snd_soc_component_read(component, RT5682S_4BTN_IL_CMD_1);
634 btn_type = val & 0xfff0;
635 snd_soc_component_write(component, RT5682S_4BTN_IL_CMD_1, val);
636 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type);
637 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_2,
638 RT5682S_SAR_ADC_PSV_MASK, RT5682S_SAR_ADC_PSV_ENTRY);
639
640 return btn_type;
641 }
642
643 enum {
644 SAR_PWR_OFF,
645 SAR_PWR_NORMAL,
646 SAR_PWR_SAVING,
647 };
648
rt5682s_sar_power_mode(struct snd_soc_component * component,int mode)649 static void rt5682s_sar_power_mode(struct snd_soc_component *component, int mode)
650 {
651 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
652
653 mutex_lock(&rt5682s->sar_mutex);
654
655 switch (mode) {
656 case SAR_PWR_SAVING:
657 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
658 RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_DIS);
659 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
660 RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK,
661 RT5682S_CTRL_MB1_REG | RT5682S_CTRL_MB2_REG);
662 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
663 RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
664 RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS |
665 RT5682S_SAR_BUTDET_POW_SAV | RT5682S_SAR_SEL_MB1_2_MANU);
666 usleep_range(5000, 5500);
667 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
668 RT5682S_SAR_BUTDET_MASK, RT5682S_SAR_BUTDET_EN);
669 usleep_range(5000, 5500);
670 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_2,
671 RT5682S_SAR_ADC_PSV_MASK, RT5682S_SAR_ADC_PSV_ENTRY);
672 break;
673 case SAR_PWR_NORMAL:
674 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
675 RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_EN);
676 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
677 RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK,
678 RT5682S_CTRL_MB1_FSM | RT5682S_CTRL_MB2_FSM);
679 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
680 RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_SEL_MB1_2_AUTO);
681 usleep_range(5000, 5500);
682 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
683 RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK,
684 RT5682S_SAR_BUTDET_EN | RT5682S_SAR_BUTDET_POW_NORM);
685 break;
686 case SAR_PWR_OFF:
687 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
688 RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK,
689 RT5682S_CTRL_MB1_FSM | RT5682S_CTRL_MB2_FSM);
690 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
691 RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
692 RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS |
693 RT5682S_SAR_BUTDET_POW_SAV | RT5682S_SAR_SEL_MB1_2_MANU);
694 break;
695 default:
696 dev_err(component->dev, "Invalid SAR Power mode: %d\n", mode);
697 break;
698 }
699
700 mutex_unlock(&rt5682s->sar_mutex);
701 }
702
rt5682s_enable_push_button_irq(struct snd_soc_component * component)703 static void rt5682s_enable_push_button_irq(struct snd_soc_component *component)
704 {
705 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13,
706 RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_BTN);
707 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
708 RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
709 RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_EN |
710 RT5682S_SAR_BUTDET_POW_NORM | RT5682S_SAR_SEL_MB1_2_AUTO);
711 snd_soc_component_write(component, RT5682S_IL_CMD_1, 0x0040);
712 snd_soc_component_update_bits(component, RT5682S_4BTN_IL_CMD_2,
713 RT5682S_4BTN_IL_MASK | RT5682S_4BTN_IL_RST_MASK,
714 RT5682S_4BTN_IL_EN | RT5682S_4BTN_IL_NOR);
715 snd_soc_component_update_bits(component, RT5682S_IRQ_CTRL_3,
716 RT5682S_IL_IRQ_MASK, RT5682S_IL_IRQ_EN);
717 }
718
rt5682s_disable_push_button_irq(struct snd_soc_component * component)719 static void rt5682s_disable_push_button_irq(struct snd_soc_component *component)
720 {
721 snd_soc_component_update_bits(component, RT5682S_IRQ_CTRL_3,
722 RT5682S_IL_IRQ_MASK, RT5682S_IL_IRQ_DIS);
723 snd_soc_component_update_bits(component, RT5682S_4BTN_IL_CMD_2,
724 RT5682S_4BTN_IL_MASK, RT5682S_4BTN_IL_DIS);
725 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13,
726 RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_TYPE);
727 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
728 RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
729 RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS |
730 RT5682S_SAR_BUTDET_POW_SAV | RT5682S_SAR_SEL_MB1_2_MANU);
731 }
732
733 /**
734 * rt5682s_headset_detect - Detect headset.
735 * @component: SoC audio component device.
736 * @jack_insert: Jack insert or not.
737 *
738 * Detect whether is headset or not when jack inserted.
739 *
740 * Returns detect status.
741 */
rt5682s_headset_detect(struct snd_soc_component * component,int jack_insert)742 static int rt5682s_headset_detect(struct snd_soc_component *component, int jack_insert)
743 {
744 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
745 unsigned int val, count;
746 int jack_type = 0;
747
748 if (jack_insert) {
749 rt5682s_disable_push_button_irq(component);
750 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
751 RT5682S_PWR_VREF1 | RT5682S_PWR_VREF2 | RT5682S_PWR_MB,
752 RT5682S_PWR_VREF1 | RT5682S_PWR_VREF2 | RT5682S_PWR_MB);
753 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
754 RT5682S_PWR_FV1 | RT5682S_PWR_FV2, 0);
755 usleep_range(15000, 20000);
756 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
757 RT5682S_PWR_FV1 | RT5682S_PWR_FV2,
758 RT5682S_PWR_FV1 | RT5682S_PWR_FV2);
759 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3,
760 RT5682S_PWR_CBJ, RT5682S_PWR_CBJ);
761 snd_soc_component_write(component, RT5682S_SAR_IL_CMD_3, 0x0365);
762 snd_soc_component_update_bits(component, RT5682S_HP_CHARGE_PUMP_2,
763 RT5682S_OSW_L_MASK | RT5682S_OSW_R_MASK,
764 RT5682S_OSW_L_DIS | RT5682S_OSW_R_DIS);
765 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13,
766 RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_TYPE);
767 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
768 RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_EN);
769 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
770 RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_LOW);
771 usleep_range(45000, 50000);
772 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
773 RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_HIGH);
774
775 count = 0;
776 do {
777 usleep_range(10000, 15000);
778 val = snd_soc_component_read(component, RT5682S_CBJ_CTRL_2)
779 & RT5682S_JACK_TYPE_MASK;
780 count++;
781 } while (val == 0 && count < 50);
782
783 dev_dbg(component->dev, "%s, val=%d, count=%d\n", __func__, val, count);
784
785 switch (val) {
786 case 0x1:
787 case 0x2:
788 jack_type = SND_JACK_HEADSET;
789 snd_soc_component_write(component, RT5682S_SAR_IL_CMD_3, 0x024c);
790 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
791 RT5682S_FAST_OFF_MASK, RT5682S_FAST_OFF_EN);
792 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
793 RT5682S_SAR_SEL_MB1_2_MASK, val << RT5682S_SAR_SEL_MB1_2_SFT);
794 rt5682s_enable_push_button_irq(component);
795 rt5682s_sar_power_mode(component, SAR_PWR_SAVING);
796 break;
797 default:
798 jack_type = SND_JACK_HEADPHONE;
799 break;
800 }
801 snd_soc_component_update_bits(component, RT5682S_HP_CHARGE_PUMP_2,
802 RT5682S_OSW_L_MASK | RT5682S_OSW_R_MASK,
803 RT5682S_OSW_L_EN | RT5682S_OSW_R_EN);
804 usleep_range(35000, 40000);
805 } else {
806 rt5682s_sar_power_mode(component, SAR_PWR_OFF);
807 rt5682s_disable_push_button_irq(component);
808 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
809 RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_LOW);
810
811 if (!rt5682s->wclk_enabled) {
812 snd_soc_component_update_bits(component,
813 RT5682S_PWR_ANLG_1, RT5682S_PWR_VREF2 | RT5682S_PWR_MB, 0);
814 }
815
816 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3,
817 RT5682S_PWR_CBJ, 0);
818 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
819 RT5682S_FAST_OFF_MASK, RT5682S_FAST_OFF_DIS);
820 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
821 RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_DIS);
822 jack_type = 0;
823 }
824
825 dev_dbg(component->dev, "jack_type = %d\n", jack_type);
826
827 return jack_type;
828 }
829
rt5682s_jack_detect_handler(struct work_struct * work)830 static void rt5682s_jack_detect_handler(struct work_struct *work)
831 {
832 struct rt5682s_priv *rt5682s =
833 container_of(work, struct rt5682s_priv, jack_detect_work.work);
834 struct snd_soc_dapm_context *dapm;
835 int val, btn_type;
836
837 if (!rt5682s->component ||
838 !snd_soc_card_is_instantiated(rt5682s->component->card)) {
839 /* card not yet ready, try later */
840 mod_delayed_work(system_power_efficient_wq,
841 &rt5682s->jack_detect_work, msecs_to_jiffies(15));
842 return;
843 }
844
845 dapm = snd_soc_component_get_dapm(rt5682s->component);
846
847 snd_soc_dapm_mutex_lock(dapm);
848 mutex_lock(&rt5682s->calibrate_mutex);
849 mutex_lock(&rt5682s->wclk_mutex);
850
851 val = snd_soc_component_read(rt5682s->component, RT5682S_AJD1_CTRL)
852 & RT5682S_JDH_RS_MASK;
853 if (!val) {
854 /* jack in */
855 if (rt5682s->jack_type == 0) {
856 /* jack was out, report jack type */
857 rt5682s->jack_type = rt5682s_headset_detect(rt5682s->component, 1);
858 rt5682s->irq_work_delay_time = 0;
859 } else if ((rt5682s->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {
860 /* jack is already in, report button event */
861 rt5682s->jack_type = SND_JACK_HEADSET;
862 btn_type = rt5682s_button_detect(rt5682s->component);
863 /**
864 * rt5682s can report three kinds of button behavior,
865 * one click, double click and hold. However,
866 * currently we will report button pressed/released
867 * event. So all the three button behaviors are
868 * treated as button pressed.
869 */
870 switch (btn_type) {
871 case 0x8000:
872 case 0x4000:
873 case 0x2000:
874 rt5682s->jack_type |= SND_JACK_BTN_0;
875 break;
876 case 0x1000:
877 case 0x0800:
878 case 0x0400:
879 rt5682s->jack_type |= SND_JACK_BTN_1;
880 break;
881 case 0x0200:
882 case 0x0100:
883 case 0x0080:
884 rt5682s->jack_type |= SND_JACK_BTN_2;
885 break;
886 case 0x0040:
887 case 0x0020:
888 case 0x0010:
889 rt5682s->jack_type |= SND_JACK_BTN_3;
890 break;
891 case 0x0000: /* unpressed */
892 break;
893 default:
894 dev_err(rt5682s->component->dev,
895 "Unexpected button code 0x%04x\n", btn_type);
896 break;
897 }
898 }
899 } else {
900 /* jack out */
901 rt5682s->jack_type = rt5682s_headset_detect(rt5682s->component, 0);
902 rt5682s->irq_work_delay_time = 50;
903 }
904
905 mutex_unlock(&rt5682s->wclk_mutex);
906 mutex_unlock(&rt5682s->calibrate_mutex);
907 snd_soc_dapm_mutex_unlock(dapm);
908
909 snd_soc_jack_report(rt5682s->hs_jack, rt5682s->jack_type,
910 SND_JACK_HEADSET | SND_JACK_BTN_0 | SND_JACK_BTN_1 |
911 SND_JACK_BTN_2 | SND_JACK_BTN_3);
912
913 if (rt5682s->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
914 SND_JACK_BTN_2 | SND_JACK_BTN_3))
915 schedule_delayed_work(&rt5682s->jd_check_work, 0);
916 else
917 cancel_delayed_work_sync(&rt5682s->jd_check_work);
918 }
919
rt5682s_jd_check_handler(struct work_struct * work)920 static void rt5682s_jd_check_handler(struct work_struct *work)
921 {
922 struct rt5682s_priv *rt5682s =
923 container_of(work, struct rt5682s_priv, jd_check_work.work);
924
925 if (snd_soc_component_read(rt5682s->component, RT5682S_AJD1_CTRL) & RT5682S_JDH_RS_MASK) {
926 /* jack out */
927 schedule_delayed_work(&rt5682s->jack_detect_work, 0);
928 } else {
929 schedule_delayed_work(&rt5682s->jd_check_work, 500);
930 }
931 }
932
rt5682s_irq(int irq,void * data)933 static irqreturn_t rt5682s_irq(int irq, void *data)
934 {
935 struct rt5682s_priv *rt5682s = data;
936
937 mod_delayed_work(system_power_efficient_wq, &rt5682s->jack_detect_work,
938 msecs_to_jiffies(rt5682s->irq_work_delay_time));
939
940 return IRQ_HANDLED;
941 }
942
rt5682s_set_jack_detect(struct snd_soc_component * component,struct snd_soc_jack * hs_jack,void * data)943 static int rt5682s_set_jack_detect(struct snd_soc_component *component,
944 struct snd_soc_jack *hs_jack, void *data)
945 {
946 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
947 int btndet_delay = 16;
948
949 rt5682s->hs_jack = hs_jack;
950
951 if (!hs_jack) {
952 regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2,
953 RT5682S_JD1_EN_MASK, RT5682S_JD1_DIS);
954 regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL,
955 RT5682S_POW_JDH, 0);
956 cancel_delayed_work_sync(&rt5682s->jack_detect_work);
957
958 return 0;
959 }
960
961 switch (rt5682s->pdata.jd_src) {
962 case RT5682S_JD1:
963 regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_5,
964 RT5682S_JD_FAST_OFF_SRC_MASK, RT5682S_JD_FAST_OFF_SRC_JDH);
965 regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_2,
966 RT5682S_EXT_JD_SRC, RT5682S_EXT_JD_SRC_MANUAL);
967 regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_1,
968 RT5682S_EMB_JD_MASK | RT5682S_DET_TYPE |
969 RT5682S_POL_FAST_OFF_MASK | RT5682S_MIC_CAP_MASK,
970 RT5682S_EMB_JD_EN | RT5682S_DET_TYPE |
971 RT5682S_POL_FAST_OFF_HIGH | RT5682S_MIC_CAP_HS);
972 regmap_update_bits(rt5682s->regmap, RT5682S_SAR_IL_CMD_1,
973 RT5682S_SAR_POW_MASK, RT5682S_SAR_POW_EN);
974 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
975 RT5682S_GP1_PIN_MASK, RT5682S_GP1_PIN_IRQ);
976 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_3,
977 RT5682S_PWR_BGLDO, RT5682S_PWR_BGLDO);
978 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_2,
979 RT5682S_PWR_JD_MASK, RT5682S_PWR_JD_ENABLE);
980 regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL,
981 RT5682S_POW_IRQ | RT5682S_POW_JDH, RT5682S_POW_IRQ | RT5682S_POW_JDH);
982 regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2,
983 RT5682S_JD1_EN_MASK | RT5682S_JD1_POL_MASK,
984 RT5682S_JD1_EN | RT5682S_JD1_POL_NOR);
985 regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_4,
986 RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
987 (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
988 regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_5,
989 RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
990 (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
991 regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_6,
992 RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
993 (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
994 regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_7,
995 RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
996 (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
997
998 mod_delayed_work(system_power_efficient_wq,
999 &rt5682s->jack_detect_work, msecs_to_jiffies(250));
1000 break;
1001
1002 case RT5682S_JD_NULL:
1003 regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2,
1004 RT5682S_JD1_EN_MASK, RT5682S_JD1_DIS);
1005 regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL,
1006 RT5682S_POW_JDH, 0);
1007 break;
1008
1009 default:
1010 dev_warn(component->dev, "Wrong JD source\n");
1011 break;
1012 }
1013
1014 return 0;
1015 }
1016
1017 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9562, 75, 0);
1018 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1019 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
1020 static const DECLARE_TLV_DB_SCALE(cbj_bst_tlv, -1200, 150, 0);
1021
1022 static const struct snd_kcontrol_new rt5682s_snd_controls[] = {
1023 /* DAC Digital Volume */
1024 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682S_DAC1_DIG_VOL,
1025 RT5682S_L_VOL_SFT + 1, RT5682S_R_VOL_SFT + 1, 127, 0, dac_vol_tlv),
1026
1027 /* CBJ Boost Volume */
1028 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682S_REC_MIXER,
1029 RT5682S_BST_CBJ_SFT, 35, 0, cbj_bst_tlv),
1030
1031 /* ADC Digital Volume Control */
1032 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682S_STO1_ADC_DIG_VOL,
1033 RT5682S_L_MUTE_SFT, RT5682S_R_MUTE_SFT, 1, 1),
1034 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682S_STO1_ADC_DIG_VOL,
1035 RT5682S_L_VOL_SFT + 1, RT5682S_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1036
1037 /* ADC Boost Volume Control */
1038 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682S_STO1_ADC_BOOST,
1039 RT5682S_STO1_ADC_L_BST_SFT, RT5682S_STO1_ADC_R_BST_SFT, 3, 0, adc_bst_tlv),
1040 };
1041
1042 /**
1043 * rt5682s_sel_asrc_clk_src - select ASRC clock source for a set of filters
1044 * @component: SoC audio component device.
1045 * @filter_mask: mask of filters.
1046 * @clk_src: clock source
1047 *
1048 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682S can
1049 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1050 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1051 * ASRC function will track i2s clock and generate a corresponding system clock
1052 * for codec. This function provides an API to select the clock source for a
1053 * set of filters specified by the mask. And the component driver will turn on
1054 * ASRC for these filters if ASRC is selected as their clock source.
1055 */
rt5682s_sel_asrc_clk_src(struct snd_soc_component * component,unsigned int filter_mask,unsigned int clk_src)1056 int rt5682s_sel_asrc_clk_src(struct snd_soc_component *component,
1057 unsigned int filter_mask, unsigned int clk_src)
1058 {
1059 switch (clk_src) {
1060 case RT5682S_CLK_SEL_SYS:
1061 case RT5682S_CLK_SEL_I2S1_ASRC:
1062 case RT5682S_CLK_SEL_I2S2_ASRC:
1063 break;
1064
1065 default:
1066 return -EINVAL;
1067 }
1068
1069 if (filter_mask & RT5682S_DA_STEREO1_FILTER) {
1070 snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_2,
1071 RT5682S_FILTER_CLK_SEL_MASK, clk_src << RT5682S_FILTER_CLK_SEL_SFT);
1072 }
1073
1074 if (filter_mask & RT5682S_AD_STEREO1_FILTER) {
1075 snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_3,
1076 RT5682S_FILTER_CLK_SEL_MASK, clk_src << RT5682S_FILTER_CLK_SEL_SFT);
1077 }
1078
1079 snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_11,
1080 RT5682S_ASRCIN_AUTO_CLKOUT_MASK, RT5682S_ASRCIN_AUTO_CLKOUT_EN);
1081
1082 return 0;
1083 }
1084 EXPORT_SYMBOL_GPL(rt5682s_sel_asrc_clk_src);
1085
rt5682s_div_sel(struct rt5682s_priv * rt5682s,int target,const int div[],int size)1086 static int rt5682s_div_sel(struct rt5682s_priv *rt5682s,
1087 int target, const int div[], int size)
1088 {
1089 int i;
1090
1091 if (rt5682s->sysclk < target) {
1092 dev_err(rt5682s->component->dev,
1093 "sysclk rate %d is too low\n", rt5682s->sysclk);
1094 return 0;
1095 }
1096
1097 for (i = 0; i < size - 1; i++) {
1098 dev_dbg(rt5682s->component->dev, "div[%d]=%d\n", i, div[i]);
1099 if (target * div[i] == rt5682s->sysclk)
1100 return i;
1101 if (target * div[i + 1] > rt5682s->sysclk) {
1102 dev_dbg(rt5682s->component->dev,
1103 "can't find div for sysclk %d\n", rt5682s->sysclk);
1104 return i;
1105 }
1106 }
1107
1108 if (target * div[i] < rt5682s->sysclk)
1109 dev_err(rt5682s->component->dev,
1110 "sysclk rate %d is too high\n", rt5682s->sysclk);
1111
1112 return size - 1;
1113 }
1114
get_clk_info(int sclk,int rate)1115 static int get_clk_info(int sclk, int rate)
1116 {
1117 int i;
1118 static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1119
1120 if (sclk <= 0 || rate <= 0)
1121 return -EINVAL;
1122
1123 rate = rate << 8;
1124 for (i = 0; i < ARRAY_SIZE(pd); i++)
1125 if (sclk == rate * pd[i])
1126 return i;
1127
1128 return -EINVAL;
1129 }
1130
1131 /**
1132 * set_dmic_clk - Set parameter of dmic.
1133 *
1134 * @w: DAPM widget.
1135 * @kcontrol: The kcontrol of this widget.
1136 * @event: Event id.
1137 *
1138 * Choose dmic clock between 1MHz and 3MHz.
1139 * It is better for clock to approximate 3MHz.
1140 */
set_dmic_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1141 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1142 struct snd_kcontrol *kcontrol, int event)
1143 {
1144 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1145 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1146 int idx, dmic_clk_rate = 3072000;
1147 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1148
1149 if (rt5682s->pdata.dmic_clk_rate)
1150 dmic_clk_rate = rt5682s->pdata.dmic_clk_rate;
1151
1152 idx = rt5682s_div_sel(rt5682s, dmic_clk_rate, div, ARRAY_SIZE(div));
1153
1154 snd_soc_component_update_bits(component, RT5682S_DMIC_CTRL_1,
1155 RT5682S_DMIC_CLK_MASK, idx << RT5682S_DMIC_CLK_SFT);
1156
1157 return 0;
1158 }
1159
1160
rt5682s_set_pllb_power(struct rt5682s_priv * rt5682s,int on)1161 static int rt5682s_set_pllb_power(struct rt5682s_priv *rt5682s, int on)
1162 {
1163 struct snd_soc_component *component = rt5682s->component;
1164
1165 if (on) {
1166 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3,
1167 RT5682S_PWR_LDO_PLLB | RT5682S_PWR_BIAS_PLLB | RT5682S_PWR_PLLB,
1168 RT5682S_PWR_LDO_PLLB | RT5682S_PWR_BIAS_PLLB | RT5682S_PWR_PLLB);
1169 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3,
1170 RT5682S_RSTB_PLLB, RT5682S_RSTB_PLLB);
1171 } else {
1172 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3,
1173 RT5682S_PWR_LDO_PLLB | RT5682S_PWR_BIAS_PLLB |
1174 RT5682S_RSTB_PLLB | RT5682S_PWR_PLLB, 0);
1175 }
1176
1177 return 0;
1178 }
1179
set_pllb_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1180 static int set_pllb_event(struct snd_soc_dapm_widget *w,
1181 struct snd_kcontrol *kcontrol, int event)
1182 {
1183 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1184 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1185 int on = 0;
1186
1187 if (rt5682s->wclk_enabled)
1188 return 0;
1189
1190 if (SND_SOC_DAPM_EVENT_ON(event))
1191 on = 1;
1192
1193 rt5682s_set_pllb_power(rt5682s, on);
1194
1195 return 0;
1196 }
1197
rt5682s_set_filter_clk(struct rt5682s_priv * rt5682s,int reg,int ref)1198 static void rt5682s_set_filter_clk(struct rt5682s_priv *rt5682s, int reg, int ref)
1199 {
1200 struct snd_soc_component *component = rt5682s->component;
1201 int idx;
1202 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1203 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1204
1205 idx = rt5682s_div_sel(rt5682s, ref, div_f, ARRAY_SIZE(div_f));
1206
1207 snd_soc_component_update_bits(component, reg,
1208 RT5682S_FILTER_CLK_DIV_MASK, idx << RT5682S_FILTER_CLK_DIV_SFT);
1209
1210 /* select over sample rate */
1211 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1212 if (rt5682s->sysclk <= 12288000 * div_o[idx])
1213 break;
1214 }
1215
1216 snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_1,
1217 RT5682S_ADC_OSR_MASK | RT5682S_DAC_OSR_MASK,
1218 (idx << RT5682S_ADC_OSR_SFT) | (idx << RT5682S_DAC_OSR_SFT));
1219 }
1220
set_filter_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1221 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1222 struct snd_kcontrol *kcontrol, int event)
1223 {
1224 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1225 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1226 int ref, reg, val;
1227
1228 val = snd_soc_component_read(component, RT5682S_GPIO_CTRL_1)
1229 & RT5682S_GP4_PIN_MASK;
1230
1231 if (w->shift == RT5682S_PWR_ADC_S1F_BIT && val == RT5682S_GP4_PIN_ADCDAT2)
1232 ref = 256 * rt5682s->lrck[RT5682S_AIF2];
1233 else
1234 ref = 256 * rt5682s->lrck[RT5682S_AIF1];
1235
1236 if (w->shift == RT5682S_PWR_ADC_S1F_BIT)
1237 reg = RT5682S_PLL_TRACK_3;
1238 else
1239 reg = RT5682S_PLL_TRACK_2;
1240
1241 rt5682s_set_filter_clk(rt5682s, reg, ref);
1242
1243 return 0;
1244 }
1245
set_dmic_power(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1246 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1247 struct snd_kcontrol *kcontrol, int event)
1248 {
1249 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1250 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1251 unsigned int delay = 50, val;
1252
1253 if (rt5682s->pdata.dmic_delay)
1254 delay = rt5682s->pdata.dmic_delay;
1255
1256 switch (event) {
1257 case SND_SOC_DAPM_POST_PMU:
1258 val = (snd_soc_component_read(component, RT5682S_GLB_CLK)
1259 & RT5682S_SCLK_SRC_MASK) >> RT5682S_SCLK_SRC_SFT;
1260 if (val == RT5682S_CLK_SRC_PLL1 || val == RT5682S_CLK_SRC_PLL2)
1261 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
1262 RT5682S_PWR_VREF2 | RT5682S_PWR_MB,
1263 RT5682S_PWR_VREF2 | RT5682S_PWR_MB);
1264
1265 /*Add delay to avoid pop noise*/
1266 msleep(delay);
1267 break;
1268
1269 case SND_SOC_DAPM_POST_PMD:
1270 if (!rt5682s->jack_type && !rt5682s->wclk_enabled) {
1271 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
1272 RT5682S_PWR_VREF2 | RT5682S_PWR_MB, 0);
1273 }
1274 break;
1275 }
1276
1277 return 0;
1278 }
1279
rt5682s_set_i2s(struct rt5682s_priv * rt5682s,int id,int on)1280 static void rt5682s_set_i2s(struct rt5682s_priv *rt5682s, int id, int on)
1281 {
1282 struct snd_soc_component *component = rt5682s->component;
1283 int pre_div;
1284 unsigned int p_reg, p_mask, p_sft;
1285 unsigned int c_reg, c_mask, c_sft;
1286
1287 if (id == RT5682S_AIF1) {
1288 c_reg = RT5682S_ADDA_CLK_1;
1289 c_mask = RT5682S_I2S_M_D_MASK;
1290 c_sft = RT5682S_I2S_M_D_SFT;
1291 p_reg = RT5682S_PWR_DIG_1;
1292 p_mask = RT5682S_PWR_I2S1;
1293 p_sft = RT5682S_PWR_I2S1_BIT;
1294 } else {
1295 c_reg = RT5682S_I2S2_M_CLK_CTRL_1;
1296 c_mask = RT5682S_I2S2_M_D_MASK;
1297 c_sft = RT5682S_I2S2_M_D_SFT;
1298 p_reg = RT5682S_PWR_DIG_1;
1299 p_mask = RT5682S_PWR_I2S2;
1300 p_sft = RT5682S_PWR_I2S2_BIT;
1301 }
1302
1303 if (on && rt5682s->master[id]) {
1304 pre_div = get_clk_info(rt5682s->sysclk, rt5682s->lrck[id]);
1305 if (pre_div < 0) {
1306 dev_err(component->dev, "get pre_div failed\n");
1307 return;
1308 }
1309
1310 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d master\n",
1311 rt5682s->lrck[id], pre_div, id);
1312 snd_soc_component_update_bits(component, c_reg, c_mask, pre_div << c_sft);
1313 }
1314
1315 snd_soc_component_update_bits(component, p_reg, p_mask, on << p_sft);
1316 }
1317
set_i2s_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1318 static int set_i2s_event(struct snd_soc_dapm_widget *w,
1319 struct snd_kcontrol *kcontrol, int event)
1320 {
1321 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1322 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1323 int on = 0;
1324
1325 if (SND_SOC_DAPM_EVENT_ON(event))
1326 on = 1;
1327
1328 if (!strcmp(w->name, "I2S1") && !rt5682s->wclk_enabled)
1329 rt5682s_set_i2s(rt5682s, RT5682S_AIF1, on);
1330 else if (!strcmp(w->name, "I2S2"))
1331 rt5682s_set_i2s(rt5682s, RT5682S_AIF2, on);
1332
1333 return 0;
1334 }
1335
is_sys_clk_from_plla(struct snd_soc_dapm_widget * w,struct snd_soc_dapm_widget * sink)1336 static int is_sys_clk_from_plla(struct snd_soc_dapm_widget *w,
1337 struct snd_soc_dapm_widget *sink)
1338 {
1339 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1340 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1341
1342 if ((rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL1) ||
1343 (rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL2 && rt5682s->pll_comb == USE_PLLAB))
1344 return 1;
1345
1346 return 0;
1347 }
1348
is_sys_clk_from_pllb(struct snd_soc_dapm_widget * w,struct snd_soc_dapm_widget * sink)1349 static int is_sys_clk_from_pllb(struct snd_soc_dapm_widget *w,
1350 struct snd_soc_dapm_widget *sink)
1351 {
1352 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1353 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1354
1355 if (rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL2)
1356 return 1;
1357
1358 return 0;
1359 }
1360
is_using_asrc(struct snd_soc_dapm_widget * w,struct snd_soc_dapm_widget * sink)1361 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1362 struct snd_soc_dapm_widget *sink)
1363 {
1364 unsigned int reg, sft, val;
1365 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1366
1367 switch (w->shift) {
1368 case RT5682S_ADC_STO1_ASRC_SFT:
1369 reg = RT5682S_PLL_TRACK_3;
1370 sft = RT5682S_FILTER_CLK_SEL_SFT;
1371 break;
1372 case RT5682S_DAC_STO1_ASRC_SFT:
1373 reg = RT5682S_PLL_TRACK_2;
1374 sft = RT5682S_FILTER_CLK_SEL_SFT;
1375 break;
1376 default:
1377 return 0;
1378 }
1379
1380 val = (snd_soc_component_read(component, reg) >> sft) & 0xf;
1381 switch (val) {
1382 case RT5682S_CLK_SEL_I2S1_ASRC:
1383 case RT5682S_CLK_SEL_I2S2_ASRC:
1384 return 1;
1385 default:
1386 return 0;
1387 }
1388 }
1389
rt5682s_hp_amp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1390 static int rt5682s_hp_amp_event(struct snd_soc_dapm_widget *w,
1391 struct snd_kcontrol *kcontrol, int event)
1392 {
1393 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1394
1395 switch (event) {
1396 case SND_SOC_DAPM_POST_PMU:
1397 snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
1398 RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN,
1399 RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN);
1400 usleep_range(15000, 20000);
1401 snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
1402 RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN |
1403 RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN,
1404 RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN |
1405 RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN);
1406 snd_soc_component_write(component, RT5682S_BIAS_CUR_CTRL_11, 0x6666);
1407 snd_soc_component_write(component, RT5682S_BIAS_CUR_CTRL_12, 0xa82a);
1408
1409 snd_soc_component_update_bits(component, RT5682S_HP_CTRL_2,
1410 RT5682S_HPO_L_PATH_MASK | RT5682S_HPO_R_PATH_MASK |
1411 RT5682S_HPO_SEL_IP_EN_SW, RT5682S_HPO_L_PATH_EN |
1412 RT5682S_HPO_R_PATH_EN | RT5682S_HPO_IP_EN_GATING);
1413 usleep_range(5000, 10000);
1414 snd_soc_component_update_bits(component, RT5682S_HP_AMP_DET_CTL_1,
1415 RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_L | RT5682S_CP_SW_SIZE_S);
1416 break;
1417
1418 case SND_SOC_DAPM_POST_PMD:
1419 snd_soc_component_update_bits(component, RT5682S_HP_CTRL_2,
1420 RT5682S_HPO_L_PATH_MASK | RT5682S_HPO_R_PATH_MASK |
1421 RT5682S_HPO_SEL_IP_EN_SW, 0);
1422 snd_soc_component_update_bits(component, RT5682S_HP_AMP_DET_CTL_1,
1423 RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_M);
1424 snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
1425 RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN |
1426 RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN, 0);
1427 snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
1428 RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN, 0);
1429 break;
1430 }
1431
1432 return 0;
1433 }
1434
rt5682s_stereo1_adc_mixl_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1435 static int rt5682s_stereo1_adc_mixl_event(struct snd_soc_dapm_widget *w,
1436 struct snd_kcontrol *kcontrol, int event)
1437 {
1438 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1439 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1440 unsigned int delay = 0;
1441
1442 if (rt5682s->pdata.amic_delay)
1443 delay = rt5682s->pdata.amic_delay;
1444
1445 switch (event) {
1446 case SND_SOC_DAPM_POST_PMU:
1447 msleep(delay);
1448 snd_soc_component_update_bits(component, RT5682S_STO1_ADC_DIG_VOL,
1449 RT5682S_L_MUTE, 0);
1450 break;
1451 case SND_SOC_DAPM_PRE_PMD:
1452 snd_soc_component_update_bits(component, RT5682S_STO1_ADC_DIG_VOL,
1453 RT5682S_L_MUTE, RT5682S_L_MUTE);
1454 break;
1455 }
1456
1457 return 0;
1458 }
1459
sar_power_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1460 static int sar_power_event(struct snd_soc_dapm_widget *w,
1461 struct snd_kcontrol *kcontrol, int event)
1462 {
1463 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1464 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1465
1466 if ((rt5682s->jack_type & SND_JACK_HEADSET) != SND_JACK_HEADSET)
1467 return 0;
1468
1469 switch (event) {
1470 case SND_SOC_DAPM_PRE_PMU:
1471 rt5682s_sar_power_mode(component, SAR_PWR_NORMAL);
1472 break;
1473 case SND_SOC_DAPM_POST_PMD:
1474 rt5682s_sar_power_mode(component, SAR_PWR_SAVING);
1475 break;
1476 }
1477
1478 return 0;
1479 }
1480
1481 /* Interface data select */
1482 static const char * const rt5682s_data_select[] = {
1483 "L/R", "R/L", "L/L", "R/R"
1484 };
1485
1486 static SOC_ENUM_SINGLE_DECL(rt5682s_if2_adc_enum, RT5682S_DIG_INF2_DATA,
1487 RT5682S_IF2_ADC_SEL_SFT, rt5682s_data_select);
1488
1489 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_01_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
1490 RT5682S_IF1_ADC1_SEL_SFT, rt5682s_data_select);
1491
1492 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_23_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
1493 RT5682S_IF1_ADC2_SEL_SFT, rt5682s_data_select);
1494
1495 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_45_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
1496 RT5682S_IF1_ADC3_SEL_SFT, rt5682s_data_select);
1497
1498 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_67_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
1499 RT5682S_IF1_ADC4_SEL_SFT, rt5682s_data_select);
1500
1501 static const struct snd_kcontrol_new rt5682s_if2_adc_swap_mux =
1502 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682s_if2_adc_enum);
1503
1504 static const struct snd_kcontrol_new rt5682s_if1_01_adc_swap_mux =
1505 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682s_if1_01_adc_enum);
1506
1507 static const struct snd_kcontrol_new rt5682s_if1_23_adc_swap_mux =
1508 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682s_if1_23_adc_enum);
1509
1510 static const struct snd_kcontrol_new rt5682s_if1_45_adc_swap_mux =
1511 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682s_if1_45_adc_enum);
1512
1513 static const struct snd_kcontrol_new rt5682s_if1_67_adc_swap_mux =
1514 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682s_if1_67_adc_enum);
1515
1516 /* Digital Mixer */
1517 static const struct snd_kcontrol_new rt5682s_sto1_adc_l_mix[] = {
1518 SOC_DAPM_SINGLE("ADC1 Switch", RT5682S_STO1_ADC_MIXER,
1519 RT5682S_M_STO1_ADC_L1_SFT, 1, 1),
1520 SOC_DAPM_SINGLE("ADC2 Switch", RT5682S_STO1_ADC_MIXER,
1521 RT5682S_M_STO1_ADC_L2_SFT, 1, 1),
1522 };
1523
1524 static const struct snd_kcontrol_new rt5682s_sto1_adc_r_mix[] = {
1525 SOC_DAPM_SINGLE("ADC1 Switch", RT5682S_STO1_ADC_MIXER,
1526 RT5682S_M_STO1_ADC_R1_SFT, 1, 1),
1527 SOC_DAPM_SINGLE("ADC2 Switch", RT5682S_STO1_ADC_MIXER,
1528 RT5682S_M_STO1_ADC_R2_SFT, 1, 1),
1529 };
1530
1531 static const struct snd_kcontrol_new rt5682s_dac_l_mix[] = {
1532 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682S_AD_DA_MIXER,
1533 RT5682S_M_ADCMIX_L_SFT, 1, 1),
1534 SOC_DAPM_SINGLE("DAC1 Switch", RT5682S_AD_DA_MIXER,
1535 RT5682S_M_DAC1_L_SFT, 1, 1),
1536 };
1537
1538 static const struct snd_kcontrol_new rt5682s_dac_r_mix[] = {
1539 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682S_AD_DA_MIXER,
1540 RT5682S_M_ADCMIX_R_SFT, 1, 1),
1541 SOC_DAPM_SINGLE("DAC1 Switch", RT5682S_AD_DA_MIXER,
1542 RT5682S_M_DAC1_R_SFT, 1, 1),
1543 };
1544
1545 static const struct snd_kcontrol_new rt5682s_sto1_dac_l_mix[] = {
1546 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682S_STO1_DAC_MIXER,
1547 RT5682S_M_DAC_L1_STO_L_SFT, 1, 1),
1548 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682S_STO1_DAC_MIXER,
1549 RT5682S_M_DAC_R1_STO_L_SFT, 1, 1),
1550 };
1551
1552 static const struct snd_kcontrol_new rt5682s_sto1_dac_r_mix[] = {
1553 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682S_STO1_DAC_MIXER,
1554 RT5682S_M_DAC_L1_STO_R_SFT, 1, 1),
1555 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682S_STO1_DAC_MIXER,
1556 RT5682S_M_DAC_R1_STO_R_SFT, 1, 1),
1557 };
1558
1559 /* Analog Input Mixer */
1560 static const struct snd_kcontrol_new rt5682s_rec1_l_mix[] = {
1561 SOC_DAPM_SINGLE("CBJ Switch", RT5682S_REC_MIXER,
1562 RT5682S_M_CBJ_RM1_L_SFT, 1, 1),
1563 };
1564
1565 static const struct snd_kcontrol_new rt5682s_rec1_r_mix[] = {
1566 SOC_DAPM_SINGLE("CBJ Switch", RT5682S_REC_MIXER,
1567 RT5682S_M_CBJ_RM1_R_SFT, 1, 1),
1568 };
1569
1570 /* STO1 ADC1 Source */
1571 /* MX-26 [13] [5] */
1572 static const char * const rt5682s_sto1_adc1_src[] = {
1573 "DAC MIX", "ADC"
1574 };
1575
1576 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc1l_enum, RT5682S_STO1_ADC_MIXER,
1577 RT5682S_STO1_ADC1L_SRC_SFT, rt5682s_sto1_adc1_src);
1578
1579 static const struct snd_kcontrol_new rt5682s_sto1_adc1l_mux =
1580 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682s_sto1_adc1l_enum);
1581
1582 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc1r_enum, RT5682S_STO1_ADC_MIXER,
1583 RT5682S_STO1_ADC1R_SRC_SFT, rt5682s_sto1_adc1_src);
1584
1585 static const struct snd_kcontrol_new rt5682s_sto1_adc1r_mux =
1586 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682s_sto1_adc1r_enum);
1587
1588 /* STO1 ADC Source */
1589 /* MX-26 [11:10] [3:2] */
1590 static const char * const rt5682s_sto1_adc_src[] = {
1591 "ADC1 L", "ADC1 R"
1592 };
1593
1594 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adcl_enum, RT5682S_STO1_ADC_MIXER,
1595 RT5682S_STO1_ADCL_SRC_SFT, rt5682s_sto1_adc_src);
1596
1597 static const struct snd_kcontrol_new rt5682s_sto1_adcl_mux =
1598 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682s_sto1_adcl_enum);
1599
1600 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adcr_enum, RT5682S_STO1_ADC_MIXER,
1601 RT5682S_STO1_ADCR_SRC_SFT, rt5682s_sto1_adc_src);
1602
1603 static const struct snd_kcontrol_new rt5682s_sto1_adcr_mux =
1604 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682s_sto1_adcr_enum);
1605
1606 /* STO1 ADC2 Source */
1607 /* MX-26 [12] [4] */
1608 static const char * const rt5682s_sto1_adc2_src[] = {
1609 "DAC MIX", "DMIC"
1610 };
1611
1612 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc2l_enum, RT5682S_STO1_ADC_MIXER,
1613 RT5682S_STO1_ADC2L_SRC_SFT, rt5682s_sto1_adc2_src);
1614
1615 static const struct snd_kcontrol_new rt5682s_sto1_adc2l_mux =
1616 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682s_sto1_adc2l_enum);
1617
1618 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc2r_enum, RT5682S_STO1_ADC_MIXER,
1619 RT5682S_STO1_ADC2R_SRC_SFT, rt5682s_sto1_adc2_src);
1620
1621 static const struct snd_kcontrol_new rt5682s_sto1_adc2r_mux =
1622 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682s_sto1_adc2r_enum);
1623
1624 /* MX-79 [6:4] I2S1 ADC data location */
1625 static const unsigned int rt5682s_if1_adc_slot_values[] = {
1626 0, 2, 4, 6,
1627 };
1628
1629 static const char * const rt5682s_if1_adc_slot_src[] = {
1630 "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1631 };
1632
1633 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682s_if1_adc_slot_enum,
1634 RT5682S_TDM_CTRL, RT5682S_TDM_ADC_LCA_SFT, RT5682S_TDM_ADC_LCA_MASK,
1635 rt5682s_if1_adc_slot_src, rt5682s_if1_adc_slot_values);
1636
1637 static const struct snd_kcontrol_new rt5682s_if1_adc_slot_mux =
1638 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682s_if1_adc_slot_enum);
1639
1640 /* Analog DAC L1 Source, Analog DAC R1 Source*/
1641 /* MX-2B [4], MX-2B [0]*/
1642 static const char * const rt5682s_alg_dac1_src[] = {
1643 "Stereo1 DAC Mixer", "DAC1"
1644 };
1645
1646 static SOC_ENUM_SINGLE_DECL(rt5682s_alg_dac_l1_enum, RT5682S_A_DAC1_MUX,
1647 RT5682S_A_DACL1_SFT, rt5682s_alg_dac1_src);
1648
1649 static const struct snd_kcontrol_new rt5682s_alg_dac_l1_mux =
1650 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682s_alg_dac_l1_enum);
1651
1652 static SOC_ENUM_SINGLE_DECL(rt5682s_alg_dac_r1_enum, RT5682S_A_DAC1_MUX,
1653 RT5682S_A_DACR1_SFT, rt5682s_alg_dac1_src);
1654
1655 static const struct snd_kcontrol_new rt5682s_alg_dac_r1_mux =
1656 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682s_alg_dac_r1_enum);
1657
1658 static const unsigned int rt5682s_adcdat_pin_values[] = {
1659 1, 3,
1660 };
1661
1662 static const char * const rt5682s_adcdat_pin_select[] = {
1663 "ADCDAT1", "ADCDAT2",
1664 };
1665
1666 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682s_adcdat_pin_enum,
1667 RT5682S_GPIO_CTRL_1, RT5682S_GP4_PIN_SFT, RT5682S_GP4_PIN_MASK,
1668 rt5682s_adcdat_pin_select, rt5682s_adcdat_pin_values);
1669
1670 static const struct snd_kcontrol_new rt5682s_adcdat_pin_ctrl =
1671 SOC_DAPM_ENUM("ADCDAT", rt5682s_adcdat_pin_enum);
1672
1673 static const struct snd_soc_dapm_widget rt5682s_dapm_widgets[] = {
1674 SND_SOC_DAPM_SUPPLY("LDO MB1", RT5682S_PWR_ANLG_3,
1675 RT5682S_PWR_LDO_MB1_BIT, 0, NULL, 0),
1676 SND_SOC_DAPM_SUPPLY("LDO MB2", RT5682S_PWR_ANLG_3,
1677 RT5682S_PWR_LDO_MB2_BIT, 0, NULL, 0),
1678 SND_SOC_DAPM_SUPPLY("LDO", RT5682S_PWR_ANLG_3,
1679 RT5682S_PWR_LDO_BIT, 0, NULL, 0),
1680
1681 /* PLL Powers */
1682 SND_SOC_DAPM_SUPPLY_S("PLLA_LDO", 0, RT5682S_PWR_ANLG_3,
1683 RT5682S_PWR_LDO_PLLA_BIT, 0, NULL, 0),
1684 SND_SOC_DAPM_SUPPLY_S("PLLA_BIAS", 0, RT5682S_PWR_ANLG_3,
1685 RT5682S_PWR_BIAS_PLLA_BIT, 0, NULL, 0),
1686 SND_SOC_DAPM_SUPPLY_S("PLLA", 0, RT5682S_PWR_ANLG_3,
1687 RT5682S_PWR_PLLA_BIT, 0, NULL, 0),
1688 SND_SOC_DAPM_SUPPLY_S("PLLA_RST", 1, RT5682S_PWR_ANLG_3,
1689 RT5682S_RSTB_PLLA_BIT, 0, NULL, 0),
1690 SND_SOC_DAPM_SUPPLY("PLLB", SND_SOC_NOPM, 0, 0,
1691 set_pllb_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1692
1693 /* ASRC */
1694 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682S_PLL_TRACK_1,
1695 RT5682S_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1696 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682S_PLL_TRACK_1,
1697 RT5682S_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1698 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682S_PLL_TRACK_1,
1699 RT5682S_AD_ASRC_SFT, 0, NULL, 0),
1700 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682S_PLL_TRACK_1,
1701 RT5682S_DA_ASRC_SFT, 0, NULL, 0),
1702 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682S_PLL_TRACK_1,
1703 RT5682S_DMIC_ASRC_SFT, 0, NULL, 0),
1704
1705 /* Input Side */
1706 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682S_PWR_ANLG_2,
1707 RT5682S_PWR_MB1_BIT, 0, NULL, 0),
1708 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682S_PWR_ANLG_2,
1709 RT5682S_PWR_MB2_BIT, 0, NULL, 0),
1710
1711 /* Input Lines */
1712 SND_SOC_DAPM_INPUT("DMIC L1"),
1713 SND_SOC_DAPM_INPUT("DMIC R1"),
1714
1715 SND_SOC_DAPM_INPUT("IN1P"),
1716
1717 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1718 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1719 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682S_DMIC_CTRL_1, RT5682S_DMIC_1_EN_SFT, 0,
1720 set_dmic_power, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1721
1722 /* Boost */
1723 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
1724
1725 /* REC Mixer */
1726 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682s_rec1_l_mix,
1727 ARRAY_SIZE(rt5682s_rec1_l_mix)),
1728 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5682s_rec1_r_mix,
1729 ARRAY_SIZE(rt5682s_rec1_r_mix)),
1730 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682S_CAL_REC,
1731 RT5682S_PWR_RM1_L_BIT, 0, NULL, 0),
1732 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5682S_CAL_REC,
1733 RT5682S_PWR_RM1_R_BIT, 0, NULL, 0),
1734
1735 /* ADCs */
1736 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1737 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1738
1739 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682S_PWR_DIG_1,
1740 RT5682S_PWR_ADC_L1_BIT, 0, NULL, 0),
1741 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682S_PWR_DIG_1,
1742 RT5682S_PWR_ADC_R1_BIT, 0, NULL, 0),
1743 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682S_CHOP_ADC,
1744 RT5682S_CKGEN_ADC1_SFT, 0, NULL, 0),
1745
1746 /* ADC Mux */
1747 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1748 &rt5682s_sto1_adc1l_mux),
1749 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1750 &rt5682s_sto1_adc1r_mux),
1751 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1752 &rt5682s_sto1_adc2l_mux),
1753 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1754 &rt5682s_sto1_adc2r_mux),
1755 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1756 &rt5682s_sto1_adcl_mux),
1757 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1758 &rt5682s_sto1_adcr_mux),
1759 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1760 &rt5682s_if1_adc_slot_mux),
1761
1762 /* ADC Mixer */
1763 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682S_PWR_DIG_2,
1764 RT5682S_PWR_ADC_S1F_BIT, 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1765 SND_SOC_DAPM_MIXER_E("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1766 rt5682s_sto1_adc_l_mix, ARRAY_SIZE(rt5682s_sto1_adc_l_mix),
1767 rt5682s_stereo1_adc_mixl_event,
1768 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1769 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682S_STO1_ADC_DIG_VOL,
1770 RT5682S_R_MUTE_SFT, 1, rt5682s_sto1_adc_r_mix,
1771 ARRAY_SIZE(rt5682s_sto1_adc_r_mix)),
1772
1773 /* ADC PGA */
1774 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1775
1776 /* Digital Interface */
1777 SND_SOC_DAPM_SUPPLY("I2S1", SND_SOC_NOPM, 0, 0,
1778 set_i2s_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1779 SND_SOC_DAPM_SUPPLY("I2S2", SND_SOC_NOPM, 0, 0,
1780 set_i2s_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1781 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1782 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1783
1784 /* Digital Interface Select */
1785 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1786 &rt5682s_if1_01_adc_swap_mux),
1787 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1788 &rt5682s_if1_23_adc_swap_mux),
1789 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1790 &rt5682s_if1_45_adc_swap_mux),
1791 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1792 &rt5682s_if1_67_adc_swap_mux),
1793 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1794 &rt5682s_if2_adc_swap_mux),
1795
1796 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, &rt5682s_adcdat_pin_ctrl),
1797
1798 /* Audio Interface */
1799 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, RT5682S_I2S1_SDP,
1800 RT5682S_SEL_ADCDAT_SFT, 1),
1801 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, RT5682S_I2S2_SDP,
1802 RT5682S_I2S2_PIN_CFG_SFT, 1),
1803 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1804
1805 /* Output Side */
1806 /* DAC mixer before sound effect */
1807 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1808 rt5682s_dac_l_mix, ARRAY_SIZE(rt5682s_dac_l_mix)),
1809 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1810 rt5682s_dac_r_mix, ARRAY_SIZE(rt5682s_dac_r_mix)),
1811
1812 /* DAC channel Mux */
1813 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, &rt5682s_alg_dac_l1_mux),
1814 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, &rt5682s_alg_dac_r1_mux),
1815
1816 /* DAC Mixer */
1817 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682S_PWR_DIG_2,
1818 RT5682S_PWR_DAC_S1F_BIT, 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1819 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1820 rt5682s_sto1_dac_l_mix, ARRAY_SIZE(rt5682s_sto1_dac_l_mix)),
1821 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1822 rt5682s_sto1_dac_r_mix, ARRAY_SIZE(rt5682s_sto1_dac_r_mix)),
1823
1824 /* DACs */
1825 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682S_PWR_DIG_1, RT5682S_PWR_DAC_L1_BIT, 0),
1826 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682S_PWR_DIG_1, RT5682S_PWR_DAC_R1_BIT, 0),
1827
1828 /* HPO */
1829 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682s_hp_amp_event,
1830 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
1831
1832 /* CLK DET */
1833 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682S_CLK_DET,
1834 RT5682S_SYS_CLK_DET_SFT, 0, NULL, 0),
1835 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682S_CLK_DET,
1836 RT5682S_PLL1_CLK_DET_SFT, 0, NULL, 0),
1837 SND_SOC_DAPM_SUPPLY("MCLK0 DET PWR", RT5682S_PWR_ANLG_2,
1838 RT5682S_PWR_MCLK0_WD_BIT, 0, NULL, 0),
1839
1840 /* SAR */
1841 SND_SOC_DAPM_SUPPLY("SAR", SND_SOC_NOPM, 0, 0, sar_power_event,
1842 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1843
1844 /* Output Lines */
1845 SND_SOC_DAPM_OUTPUT("HPOL"),
1846 SND_SOC_DAPM_OUTPUT("HPOR"),
1847 };
1848
1849 static const struct snd_soc_dapm_route rt5682s_dapm_routes[] = {
1850 /*PLL*/
1851 {"ADC Stereo1 Filter", NULL, "PLLA", is_sys_clk_from_plla},
1852 {"ADC Stereo1 Filter", NULL, "PLLB", is_sys_clk_from_pllb},
1853 {"DAC Stereo1 Filter", NULL, "PLLA", is_sys_clk_from_plla},
1854 {"DAC Stereo1 Filter", NULL, "PLLB", is_sys_clk_from_pllb},
1855 {"PLLA", NULL, "PLLA_LDO"},
1856 {"PLLA", NULL, "PLLA_BIAS"},
1857 {"PLLA", NULL, "PLLA_RST"},
1858
1859 /*ASRC*/
1860 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1861 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1862 {"ADC STO1 ASRC", NULL, "AD ASRC"},
1863 {"ADC STO1 ASRC", NULL, "DA ASRC"},
1864 {"DAC STO1 ASRC", NULL, "AD ASRC"},
1865 {"DAC STO1 ASRC", NULL, "DA ASRC"},
1866
1867 {"CLKDET SYS", NULL, "MCLK0 DET PWR"},
1868
1869 {"BST1 CBJ", NULL, "IN1P"},
1870 {"BST1 CBJ", NULL, "SAR"},
1871
1872 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1873 {"RECMIX1L", NULL, "RECMIX1L Power"},
1874 {"RECMIX1R", "CBJ Switch", "BST1 CBJ"},
1875 {"RECMIX1R", NULL, "RECMIX1R Power"},
1876
1877 {"ADC1 L", NULL, "RECMIX1L"},
1878 {"ADC1 L", NULL, "ADC1 L Power"},
1879 {"ADC1 L", NULL, "ADC1 clock"},
1880 {"ADC1 R", NULL, "RECMIX1R"},
1881 {"ADC1 R", NULL, "ADC1 R Power"},
1882 {"ADC1 R", NULL, "ADC1 clock"},
1883
1884 {"DMIC L1", NULL, "DMIC CLK"},
1885 {"DMIC L1", NULL, "DMIC1 Power"},
1886 {"DMIC R1", NULL, "DMIC CLK"},
1887 {"DMIC R1", NULL, "DMIC1 Power"},
1888 {"DMIC CLK", NULL, "DMIC ASRC"},
1889
1890 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1891 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1892 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1893 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1894
1895 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1896 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1897 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1898 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1899
1900 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1901 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1902 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1903 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1904
1905 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1906 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1907 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1908
1909 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1910 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1911 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1912
1913 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1914 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1915
1916 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1917 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1918 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1919 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1920 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1921 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1922 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1923 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1924 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1925 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1926 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1927 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1928 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1929 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1930 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1931 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1932
1933 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1934 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1935 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1936 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1937 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1938 {"AIF1TX", NULL, "I2S1"},
1939 {"AIF1TX", NULL, "ADCDAT Mux"},
1940 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1941 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1942 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1943 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1944 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1945 {"AIF2TX", NULL, "ADCDAT Mux"},
1946
1947 {"IF1 DAC1 L", NULL, "AIF1RX"},
1948 {"IF1 DAC1 L", NULL, "I2S1"},
1949 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1950 {"IF1 DAC1 R", NULL, "AIF1RX"},
1951 {"IF1 DAC1 R", NULL, "I2S1"},
1952 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1953
1954 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1955 {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"},
1956 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1957 {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"},
1958
1959 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1960 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
1961
1962 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
1963 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
1964
1965 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
1966 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
1967 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
1968 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
1969
1970 {"DAC L1", NULL, "DAC L1 Source"},
1971 {"DAC R1", NULL, "DAC R1 Source"},
1972
1973 {"HP Amp", NULL, "DAC L1"},
1974 {"HP Amp", NULL, "DAC R1"},
1975 {"HP Amp", NULL, "CLKDET SYS"},
1976 {"HP Amp", NULL, "SAR"},
1977
1978 {"HPOL", NULL, "HP Amp"},
1979 {"HPOR", NULL, "HP Amp"},
1980 };
1981
rt5682s_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)1982 static int rt5682s_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1983 unsigned int rx_mask, int slots, int slot_width)
1984 {
1985 struct snd_soc_component *component = dai->component;
1986 unsigned int cl, val = 0, tx_slotnum;
1987
1988 if (tx_mask || rx_mask)
1989 snd_soc_component_update_bits(component,
1990 RT5682S_TDM_ADDA_CTRL_2, RT5682S_TDM_EN, RT5682S_TDM_EN);
1991 else
1992 snd_soc_component_update_bits(component,
1993 RT5682S_TDM_ADDA_CTRL_2, RT5682S_TDM_EN, 0);
1994
1995 /* Tx slot configuration */
1996 tx_slotnum = hweight_long(tx_mask);
1997 if (tx_slotnum) {
1998 if (tx_slotnum > slots) {
1999 dev_err(component->dev, "Invalid or oversized Tx slots.\n");
2000 return -EINVAL;
2001 }
2002 val |= (tx_slotnum - 1) << RT5682S_TDM_ADC_DL_SFT;
2003 }
2004
2005 switch (slots) {
2006 case 4:
2007 val |= RT5682S_TDM_TX_CH_4;
2008 val |= RT5682S_TDM_RX_CH_4;
2009 break;
2010 case 6:
2011 val |= RT5682S_TDM_TX_CH_6;
2012 val |= RT5682S_TDM_RX_CH_6;
2013 break;
2014 case 8:
2015 val |= RT5682S_TDM_TX_CH_8;
2016 val |= RT5682S_TDM_RX_CH_8;
2017 break;
2018 case 2:
2019 break;
2020 default:
2021 return -EINVAL;
2022 }
2023
2024 snd_soc_component_update_bits(component, RT5682S_TDM_CTRL,
2025 RT5682S_TDM_TX_CH_MASK | RT5682S_TDM_RX_CH_MASK |
2026 RT5682S_TDM_ADC_DL_MASK, val);
2027
2028 switch (slot_width) {
2029 case 8:
2030 if (tx_mask || rx_mask)
2031 return -EINVAL;
2032 cl = RT5682S_I2S1_TX_CHL_8 | RT5682S_I2S1_RX_CHL_8;
2033 break;
2034 case 16:
2035 val = RT5682S_TDM_CL_16;
2036 cl = RT5682S_I2S1_TX_CHL_16 | RT5682S_I2S1_RX_CHL_16;
2037 break;
2038 case 20:
2039 val = RT5682S_TDM_CL_20;
2040 cl = RT5682S_I2S1_TX_CHL_20 | RT5682S_I2S1_RX_CHL_20;
2041 break;
2042 case 24:
2043 val = RT5682S_TDM_CL_24;
2044 cl = RT5682S_I2S1_TX_CHL_24 | RT5682S_I2S1_RX_CHL_24;
2045 break;
2046 case 32:
2047 val = RT5682S_TDM_CL_32;
2048 cl = RT5682S_I2S1_TX_CHL_32 | RT5682S_I2S1_RX_CHL_32;
2049 break;
2050 default:
2051 return -EINVAL;
2052 }
2053
2054 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2055 RT5682S_TDM_CL_MASK, val);
2056 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2057 RT5682S_I2S1_TX_CHL_MASK | RT5682S_I2S1_RX_CHL_MASK, cl);
2058
2059 return 0;
2060 }
2061
rt5682s_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)2062 static int rt5682s_hw_params(struct snd_pcm_substream *substream,
2063 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2064 {
2065 struct snd_soc_component *component = dai->component;
2066 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2067 unsigned int len_1 = 0, len_2 = 0;
2068 int frame_size;
2069
2070 rt5682s->lrck[dai->id] = params_rate(params);
2071
2072 frame_size = snd_soc_params_to_frame_size(params);
2073 if (frame_size < 0) {
2074 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
2075 return -EINVAL;
2076 }
2077
2078 switch (params_width(params)) {
2079 case 16:
2080 break;
2081 case 20:
2082 len_1 |= RT5682S_I2S1_DL_20;
2083 len_2 |= RT5682S_I2S2_DL_20;
2084 break;
2085 case 24:
2086 len_1 |= RT5682S_I2S1_DL_24;
2087 len_2 |= RT5682S_I2S2_DL_24;
2088 break;
2089 case 32:
2090 len_1 |= RT5682S_I2S1_DL_32;
2091 len_2 |= RT5682S_I2S2_DL_24;
2092 break;
2093 case 8:
2094 len_1 |= RT5682S_I2S2_DL_8;
2095 len_2 |= RT5682S_I2S2_DL_8;
2096 break;
2097 default:
2098 return -EINVAL;
2099 }
2100
2101 switch (dai->id) {
2102 case RT5682S_AIF1:
2103 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2104 RT5682S_I2S1_DL_MASK, len_1);
2105 if (params_channels(params) == 1) /* mono mode */
2106 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2107 RT5682S_I2S1_MONO_MASK, RT5682S_I2S1_MONO_EN);
2108 else
2109 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2110 RT5682S_I2S1_MONO_MASK, RT5682S_I2S1_MONO_DIS);
2111 break;
2112 case RT5682S_AIF2:
2113 snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
2114 RT5682S_I2S2_DL_MASK, len_2);
2115 if (params_channels(params) == 1) /* mono mode */
2116 snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
2117 RT5682S_I2S2_MONO_MASK, RT5682S_I2S2_MONO_EN);
2118 else
2119 snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
2120 RT5682S_I2S2_MONO_MASK, RT5682S_I2S2_MONO_DIS);
2121 break;
2122 default:
2123 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2124 return -EINVAL;
2125 }
2126
2127 return 0;
2128 }
2129
rt5682s_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)2130 static int rt5682s_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2131 {
2132 struct snd_soc_component *component = dai->component;
2133 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2134 unsigned int reg_val = 0, tdm_ctrl = 0;
2135
2136 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2137 case SND_SOC_DAIFMT_CBM_CFM:
2138 rt5682s->master[dai->id] = 1;
2139 break;
2140 case SND_SOC_DAIFMT_CBS_CFS:
2141 rt5682s->master[dai->id] = 0;
2142 break;
2143 default:
2144 return -EINVAL;
2145 }
2146
2147 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2148 case SND_SOC_DAIFMT_NB_NF:
2149 break;
2150 case SND_SOC_DAIFMT_IB_NF:
2151 reg_val |= RT5682S_I2S_BP_INV;
2152 tdm_ctrl |= RT5682S_TDM_S_BP_INV;
2153 break;
2154 case SND_SOC_DAIFMT_NB_IF:
2155 if (dai->id == RT5682S_AIF1)
2156 tdm_ctrl |= RT5682S_TDM_S_LP_INV | RT5682S_TDM_M_BP_INV;
2157 else
2158 return -EINVAL;
2159 break;
2160 case SND_SOC_DAIFMT_IB_IF:
2161 if (dai->id == RT5682S_AIF1)
2162 tdm_ctrl |= RT5682S_TDM_S_BP_INV | RT5682S_TDM_S_LP_INV |
2163 RT5682S_TDM_M_BP_INV | RT5682S_TDM_M_LP_INV;
2164 else
2165 return -EINVAL;
2166 break;
2167 default:
2168 return -EINVAL;
2169 }
2170
2171 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2172 case SND_SOC_DAIFMT_I2S:
2173 break;
2174 case SND_SOC_DAIFMT_LEFT_J:
2175 reg_val |= RT5682S_I2S_DF_LEFT;
2176 tdm_ctrl |= RT5682S_TDM_DF_LEFT;
2177 break;
2178 case SND_SOC_DAIFMT_DSP_A:
2179 reg_val |= RT5682S_I2S_DF_PCM_A;
2180 tdm_ctrl |= RT5682S_TDM_DF_PCM_A;
2181 break;
2182 case SND_SOC_DAIFMT_DSP_B:
2183 reg_val |= RT5682S_I2S_DF_PCM_B;
2184 tdm_ctrl |= RT5682S_TDM_DF_PCM_B;
2185 break;
2186 default:
2187 return -EINVAL;
2188 }
2189
2190 switch (dai->id) {
2191 case RT5682S_AIF1:
2192 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2193 RT5682S_I2S_DF_MASK, reg_val);
2194 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2195 RT5682S_TDM_MS_MASK | RT5682S_TDM_S_BP_MASK |
2196 RT5682S_TDM_DF_MASK | RT5682S_TDM_M_BP_MASK |
2197 RT5682S_TDM_M_LP_MASK | RT5682S_TDM_S_LP_MASK,
2198 tdm_ctrl | rt5682s->master[dai->id]);
2199 break;
2200 case RT5682S_AIF2:
2201 if (rt5682s->master[dai->id] == 0)
2202 reg_val |= RT5682S_I2S2_MS_S;
2203 snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
2204 RT5682S_I2S2_MS_MASK | RT5682S_I2S_BP_MASK |
2205 RT5682S_I2S_DF_MASK, reg_val);
2206 break;
2207 default:
2208 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2209 return -EINVAL;
2210 }
2211 return 0;
2212 }
2213
rt5682s_set_component_sysclk(struct snd_soc_component * component,int clk_id,int source,unsigned int freq,int dir)2214 static int rt5682s_set_component_sysclk(struct snd_soc_component *component,
2215 int clk_id, int source, unsigned int freq, int dir)
2216 {
2217 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2218 unsigned int src = 0;
2219
2220 if (freq == rt5682s->sysclk && clk_id == rt5682s->sysclk_src)
2221 return 0;
2222
2223 switch (clk_id) {
2224 case RT5682S_SCLK_S_MCLK:
2225 src = RT5682S_CLK_SRC_MCLK;
2226 break;
2227 case RT5682S_SCLK_S_PLL1:
2228 src = RT5682S_CLK_SRC_PLL1;
2229 break;
2230 case RT5682S_SCLK_S_PLL2:
2231 src = RT5682S_CLK_SRC_PLL2;
2232 break;
2233 case RT5682S_SCLK_S_RCCLK:
2234 src = RT5682S_CLK_SRC_RCCLK;
2235 break;
2236 default:
2237 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2238 return -EINVAL;
2239 }
2240
2241 snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
2242 RT5682S_SCLK_SRC_MASK, src << RT5682S_SCLK_SRC_SFT);
2243 snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_1,
2244 RT5682S_I2S_M_CLK_SRC_MASK, src << RT5682S_I2S_M_CLK_SRC_SFT);
2245 snd_soc_component_update_bits(component, RT5682S_I2S2_M_CLK_CTRL_1,
2246 RT5682S_I2S2_M_CLK_SRC_MASK, src << RT5682S_I2S2_M_CLK_SRC_SFT);
2247
2248 rt5682s->sysclk = freq;
2249 rt5682s->sysclk_src = clk_id;
2250
2251 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2252 freq, clk_id);
2253
2254 return 0;
2255 }
2256
2257 static const struct pll_calc_map plla_table[] = {
2258 {2048000, 24576000, 0, 46, 2, true, false, false, false},
2259 {256000, 24576000, 0, 382, 2, true, false, false, false},
2260 {512000, 24576000, 0, 190, 2, true, false, false, false},
2261 {4096000, 24576000, 0, 22, 2, true, false, false, false},
2262 {1024000, 24576000, 0, 94, 2, true, false, false, false},
2263 {11289600, 22579200, 1, 22, 2, false, false, false, false},
2264 {1411200, 22579200, 0, 62, 2, true, false, false, false},
2265 {2822400, 22579200, 0, 30, 2, true, false, false, false},
2266 {12288000, 24576000, 1, 22, 2, false, false, false, false},
2267 {1536000, 24576000, 0, 62, 2, true, false, false, false},
2268 {3072000, 24576000, 0, 30, 2, true, false, false, false},
2269 {24576000, 49152000, 4, 22, 0, false, false, false, false},
2270 {3072000, 49152000, 0, 30, 0, true, false, false, false},
2271 {6144000, 49152000, 0, 30, 0, false, false, false, false},
2272 {49152000, 98304000, 10, 22, 0, false, true, false, false},
2273 {6144000, 98304000, 0, 30, 0, false, true, false, false},
2274 {12288000, 98304000, 1, 22, 0, false, true, false, false},
2275 {48000000, 3840000, 10, 22, 23, false, false, false, false},
2276 {24000000, 3840000, 4, 22, 23, false, false, false, false},
2277 {19200000, 3840000, 3, 23, 23, false, false, false, false},
2278 {38400000, 3840000, 8, 23, 23, false, false, false, false},
2279 };
2280
2281 static const struct pll_calc_map pllb_table[] = {
2282 {48000000, 24576000, 8, 6, 3, false, false, false, false},
2283 {48000000, 22579200, 23, 12, 3, false, false, false, true},
2284 {24000000, 24576000, 3, 6, 3, false, false, false, false},
2285 {24000000, 22579200, 23, 26, 3, false, false, false, true},
2286 {19200000, 24576000, 2, 6, 3, false, false, false, false},
2287 {19200000, 22579200, 3, 5, 3, false, false, false, true},
2288 {38400000, 24576000, 6, 6, 3, false, false, false, false},
2289 {38400000, 22579200, 8, 5, 3, false, false, false, true},
2290 {3840000, 49152000, 0, 6, 0, true, false, false, false},
2291 };
2292
find_pll_inter_combination(unsigned int f_in,unsigned int f_out,struct pll_calc_map * a,struct pll_calc_map * b)2293 static int find_pll_inter_combination(unsigned int f_in, unsigned int f_out,
2294 struct pll_calc_map *a, struct pll_calc_map *b)
2295 {
2296 int i, j;
2297
2298 /* Look at PLLA table */
2299 for (i = 0; i < ARRAY_SIZE(plla_table); i++) {
2300 if (plla_table[i].freq_in == f_in && plla_table[i].freq_out == f_out) {
2301 memcpy(a, plla_table + i, sizeof(*a));
2302 return USE_PLLA;
2303 }
2304 }
2305
2306 /* Look at PLLB table */
2307 for (i = 0; i < ARRAY_SIZE(pllb_table); i++) {
2308 if (pllb_table[i].freq_in == f_in && pllb_table[i].freq_out == f_out) {
2309 memcpy(b, pllb_table + i, sizeof(*b));
2310 return USE_PLLB;
2311 }
2312 }
2313
2314 /* Find a combination of PLLA & PLLB */
2315 for (i = ARRAY_SIZE(plla_table) - 1; i >= 0; i--) {
2316 if (plla_table[i].freq_in == f_in && plla_table[i].freq_out == 3840000) {
2317 for (j = ARRAY_SIZE(pllb_table) - 1; j >= 0; j--) {
2318 if (pllb_table[j].freq_in == 3840000 &&
2319 pllb_table[j].freq_out == f_out) {
2320 memcpy(a, plla_table + i, sizeof(*a));
2321 memcpy(b, pllb_table + j, sizeof(*b));
2322 return USE_PLLAB;
2323 }
2324 }
2325 }
2326 }
2327
2328 return -EINVAL;
2329 }
2330
rt5682s_set_component_pll(struct snd_soc_component * component,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)2331 static int rt5682s_set_component_pll(struct snd_soc_component *component,
2332 int pll_id, int source, unsigned int freq_in,
2333 unsigned int freq_out)
2334 {
2335 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2336 struct pll_calc_map a_map, b_map;
2337
2338 if (source == rt5682s->pll_src[pll_id] && freq_in == rt5682s->pll_in[pll_id] &&
2339 freq_out == rt5682s->pll_out[pll_id])
2340 return 0;
2341
2342 if (!freq_in || !freq_out) {
2343 dev_dbg(component->dev, "PLL disabled\n");
2344 rt5682s->pll_in[pll_id] = 0;
2345 rt5682s->pll_out[pll_id] = 0;
2346 snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
2347 RT5682S_SCLK_SRC_MASK, RT5682S_CLK_SRC_MCLK << RT5682S_SCLK_SRC_SFT);
2348 return 0;
2349 }
2350
2351 switch (source) {
2352 case RT5682S_PLL_S_MCLK:
2353 snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
2354 RT5682S_PLL_SRC_MASK, RT5682S_PLL_SRC_MCLK);
2355 break;
2356 case RT5682S_PLL_S_BCLK1:
2357 snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
2358 RT5682S_PLL_SRC_MASK, RT5682S_PLL_SRC_BCLK1);
2359 break;
2360 default:
2361 dev_err(component->dev, "Unknown PLL Source %d\n", source);
2362 return -EINVAL;
2363 }
2364
2365 rt5682s->pll_comb = find_pll_inter_combination(freq_in, freq_out,
2366 &a_map, &b_map);
2367
2368 if ((pll_id == RT5682S_PLL1 && rt5682s->pll_comb == USE_PLLA) ||
2369 (pll_id == RT5682S_PLL2 && (rt5682s->pll_comb == USE_PLLB ||
2370 rt5682s->pll_comb == USE_PLLAB))) {
2371 dev_dbg(component->dev,
2372 "Supported freq conversion for PLL%d:(%d->%d): %d\n",
2373 pll_id + 1, freq_in, freq_out, rt5682s->pll_comb);
2374 } else {
2375 dev_err(component->dev,
2376 "Unsupported freq conversion for PLL%d:(%d->%d): %d\n",
2377 pll_id + 1, freq_in, freq_out, rt5682s->pll_comb);
2378 return -EINVAL;
2379 }
2380
2381 if (rt5682s->pll_comb == USE_PLLA || rt5682s->pll_comb == USE_PLLAB) {
2382 dev_dbg(component->dev,
2383 "PLLA: fin=%d fout=%d m_bp=%d k_bp=%d m=%d n=%d k=%d\n",
2384 a_map.freq_in, a_map.freq_out, a_map.m_bp, a_map.k_bp,
2385 (a_map.m_bp ? 0 : a_map.m), a_map.n, (a_map.k_bp ? 0 : a_map.k));
2386 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_1,
2387 RT5682S_PLLA_N_MASK, a_map.n);
2388 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_2,
2389 RT5682S_PLLA_M_MASK | RT5682S_PLLA_K_MASK,
2390 a_map.m << RT5682S_PLLA_M_SFT | a_map.k);
2391 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_6,
2392 RT5682S_PLLA_M_BP_MASK | RT5682S_PLLA_K_BP_MASK,
2393 a_map.m_bp << RT5682S_PLLA_M_BP_SFT |
2394 a_map.k_bp << RT5682S_PLLA_K_BP_SFT);
2395 }
2396
2397 if (rt5682s->pll_comb == USE_PLLB || rt5682s->pll_comb == USE_PLLAB) {
2398 dev_dbg(component->dev,
2399 "PLLB: fin=%d fout=%d m_bp=%d k_bp=%d m=%d n=%d k=%d byp_ps=%d sel_ps=%d\n",
2400 b_map.freq_in, b_map.freq_out, b_map.m_bp, b_map.k_bp,
2401 (b_map.m_bp ? 0 : b_map.m), b_map.n, (b_map.k_bp ? 0 : b_map.k),
2402 b_map.byp_ps, b_map.sel_ps);
2403 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_3,
2404 RT5682S_PLLB_N_MASK, b_map.n);
2405 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_4,
2406 RT5682S_PLLB_M_MASK | RT5682S_PLLB_K_MASK,
2407 b_map.m << RT5682S_PLLB_M_SFT | b_map.k);
2408 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_6,
2409 RT5682S_PLLB_SEL_PS_MASK | RT5682S_PLLB_BYP_PS_MASK |
2410 RT5682S_PLLB_M_BP_MASK | RT5682S_PLLB_K_BP_MASK,
2411 b_map.sel_ps << RT5682S_PLLB_SEL_PS_SFT |
2412 b_map.byp_ps << RT5682S_PLLB_BYP_PS_SFT |
2413 b_map.m_bp << RT5682S_PLLB_M_BP_SFT |
2414 b_map.k_bp << RT5682S_PLLB_K_BP_SFT);
2415 }
2416
2417 if (rt5682s->pll_comb == USE_PLLB)
2418 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_7,
2419 RT5682S_PLLB_SRC_MASK, RT5682S_PLLB_SRC_DFIN);
2420
2421 rt5682s->pll_in[pll_id] = freq_in;
2422 rt5682s->pll_out[pll_id] = freq_out;
2423 rt5682s->pll_src[pll_id] = source;
2424
2425 return 0;
2426 }
2427
rt5682s_set_bclk1_ratio(struct snd_soc_dai * dai,unsigned int ratio)2428 static int rt5682s_set_bclk1_ratio(struct snd_soc_dai *dai,
2429 unsigned int ratio)
2430 {
2431 struct snd_soc_component *component = dai->component;
2432 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2433
2434 rt5682s->bclk[dai->id] = ratio;
2435
2436 switch (ratio) {
2437 case 256:
2438 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2439 RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_256);
2440 break;
2441 case 128:
2442 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2443 RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_128);
2444 break;
2445 case 64:
2446 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2447 RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_64);
2448 break;
2449 case 32:
2450 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2451 RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_32);
2452 break;
2453 default:
2454 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
2455 return -EINVAL;
2456 }
2457
2458 return 0;
2459 }
2460
rt5682s_set_bclk2_ratio(struct snd_soc_dai * dai,unsigned int ratio)2461 static int rt5682s_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2462 {
2463 struct snd_soc_component *component = dai->component;
2464 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2465
2466 rt5682s->bclk[dai->id] = ratio;
2467
2468 switch (ratio) {
2469 case 64:
2470 snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_2,
2471 RT5682S_I2S2_BCLK_MS2_MASK, RT5682S_I2S2_BCLK_MS2_64);
2472 break;
2473 case 32:
2474 snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_2,
2475 RT5682S_I2S2_BCLK_MS2_MASK, RT5682S_I2S2_BCLK_MS2_32);
2476 break;
2477 default:
2478 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
2479 return -EINVAL;
2480 }
2481
2482 return 0;
2483 }
2484
rt5682s_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)2485 static int rt5682s_set_bias_level(struct snd_soc_component *component,
2486 enum snd_soc_bias_level level)
2487 {
2488 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2489
2490 switch (level) {
2491 case SND_SOC_BIAS_PREPARE:
2492 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1,
2493 RT5682S_PWR_LDO, RT5682S_PWR_LDO);
2494 break;
2495 case SND_SOC_BIAS_STANDBY:
2496 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
2497 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1,
2498 RT5682S_DIG_GATE_CTRL, RT5682S_DIG_GATE_CTRL);
2499 break;
2500 case SND_SOC_BIAS_OFF:
2501 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1, RT5682S_PWR_LDO, 0);
2502 if (!rt5682s->wclk_enabled)
2503 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1,
2504 RT5682S_DIG_GATE_CTRL, 0);
2505 break;
2506 case SND_SOC_BIAS_ON:
2507 break;
2508 }
2509
2510 return 0;
2511 }
2512
2513 #ifdef CONFIG_COMMON_CLK
2514 #define CLK_PLL2_FIN 48000000
2515 #define CLK_48 48000
2516 #define CLK_44 44100
2517
rt5682s_clk_check(struct rt5682s_priv * rt5682s)2518 static bool rt5682s_clk_check(struct rt5682s_priv *rt5682s)
2519 {
2520 if (!rt5682s->master[RT5682S_AIF1]) {
2521 dev_dbg(rt5682s->component->dev, "dai clk fmt not set correctly\n");
2522 return false;
2523 }
2524 return true;
2525 }
2526
rt5682s_wclk_prepare(struct clk_hw * hw)2527 static int rt5682s_wclk_prepare(struct clk_hw *hw)
2528 {
2529 struct rt5682s_priv *rt5682s =
2530 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2531 struct snd_soc_component *component = rt5682s->component;
2532 int ref, reg;
2533
2534 if (!rt5682s_clk_check(rt5682s))
2535 return -EINVAL;
2536
2537 mutex_lock(&rt5682s->wclk_mutex);
2538
2539 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
2540 RT5682S_PWR_VREF2 | RT5682S_PWR_FV2 | RT5682S_PWR_MB,
2541 RT5682S_PWR_VREF2 | RT5682S_PWR_MB);
2542 usleep_range(15000, 20000);
2543 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
2544 RT5682S_PWR_FV2, RT5682S_PWR_FV2);
2545
2546 /* Set and power on I2S1 */
2547 snd_soc_component_update_bits(component, RT5682S_PWR_DIG_1,
2548 RT5682S_DIG_GATE_CTRL, RT5682S_DIG_GATE_CTRL);
2549 rt5682s_set_i2s(rt5682s, RT5682S_AIF1, 1);
2550
2551 /* Only need to power on PLLB due to the rate set restriction */
2552 reg = RT5682S_PLL_TRACK_2;
2553 ref = 256 * rt5682s->lrck[RT5682S_AIF1];
2554 rt5682s_set_filter_clk(rt5682s, reg, ref);
2555 rt5682s_set_pllb_power(rt5682s, 1);
2556
2557 rt5682s->wclk_enabled = 1;
2558
2559 mutex_unlock(&rt5682s->wclk_mutex);
2560
2561 return 0;
2562 }
2563
rt5682s_wclk_unprepare(struct clk_hw * hw)2564 static void rt5682s_wclk_unprepare(struct clk_hw *hw)
2565 {
2566 struct rt5682s_priv *rt5682s =
2567 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2568 struct snd_soc_component *component = rt5682s->component;
2569
2570 if (!rt5682s_clk_check(rt5682s))
2571 return;
2572
2573 mutex_lock(&rt5682s->wclk_mutex);
2574
2575 if (!rt5682s->jack_type)
2576 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
2577 RT5682S_PWR_VREF2 | RT5682S_PWR_FV2 | RT5682S_PWR_MB, 0);
2578
2579 /* Power down I2S1 */
2580 rt5682s_set_i2s(rt5682s, RT5682S_AIF1, 0);
2581 snd_soc_component_update_bits(component, RT5682S_PWR_DIG_1,
2582 RT5682S_DIG_GATE_CTRL, 0);
2583
2584 /* Power down PLLB */
2585 rt5682s_set_pllb_power(rt5682s, 0);
2586
2587 rt5682s->wclk_enabled = 0;
2588
2589 mutex_unlock(&rt5682s->wclk_mutex);
2590 }
2591
rt5682s_wclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2592 static unsigned long rt5682s_wclk_recalc_rate(struct clk_hw *hw,
2593 unsigned long parent_rate)
2594 {
2595 struct rt5682s_priv *rt5682s =
2596 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2597 struct snd_soc_component *component = rt5682s->component;
2598 const char * const clk_name = clk_hw_get_name(hw);
2599
2600 if (!rt5682s_clk_check(rt5682s))
2601 return 0;
2602 /*
2603 * Only accept to set wclk rate to 44.1k or 48kHz.
2604 */
2605 if (rt5682s->lrck[RT5682S_AIF1] != CLK_48 &&
2606 rt5682s->lrck[RT5682S_AIF1] != CLK_44) {
2607 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2608 __func__, clk_name, CLK_44, CLK_48);
2609 return 0;
2610 }
2611
2612 return rt5682s->lrck[RT5682S_AIF1];
2613 }
2614
rt5682s_wclk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)2615 static long rt5682s_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
2616 unsigned long *parent_rate)
2617 {
2618 struct rt5682s_priv *rt5682s =
2619 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2620 struct snd_soc_component *component = rt5682s->component;
2621 const char * const clk_name = clk_hw_get_name(hw);
2622
2623 if (!rt5682s_clk_check(rt5682s))
2624 return -EINVAL;
2625 /*
2626 * Only accept to set wclk rate to 44.1k or 48kHz.
2627 * It will force to 48kHz if not both.
2628 */
2629 if (rate != CLK_48 && rate != CLK_44) {
2630 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2631 __func__, clk_name, CLK_44, CLK_48);
2632 rate = CLK_48;
2633 }
2634
2635 return rate;
2636 }
2637
rt5682s_wclk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)2638 static int rt5682s_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
2639 unsigned long parent_rate)
2640 {
2641 struct rt5682s_priv *rt5682s =
2642 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2643 struct snd_soc_component *component = rt5682s->component;
2644 struct clk *parent_clk;
2645 const char * const clk_name = clk_hw_get_name(hw);
2646 unsigned int clk_pll2_fout;
2647
2648 if (!rt5682s_clk_check(rt5682s))
2649 return -EINVAL;
2650
2651 /*
2652 * Whether the wclk's parent clk (mclk) exists or not, please ensure
2653 * it is fixed or set to 48MHz before setting wclk rate. It's a
2654 * temporary limitation. Only accept 48MHz clk as the clk provider.
2655 *
2656 * It will set the codec anyway by assuming mclk is 48MHz.
2657 */
2658 parent_clk = clk_get_parent(hw->clk);
2659 if (!parent_clk)
2660 dev_warn(component->dev,
2661 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
2662 CLK_PLL2_FIN);
2663
2664 if (parent_rate != CLK_PLL2_FIN)
2665 dev_warn(component->dev, "clk %s only support %d Hz input\n",
2666 clk_name, CLK_PLL2_FIN);
2667
2668 /*
2669 * To achieve the rate conversion from 48MHz to 44.1k or 48kHz,
2670 * PLL2 is needed.
2671 */
2672 clk_pll2_fout = rate * 512;
2673 rt5682s_set_component_pll(component, RT5682S_PLL2, RT5682S_PLL_S_MCLK,
2674 CLK_PLL2_FIN, clk_pll2_fout);
2675
2676 rt5682s_set_component_sysclk(component, RT5682S_SCLK_S_PLL2, 0,
2677 clk_pll2_fout, SND_SOC_CLOCK_IN);
2678
2679 rt5682s->lrck[RT5682S_AIF1] = rate;
2680
2681 return 0;
2682 }
2683
rt5682s_bclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2684 static unsigned long rt5682s_bclk_recalc_rate(struct clk_hw *hw,
2685 unsigned long parent_rate)
2686 {
2687 struct rt5682s_priv *rt5682s =
2688 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]);
2689 struct snd_soc_component *component = rt5682s->component;
2690 unsigned int bclks_per_wclk;
2691
2692 bclks_per_wclk = snd_soc_component_read(component, RT5682S_TDM_TCON_CTRL_1);
2693
2694 switch (bclks_per_wclk & RT5682S_TDM_BCLK_MS1_MASK) {
2695 case RT5682S_TDM_BCLK_MS1_256:
2696 return parent_rate * 256;
2697 case RT5682S_TDM_BCLK_MS1_128:
2698 return parent_rate * 128;
2699 case RT5682S_TDM_BCLK_MS1_64:
2700 return parent_rate * 64;
2701 case RT5682S_TDM_BCLK_MS1_32:
2702 return parent_rate * 32;
2703 default:
2704 return 0;
2705 }
2706 }
2707
rt5682s_bclk_get_factor(unsigned long rate,unsigned long parent_rate)2708 static unsigned long rt5682s_bclk_get_factor(unsigned long rate,
2709 unsigned long parent_rate)
2710 {
2711 unsigned long factor;
2712
2713 factor = rate / parent_rate;
2714 if (factor < 64)
2715 return 32;
2716 else if (factor < 128)
2717 return 64;
2718 else if (factor < 256)
2719 return 128;
2720 else
2721 return 256;
2722 }
2723
rt5682s_bclk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)2724 static long rt5682s_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2725 unsigned long *parent_rate)
2726 {
2727 struct rt5682s_priv *rt5682s =
2728 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]);
2729 unsigned long factor;
2730
2731 if (!*parent_rate || !rt5682s_clk_check(rt5682s))
2732 return -EINVAL;
2733
2734 /*
2735 * BCLK rates are set as a multiplier of WCLK in HW.
2736 * We don't allow changing the parent WCLK. We just do
2737 * some rounding down based on the parent WCLK rate
2738 * and find the appropriate multiplier of BCLK to
2739 * get the rounded down BCLK value.
2740 */
2741 factor = rt5682s_bclk_get_factor(rate, *parent_rate);
2742
2743 return *parent_rate * factor;
2744 }
2745
rt5682s_bclk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)2746 static int rt5682s_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
2747 unsigned long parent_rate)
2748 {
2749 struct rt5682s_priv *rt5682s =
2750 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]);
2751 struct snd_soc_component *component = rt5682s->component;
2752 struct snd_soc_dai *dai;
2753 unsigned long factor;
2754
2755 if (!rt5682s_clk_check(rt5682s))
2756 return -EINVAL;
2757
2758 factor = rt5682s_bclk_get_factor(rate, parent_rate);
2759
2760 for_each_component_dais(component, dai)
2761 if (dai->id == RT5682S_AIF1)
2762 return rt5682s_set_bclk1_ratio(dai, factor);
2763
2764 dev_err(component->dev, "dai %d not found in component\n",
2765 RT5682S_AIF1);
2766 return -ENODEV;
2767 }
2768
2769 static const struct clk_ops rt5682s_dai_clk_ops[RT5682S_DAI_NUM_CLKS] = {
2770 [RT5682S_DAI_WCLK_IDX] = {
2771 .prepare = rt5682s_wclk_prepare,
2772 .unprepare = rt5682s_wclk_unprepare,
2773 .recalc_rate = rt5682s_wclk_recalc_rate,
2774 .round_rate = rt5682s_wclk_round_rate,
2775 .set_rate = rt5682s_wclk_set_rate,
2776 },
2777 [RT5682S_DAI_BCLK_IDX] = {
2778 .recalc_rate = rt5682s_bclk_recalc_rate,
2779 .round_rate = rt5682s_bclk_round_rate,
2780 .set_rate = rt5682s_bclk_set_rate,
2781 },
2782 };
2783
rt5682s_register_dai_clks(struct snd_soc_component * component)2784 static int rt5682s_register_dai_clks(struct snd_soc_component *component)
2785 {
2786 struct device *dev = component->dev;
2787 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2788 struct rt5682s_platform_data *pdata = &rt5682s->pdata;
2789 struct clk_hw *dai_clk_hw;
2790 int i, ret;
2791
2792 for (i = 0; i < RT5682S_DAI_NUM_CLKS; ++i) {
2793 struct clk_init_data init = { };
2794 struct clk_parent_data parent_data;
2795 const struct clk_hw *parent;
2796
2797 dai_clk_hw = &rt5682s->dai_clks_hw[i];
2798
2799 switch (i) {
2800 case RT5682S_DAI_WCLK_IDX:
2801 /* Make MCLK the parent of WCLK */
2802 if (rt5682s->mclk) {
2803 parent_data = (struct clk_parent_data){
2804 .fw_name = "mclk",
2805 };
2806 init.parent_data = &parent_data;
2807 init.num_parents = 1;
2808 }
2809 break;
2810 case RT5682S_DAI_BCLK_IDX:
2811 /* Make WCLK the parent of BCLK */
2812 parent = &rt5682s->dai_clks_hw[RT5682S_DAI_WCLK_IDX];
2813 init.parent_hws = &parent;
2814 init.num_parents = 1;
2815 break;
2816 default:
2817 dev_err(dev, "Invalid clock index\n");
2818 return -EINVAL;
2819 }
2820
2821 init.name = pdata->dai_clk_names[i];
2822 init.ops = &rt5682s_dai_clk_ops[i];
2823 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
2824 dai_clk_hw->init = &init;
2825
2826 ret = devm_clk_hw_register(dev, dai_clk_hw);
2827 if (ret) {
2828 dev_warn(dev, "Failed to register %s: %d\n", init.name, ret);
2829 return ret;
2830 }
2831
2832 if (dev->of_node) {
2833 devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, dai_clk_hw);
2834 } else {
2835 ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw,
2836 init.name, dev_name(dev));
2837 if (ret)
2838 return ret;
2839 }
2840 }
2841
2842 return 0;
2843 }
2844
rt5682s_dai_probe_clks(struct snd_soc_component * component)2845 static int rt5682s_dai_probe_clks(struct snd_soc_component *component)
2846 {
2847 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2848 int ret;
2849
2850 /* Check if MCLK provided */
2851 rt5682s->mclk = devm_clk_get(component->dev, "mclk");
2852 if (IS_ERR(rt5682s->mclk)) {
2853 if (PTR_ERR(rt5682s->mclk) != -ENOENT) {
2854 ret = PTR_ERR(rt5682s->mclk);
2855 return ret;
2856 }
2857 rt5682s->mclk = NULL;
2858 }
2859
2860 /* Register CCF DAI clock control */
2861 ret = rt5682s_register_dai_clks(component);
2862 if (ret)
2863 return ret;
2864
2865 /* Initial setup for CCF */
2866 rt5682s->lrck[RT5682S_AIF1] = CLK_48;
2867
2868 return 0;
2869 }
2870 #else
rt5682s_dai_probe_clks(struct snd_soc_component * component)2871 static inline int rt5682s_dai_probe_clks(struct snd_soc_component *component)
2872 {
2873 return 0;
2874 }
2875 #endif /* CONFIG_COMMON_CLK */
2876
rt5682s_probe(struct snd_soc_component * component)2877 static int rt5682s_probe(struct snd_soc_component *component)
2878 {
2879 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2880
2881 rt5682s->component = component;
2882
2883 return rt5682s_dai_probe_clks(component);
2884 }
2885
rt5682s_remove(struct snd_soc_component * component)2886 static void rt5682s_remove(struct snd_soc_component *component)
2887 {
2888 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2889
2890 rt5682s_reset(rt5682s);
2891 }
2892
2893 #ifdef CONFIG_PM
rt5682s_suspend(struct snd_soc_component * component)2894 static int rt5682s_suspend(struct snd_soc_component *component)
2895 {
2896 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2897
2898 if (rt5682s->irq)
2899 disable_irq(rt5682s->irq);
2900
2901 cancel_delayed_work_sync(&rt5682s->jack_detect_work);
2902 cancel_delayed_work_sync(&rt5682s->jd_check_work);
2903
2904 if (rt5682s->hs_jack)
2905 rt5682s->jack_type = rt5682s_headset_detect(component, 0);
2906
2907 regcache_cache_only(rt5682s->regmap, true);
2908 regcache_mark_dirty(rt5682s->regmap);
2909
2910 return 0;
2911 }
2912
rt5682s_resume(struct snd_soc_component * component)2913 static int rt5682s_resume(struct snd_soc_component *component)
2914 {
2915 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2916
2917 regcache_cache_only(rt5682s->regmap, false);
2918 regcache_sync(rt5682s->regmap);
2919
2920 if (rt5682s->hs_jack) {
2921 mod_delayed_work(system_power_efficient_wq,
2922 &rt5682s->jack_detect_work, msecs_to_jiffies(0));
2923 }
2924
2925 if (rt5682s->irq)
2926 enable_irq(rt5682s->irq);
2927
2928 return 0;
2929 }
2930 #else
2931 #define rt5682s_suspend NULL
2932 #define rt5682s_resume NULL
2933 #endif
2934
2935 static const struct snd_soc_dai_ops rt5682s_aif1_dai_ops = {
2936 .hw_params = rt5682s_hw_params,
2937 .set_fmt = rt5682s_set_dai_fmt,
2938 .set_tdm_slot = rt5682s_set_tdm_slot,
2939 .set_bclk_ratio = rt5682s_set_bclk1_ratio,
2940 };
2941
2942 static const struct snd_soc_dai_ops rt5682s_aif2_dai_ops = {
2943 .hw_params = rt5682s_hw_params,
2944 .set_fmt = rt5682s_set_dai_fmt,
2945 .set_bclk_ratio = rt5682s_set_bclk2_ratio,
2946 };
2947
2948 static const struct snd_soc_component_driver rt5682s_soc_component_dev = {
2949 .probe = rt5682s_probe,
2950 .remove = rt5682s_remove,
2951 .suspend = rt5682s_suspend,
2952 .resume = rt5682s_resume,
2953 .set_bias_level = rt5682s_set_bias_level,
2954 .controls = rt5682s_snd_controls,
2955 .num_controls = ARRAY_SIZE(rt5682s_snd_controls),
2956 .dapm_widgets = rt5682s_dapm_widgets,
2957 .num_dapm_widgets = ARRAY_SIZE(rt5682s_dapm_widgets),
2958 .dapm_routes = rt5682s_dapm_routes,
2959 .num_dapm_routes = ARRAY_SIZE(rt5682s_dapm_routes),
2960 .set_sysclk = rt5682s_set_component_sysclk,
2961 .set_pll = rt5682s_set_component_pll,
2962 .set_jack = rt5682s_set_jack_detect,
2963 .use_pmdown_time = 1,
2964 .endianness = 1,
2965 };
2966
rt5682s_parse_dt(struct rt5682s_priv * rt5682s,struct device * dev)2967 static int rt5682s_parse_dt(struct rt5682s_priv *rt5682s, struct device *dev)
2968 {
2969 device_property_read_u32(dev, "realtek,dmic1-data-pin",
2970 &rt5682s->pdata.dmic1_data_pin);
2971 device_property_read_u32(dev, "realtek,dmic1-clk-pin",
2972 &rt5682s->pdata.dmic1_clk_pin);
2973 device_property_read_u32(dev, "realtek,jd-src",
2974 &rt5682s->pdata.jd_src);
2975 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",
2976 &rt5682s->pdata.dmic_clk_rate);
2977 device_property_read_u32(dev, "realtek,dmic-delay-ms",
2978 &rt5682s->pdata.dmic_delay);
2979 device_property_read_u32(dev, "realtek,amic-delay-ms",
2980 &rt5682s->pdata.amic_delay);
2981
2982 rt5682s->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
2983 "realtek,ldo1-en-gpios", 0);
2984
2985 if (device_property_read_string_array(dev, "clock-output-names",
2986 rt5682s->pdata.dai_clk_names,
2987 RT5682S_DAI_NUM_CLKS) < 0)
2988 dev_warn(dev, "Using default DAI clk names: %s, %s\n",
2989 rt5682s->pdata.dai_clk_names[RT5682S_DAI_WCLK_IDX],
2990 rt5682s->pdata.dai_clk_names[RT5682S_DAI_BCLK_IDX]);
2991
2992 rt5682s->pdata.dmic_clk_driving_high = device_property_read_bool(dev,
2993 "realtek,dmic-clk-driving-high");
2994
2995 return 0;
2996 }
2997
rt5682s_calibrate(struct rt5682s_priv * rt5682s)2998 static void rt5682s_calibrate(struct rt5682s_priv *rt5682s)
2999 {
3000 unsigned int count, value;
3001
3002 mutex_lock(&rt5682s->calibrate_mutex);
3003
3004 regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0xaa80);
3005 usleep_range(15000, 20000);
3006 regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0xfa80);
3007 regmap_write(rt5682s->regmap, RT5682S_PWR_DIG_1, 0x01c0);
3008 regmap_write(rt5682s->regmap, RT5682S_MICBIAS_2, 0x0380);
3009 regmap_write(rt5682s->regmap, RT5682S_GLB_CLK, 0x8000);
3010 regmap_write(rt5682s->regmap, RT5682S_ADDA_CLK_1, 0x1001);
3011 regmap_write(rt5682s->regmap, RT5682S_CHOP_DAC_2, 0x3030);
3012 regmap_write(rt5682s->regmap, RT5682S_CHOP_ADC, 0xb000);
3013 regmap_write(rt5682s->regmap, RT5682S_STO1_ADC_MIXER, 0x686c);
3014 regmap_write(rt5682s->regmap, RT5682S_CAL_REC, 0x5151);
3015 regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_2, 0x0321);
3016 regmap_write(rt5682s->regmap, RT5682S_HP_LOGIC_CTRL_2, 0x0004);
3017 regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_1, 0x7c00);
3018 regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_1, 0xfc00);
3019
3020 for (count = 0; count < 60; count++) {
3021 regmap_read(rt5682s->regmap, RT5682S_HP_CALIB_ST_1, &value);
3022 if (!(value & 0x8000))
3023 break;
3024
3025 usleep_range(10000, 10005);
3026 }
3027
3028 if (count >= 60)
3029 dev_err(rt5682s->component->dev, "HP Calibration Failure\n");
3030
3031 /* restore settings */
3032 regmap_write(rt5682s->regmap, RT5682S_MICBIAS_2, 0x0180);
3033 regmap_write(rt5682s->regmap, RT5682S_CAL_REC, 0x5858);
3034 regmap_write(rt5682s->regmap, RT5682S_STO1_ADC_MIXER, 0xc0c4);
3035 regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_2, 0x0320);
3036 regmap_write(rt5682s->regmap, RT5682S_PWR_DIG_1, 0x00c0);
3037 regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0x0800);
3038 regmap_write(rt5682s->regmap, RT5682S_GLB_CLK, 0x0000);
3039
3040 mutex_unlock(&rt5682s->calibrate_mutex);
3041 }
3042
3043 static const struct regmap_config rt5682s_regmap = {
3044 .reg_bits = 16,
3045 .val_bits = 16,
3046 .max_register = RT5682S_MAX_REG,
3047 .volatile_reg = rt5682s_volatile_register,
3048 .readable_reg = rt5682s_readable_register,
3049 .cache_type = REGCACHE_RBTREE,
3050 .reg_defaults = rt5682s_reg,
3051 .num_reg_defaults = ARRAY_SIZE(rt5682s_reg),
3052 .use_single_read = true,
3053 .use_single_write = true,
3054 };
3055
3056 static struct snd_soc_dai_driver rt5682s_dai[] = {
3057 {
3058 .name = "rt5682s-aif1",
3059 .id = RT5682S_AIF1,
3060 .playback = {
3061 .stream_name = "AIF1 Playback",
3062 .channels_min = 1,
3063 .channels_max = 2,
3064 .rates = RT5682S_STEREO_RATES,
3065 .formats = RT5682S_FORMATS,
3066 },
3067 .capture = {
3068 .stream_name = "AIF1 Capture",
3069 .channels_min = 1,
3070 .channels_max = 2,
3071 .rates = RT5682S_STEREO_RATES,
3072 .formats = RT5682S_FORMATS,
3073 },
3074 .ops = &rt5682s_aif1_dai_ops,
3075 },
3076 {
3077 .name = "rt5682s-aif2",
3078 .id = RT5682S_AIF2,
3079 .capture = {
3080 .stream_name = "AIF2 Capture",
3081 .channels_min = 1,
3082 .channels_max = 2,
3083 .rates = RT5682S_STEREO_RATES,
3084 .formats = RT5682S_FORMATS,
3085 },
3086 .ops = &rt5682s_aif2_dai_ops,
3087 },
3088 };
3089
rt5682s_i2c_disable_regulators(void * data)3090 static void rt5682s_i2c_disable_regulators(void *data)
3091 {
3092 struct rt5682s_priv *rt5682s = data;
3093 struct device *dev = regmap_get_device(rt5682s->regmap);
3094 int ret;
3095
3096 ret = regulator_disable(rt5682s->supplies[RT5682S_SUPPLY_AVDD].consumer);
3097 if (ret)
3098 dev_err(dev, "Failed to disable supply AVDD: %d\n", ret);
3099
3100 ret = regulator_disable(rt5682s->supplies[RT5682S_SUPPLY_DBVDD].consumer);
3101 if (ret)
3102 dev_err(dev, "Failed to disable supply DBVDD: %d\n", ret);
3103
3104 ret = regulator_disable(rt5682s->supplies[RT5682S_SUPPLY_LDO1_IN].consumer);
3105 if (ret)
3106 dev_err(dev, "Failed to disable supply LDO1-IN: %d\n", ret);
3107
3108 usleep_range(1000, 1500);
3109
3110 ret = regulator_disable(rt5682s->supplies[RT5682S_SUPPLY_MICVDD].consumer);
3111 if (ret)
3112 dev_err(dev, "Failed to disable supply MICVDD: %d\n", ret);
3113 }
3114
rt5682s_i2c_probe(struct i2c_client * i2c)3115 static int rt5682s_i2c_probe(struct i2c_client *i2c)
3116 {
3117 struct rt5682s_platform_data *pdata = dev_get_platdata(&i2c->dev);
3118 struct rt5682s_priv *rt5682s;
3119 int i, ret;
3120 unsigned int val;
3121
3122 rt5682s = devm_kzalloc(&i2c->dev, sizeof(struct rt5682s_priv), GFP_KERNEL);
3123 if (!rt5682s)
3124 return -ENOMEM;
3125
3126 i2c_set_clientdata(i2c, rt5682s);
3127
3128 rt5682s->pdata = i2s_default_platform_data;
3129
3130 if (pdata)
3131 rt5682s->pdata = *pdata;
3132 else
3133 rt5682s_parse_dt(rt5682s, &i2c->dev);
3134
3135 rt5682s->regmap = devm_regmap_init_i2c(i2c, &rt5682s_regmap);
3136 if (IS_ERR(rt5682s->regmap)) {
3137 ret = PTR_ERR(rt5682s->regmap);
3138 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", ret);
3139 return ret;
3140 }
3141
3142 for (i = 0; i < ARRAY_SIZE(rt5682s->supplies); i++)
3143 rt5682s->supplies[i].supply = rt5682s_supply_names[i];
3144
3145 ret = devm_regulator_bulk_get(&i2c->dev,
3146 ARRAY_SIZE(rt5682s->supplies), rt5682s->supplies);
3147 if (ret) {
3148 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3149 return ret;
3150 }
3151
3152 ret = devm_add_action_or_reset(&i2c->dev, rt5682s_i2c_disable_regulators, rt5682s);
3153 if (ret)
3154 return ret;
3155
3156 ret = regulator_enable(rt5682s->supplies[RT5682S_SUPPLY_MICVDD].consumer);
3157 if (ret) {
3158 dev_err(&i2c->dev, "Failed to enable supply MICVDD: %d\n", ret);
3159 return ret;
3160 }
3161 usleep_range(1000, 1500);
3162
3163 ret = regulator_enable(rt5682s->supplies[RT5682S_SUPPLY_AVDD].consumer);
3164 if (ret) {
3165 dev_err(&i2c->dev, "Failed to enable supply AVDD: %d\n", ret);
3166 return ret;
3167 }
3168
3169 ret = regulator_enable(rt5682s->supplies[RT5682S_SUPPLY_DBVDD].consumer);
3170 if (ret) {
3171 dev_err(&i2c->dev, "Failed to enable supply DBVDD: %d\n", ret);
3172 return ret;
3173 }
3174
3175 ret = regulator_enable(rt5682s->supplies[RT5682S_SUPPLY_LDO1_IN].consumer);
3176 if (ret) {
3177 dev_err(&i2c->dev, "Failed to enable supply LDO1-IN: %d\n", ret);
3178 return ret;
3179 }
3180
3181 if (gpio_is_valid(rt5682s->pdata.ldo1_en)) {
3182 if (devm_gpio_request_one(&i2c->dev, rt5682s->pdata.ldo1_en,
3183 GPIOF_OUT_INIT_HIGH, "rt5682s"))
3184 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
3185 }
3186
3187 /* Sleep for 50 ms minimum */
3188 usleep_range(50000, 55000);
3189
3190 regmap_read(rt5682s->regmap, RT5682S_DEVICE_ID, &val);
3191 if (val != DEVICE_ID) {
3192 dev_err(&i2c->dev, "Device with ID register %x is not rt5682s\n", val);
3193 return -ENODEV;
3194 }
3195
3196 rt5682s_reset(rt5682s);
3197 rt5682s_apply_patch_list(rt5682s, &i2c->dev);
3198
3199 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_2,
3200 RT5682S_DLDO_I_LIMIT_MASK, RT5682S_DLDO_I_LIMIT_DIS);
3201 usleep_range(20000, 25000);
3202
3203 mutex_init(&rt5682s->calibrate_mutex);
3204 mutex_init(&rt5682s->sar_mutex);
3205 mutex_init(&rt5682s->wclk_mutex);
3206 rt5682s_calibrate(rt5682s);
3207
3208 regmap_update_bits(rt5682s->regmap, RT5682S_MICBIAS_2,
3209 RT5682S_PWR_CLK25M_MASK | RT5682S_PWR_CLK1M_MASK,
3210 RT5682S_PWR_CLK25M_PD | RT5682S_PWR_CLK1M_PU);
3211 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_1,
3212 RT5682S_PWR_BG, RT5682S_PWR_BG);
3213 regmap_update_bits(rt5682s->regmap, RT5682S_HP_LOGIC_CTRL_2,
3214 RT5682S_HP_SIG_SRC_MASK, RT5682S_HP_SIG_SRC_1BIT_CTL);
3215 regmap_update_bits(rt5682s->regmap, RT5682S_HP_CHARGE_PUMP_2,
3216 RT5682S_PM_HP_MASK, RT5682S_PM_HP_HV);
3217 regmap_update_bits(rt5682s->regmap, RT5682S_HP_AMP_DET_CTL_1,
3218 RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_M);
3219
3220 /* DMIC data pin */
3221 switch (rt5682s->pdata.dmic1_data_pin) {
3222 case RT5682S_DMIC1_DATA_NULL:
3223 break;
3224 case RT5682S_DMIC1_DATA_GPIO2: /* share with LRCK2 */
3225 regmap_update_bits(rt5682s->regmap, RT5682S_DMIC_CTRL_1,
3226 RT5682S_DMIC_1_DP_MASK, RT5682S_DMIC_1_DP_GPIO2);
3227 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3228 RT5682S_GP2_PIN_MASK, RT5682S_GP2_PIN_DMIC_SDA);
3229 break;
3230 case RT5682S_DMIC1_DATA_GPIO5: /* share with DACDAT1 */
3231 regmap_update_bits(rt5682s->regmap, RT5682S_DMIC_CTRL_1,
3232 RT5682S_DMIC_1_DP_MASK, RT5682S_DMIC_1_DP_GPIO5);
3233 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3234 RT5682S_GP5_PIN_MASK, RT5682S_GP5_PIN_DMIC_SDA);
3235 break;
3236 default:
3237 dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n");
3238 break;
3239 }
3240
3241 /* DMIC clk pin */
3242 switch (rt5682s->pdata.dmic1_clk_pin) {
3243 case RT5682S_DMIC1_CLK_NULL:
3244 break;
3245 case RT5682S_DMIC1_CLK_GPIO1: /* share with IRQ */
3246 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3247 RT5682S_GP1_PIN_MASK, RT5682S_GP1_PIN_DMIC_CLK);
3248 break;
3249 case RT5682S_DMIC1_CLK_GPIO3: /* share with BCLK2 */
3250 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3251 RT5682S_GP3_PIN_MASK, RT5682S_GP3_PIN_DMIC_CLK);
3252 if (rt5682s->pdata.dmic_clk_driving_high)
3253 regmap_update_bits(rt5682s->regmap, RT5682S_PAD_DRIVING_CTRL,
3254 RT5682S_PAD_DRV_GP3_MASK, RT5682S_PAD_DRV_GP3_HIGH);
3255 break;
3256 default:
3257 dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n");
3258 break;
3259 }
3260
3261 INIT_DELAYED_WORK(&rt5682s->jack_detect_work, rt5682s_jack_detect_handler);
3262 INIT_DELAYED_WORK(&rt5682s->jd_check_work, rt5682s_jd_check_handler);
3263
3264 if (i2c->irq) {
3265 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, rt5682s_irq,
3266 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
3267 "rt5682s", rt5682s);
3268 if (!ret)
3269 rt5682s->irq = i2c->irq;
3270 else
3271 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
3272 }
3273
3274 return devm_snd_soc_register_component(&i2c->dev, &rt5682s_soc_component_dev,
3275 rt5682s_dai, ARRAY_SIZE(rt5682s_dai));
3276 }
3277
rt5682s_i2c_shutdown(struct i2c_client * client)3278 static void rt5682s_i2c_shutdown(struct i2c_client *client)
3279 {
3280 struct rt5682s_priv *rt5682s = i2c_get_clientdata(client);
3281
3282 disable_irq(client->irq);
3283 cancel_delayed_work_sync(&rt5682s->jack_detect_work);
3284 cancel_delayed_work_sync(&rt5682s->jd_check_work);
3285
3286 rt5682s_reset(rt5682s);
3287 }
3288
rt5682s_i2c_remove(struct i2c_client * client)3289 static void rt5682s_i2c_remove(struct i2c_client *client)
3290 {
3291 rt5682s_i2c_shutdown(client);
3292 }
3293
3294 static const struct of_device_id rt5682s_of_match[] = {
3295 {.compatible = "realtek,rt5682s"},
3296 {},
3297 };
3298 MODULE_DEVICE_TABLE(of, rt5682s_of_match);
3299
3300 static const struct acpi_device_id rt5682s_acpi_match[] = {
3301 {"RTL5682", 0,},
3302 {},
3303 };
3304 MODULE_DEVICE_TABLE(acpi, rt5682s_acpi_match);
3305
3306 static const struct i2c_device_id rt5682s_i2c_id[] = {
3307 {"rt5682s", 0},
3308 {}
3309 };
3310 MODULE_DEVICE_TABLE(i2c, rt5682s_i2c_id);
3311
3312 static struct i2c_driver rt5682s_i2c_driver = {
3313 .driver = {
3314 .name = "rt5682s",
3315 .of_match_table = rt5682s_of_match,
3316 .acpi_match_table = rt5682s_acpi_match,
3317 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
3318 },
3319 .probe_new = rt5682s_i2c_probe,
3320 .remove = rt5682s_i2c_remove,
3321 .shutdown = rt5682s_i2c_shutdown,
3322 .id_table = rt5682s_i2c_id,
3323 };
3324 module_i2c_driver(rt5682s_i2c_driver);
3325
3326 MODULE_DESCRIPTION("ASoC RT5682I-VS driver");
3327 MODULE_AUTHOR("Derek Fang <derek.fang@realtek.com>");
3328 MODULE_LICENSE("GPL v2");
3329