1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2017 Intel Corporation. All rights reserved.
7 *
8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 */
10
11 #ifndef __SOF_INTEL_HDA_H
12 #define __SOF_INTEL_HDA_H
13
14 #include <linux/soundwire/sdw.h>
15 #include <linux/soundwire/sdw_intel.h>
16 #include <sound/compress_driver.h>
17 #include <sound/hda_codec.h>
18 #include <sound/hdaudio_ext.h>
19 #include "../sof-client-probes.h"
20 #include "../sof-audio.h"
21 #include "shim.h"
22
23 /* PCI registers */
24 #define PCI_TCSEL 0x44
25 #define PCI_PGCTL PCI_TCSEL
26 #define PCI_CGCTL 0x48
27
28 /* PCI_PGCTL bits */
29 #define PCI_PGCTL_ADSPPGD BIT(2)
30 #define PCI_PGCTL_LSRMD_MASK BIT(4)
31
32 /* PCI_CGCTL bits */
33 #define PCI_CGCTL_MISCBDCGE_MASK BIT(6)
34 #define PCI_CGCTL_ADSPDCGE BIT(1)
35
36 /* Legacy HDA registers and bits used - widths are variable */
37 #define SOF_HDA_GCAP 0x0
38 #define SOF_HDA_GCTL 0x8
39 /* accept unsol. response enable */
40 #define SOF_HDA_GCTL_UNSOL BIT(8)
41 #define SOF_HDA_LLCH 0x14
42 #define SOF_HDA_INTCTL 0x20
43 #define SOF_HDA_INTSTS 0x24
44 #define SOF_HDA_WAKESTS 0x0E
45 #define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1)
46 #define SOF_HDA_RIRBSTS 0x5d
47
48 /* SOF_HDA_GCTL register bist */
49 #define SOF_HDA_GCTL_RESET BIT(0)
50
51 /* SOF_HDA_INCTL regs */
52 #define SOF_HDA_INT_GLOBAL_EN BIT(31)
53 #define SOF_HDA_INT_CTRL_EN BIT(30)
54 #define SOF_HDA_INT_ALL_STREAM 0xff
55
56 /* SOF_HDA_INTSTS regs */
57 #define SOF_HDA_INTSTS_GIS BIT(31)
58
59 #define SOF_HDA_MAX_CAPS 10
60 #define SOF_HDA_CAP_ID_OFF 16
61 #define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\
62 SOF_HDA_CAP_ID_OFF)
63 #define SOF_HDA_CAP_NEXT_MASK 0xFFFF
64
65 #define SOF_HDA_GTS_CAP_ID 0x1
66 #define SOF_HDA_ML_CAP_ID 0x2
67
68 #define SOF_HDA_PP_CAP_ID 0x3
69 #define SOF_HDA_REG_PP_PPCH 0x10
70 #define SOF_HDA_REG_PP_PPCTL 0x04
71 #define SOF_HDA_REG_PP_PPSTS 0x08
72 #define SOF_HDA_PPCTL_PIE BIT(31)
73 #define SOF_HDA_PPCTL_GPROCEN BIT(30)
74
75 /*Vendor Specific Registers*/
76 #define SOF_HDA_VS_D0I3C 0x104A
77
78 /* D0I3C Register fields */
79 #define SOF_HDA_VS_D0I3C_CIP BIT(0) /* Command-In-Progress */
80 #define SOF_HDA_VS_D0I3C_I3 BIT(2) /* D0i3 enable bit */
81
82 /* DPIB entry size: 8 Bytes = 2 DWords */
83 #define SOF_HDA_DPIB_ENTRY_SIZE 0x8
84
85 #define SOF_HDA_SPIB_CAP_ID 0x4
86 #define SOF_HDA_DRSM_CAP_ID 0x5
87
88 #define SOF_HDA_SPIB_BASE 0x08
89 #define SOF_HDA_SPIB_INTERVAL 0x08
90 #define SOF_HDA_SPIB_SPIB 0x00
91 #define SOF_HDA_SPIB_MAXFIFO 0x04
92
93 #define SOF_HDA_PPHC_BASE 0x10
94 #define SOF_HDA_PPHC_INTERVAL 0x10
95
96 #define SOF_HDA_PPLC_BASE 0x10
97 #define SOF_HDA_PPLC_MULTI 0x10
98 #define SOF_HDA_PPLC_INTERVAL 0x10
99
100 #define SOF_HDA_DRSM_BASE 0x08
101 #define SOF_HDA_DRSM_INTERVAL 0x08
102
103 /* Descriptor error interrupt */
104 #define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10
105
106 /* FIFO error interrupt */
107 #define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08
108
109 /* Buffer completion interrupt */
110 #define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04
111
112 #define SOF_HDA_CL_DMA_SD_INT_MASK \
113 (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \
114 SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \
115 SOF_HDA_CL_DMA_SD_INT_COMPLETE)
116 #define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */
117
118 /* Intel HD Audio Code Loader DMA Registers */
119 #define SOF_HDA_ADSP_LOADER_BASE 0x80
120 #define SOF_HDA_ADSP_DPLBASE 0x70
121 #define SOF_HDA_ADSP_DPUBASE 0x74
122 #define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01
123
124 /* Stream Registers */
125 #define SOF_HDA_ADSP_REG_SD_CTL 0x00
126 #define SOF_HDA_ADSP_REG_SD_STS 0x03
127 #define SOF_HDA_ADSP_REG_SD_LPIB 0x04
128 #define SOF_HDA_ADSP_REG_SD_CBL 0x08
129 #define SOF_HDA_ADSP_REG_SD_LVI 0x0C
130 #define SOF_HDA_ADSP_REG_SD_FIFOW 0x0E
131 #define SOF_HDA_ADSP_REG_SD_FIFOSIZE 0x10
132 #define SOF_HDA_ADSP_REG_SD_FORMAT 0x12
133 #define SOF_HDA_ADSP_REG_SD_FIFOL 0x14
134 #define SOF_HDA_ADSP_REG_SD_BDLPL 0x18
135 #define SOF_HDA_ADSP_REG_SD_BDLPU 0x1C
136 #define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20
137
138 /* CL: Software Position Based FIFO Capability Registers */
139 #define SOF_DSP_REG_CL_SPBFIFO \
140 (SOF_HDA_ADSP_LOADER_BASE + 0x20)
141 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0
142 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4
143 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8
144 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc
145
146 /* Stream Number */
147 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20
148 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \
149 GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\
150 SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT)
151
152 #define HDA_DSP_HDA_BAR 0
153 #define HDA_DSP_PP_BAR 1
154 #define HDA_DSP_SPIB_BAR 2
155 #define HDA_DSP_DRSM_BAR 3
156 #define HDA_DSP_BAR 4
157
158 #define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000)
159
160 #define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0)
161
162 #define HDA_DSP_PANIC_OFFSET(x) \
163 (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET)
164
165 /* SRAM window 0 FW "registers" */
166 #define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0)
167 #define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4)
168 /* FW and ROM share offset 4 */
169 #define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4)
170 #define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8)
171 #define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc)
172
173 #define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000
174
175 #define HDA_DSP_STREAM_RESET_TIMEOUT 300
176 /*
177 * Timeout in us, for setting the stream RUN bit, during
178 * start/stop the stream. The timeout expires if new RUN bit
179 * value cannot be read back within the specified time.
180 */
181 #define HDA_DSP_STREAM_RUN_TIMEOUT 300
182
183 #define HDA_DSP_SPIB_ENABLE 1
184 #define HDA_DSP_SPIB_DISABLE 0
185
186 #define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE)
187
188 #define HDA_DSP_STACK_DUMP_SIZE 32
189
190 /* ROM/FW status register */
191 #define FSR_STATE_MASK GENMASK(23, 0)
192 #define FSR_WAIT_STATE_MASK GENMASK(27, 24)
193 #define FSR_MODULE_MASK GENMASK(30, 28)
194 #define FSR_HALTED BIT(31)
195 #define FSR_TO_STATE_CODE(x) ((x) & FSR_STATE_MASK)
196 #define FSR_TO_WAIT_STATE_CODE(x) (((x) & FSR_WAIT_STATE_MASK) >> 24)
197 #define FSR_TO_MODULE_CODE(x) (((x) & FSR_MODULE_MASK) >> 28)
198
199 /* Wait states */
200 #define FSR_WAIT_FOR_IPC_BUSY 0x1
201 #define FSR_WAIT_FOR_IPC_DONE 0x2
202 #define FSR_WAIT_FOR_CACHE_INVALIDATION 0x3
203 #define FSR_WAIT_FOR_LP_SRAM_OFF 0x4
204 #define FSR_WAIT_FOR_DMA_BUFFER_FULL 0x5
205 #define FSR_WAIT_FOR_CSE_CSR 0x6
206
207 /* Module codes */
208 #define FSR_MOD_ROM 0x0
209 #define FSR_MOD_ROM_BYP 0x1
210 #define FSR_MOD_BASE_FW 0x2
211 #define FSR_MOD_LP_BOOT 0x3
212 #define FSR_MOD_BRNGUP 0x4
213 #define FSR_MOD_ROM_EXT 0x5
214
215 /* State codes (module dependent) */
216 /* Module independent states */
217 #define FSR_STATE_INIT 0x0
218 #define FSR_STATE_INIT_DONE 0x1
219 #define FSR_STATE_FW_ENTERED 0x5
220
221 /* ROM states */
222 #define FSR_STATE_ROM_INIT FSR_STATE_INIT
223 #define FSR_STATE_ROM_INIT_DONE FSR_STATE_INIT_DONE
224 #define FSR_STATE_ROM_CSE_MANIFEST_LOADED 0x2
225 #define FSR_STATE_ROM_FW_MANIFEST_LOADED 0x3
226 #define FSR_STATE_ROM_FW_FW_LOADED 0x4
227 #define FSR_STATE_ROM_FW_ENTERED FSR_STATE_FW_ENTERED
228 #define FSR_STATE_ROM_VERIFY_FEATURE_MASK 0x6
229 #define FSR_STATE_ROM_GET_LOAD_OFFSET 0x7
230 #define FSR_STATE_ROM_FETCH_ROM_EXT 0x8
231 #define FSR_STATE_ROM_FETCH_ROM_EXT_DONE 0x9
232 #define FSR_STATE_ROM_BASEFW_ENTERED 0xf /* SKL */
233
234 /* (ROM) CSE states */
235 #define FSR_STATE_ROM_CSE_IMR_REQUEST 0x10
236 #define FSR_STATE_ROM_CSE_IMR_GRANTED 0x11
237 #define FSR_STATE_ROM_CSE_VALIDATE_IMAGE_REQUEST 0x12
238 #define FSR_STATE_ROM_CSE_IMAGE_VALIDATED 0x13
239
240 #define FSR_STATE_ROM_CSE_IPC_IFACE_INIT 0x20
241 #define FSR_STATE_ROM_CSE_IPC_RESET_PHASE_1 0x21
242 #define FSR_STATE_ROM_CSE_IPC_OPERATIONAL_ENTRY 0x22
243 #define FSR_STATE_ROM_CSE_IPC_OPERATIONAL 0x23
244 #define FSR_STATE_ROM_CSE_IPC_DOWN 0x24
245
246 /* BRINGUP (or BRNGUP) states */
247 #define FSR_STATE_BRINGUP_INIT FSR_STATE_INIT
248 #define FSR_STATE_BRINGUP_INIT_DONE FSR_STATE_INIT_DONE
249 #define FSR_STATE_BRINGUP_HPSRAM_LOAD 0x2
250 #define FSR_STATE_BRINGUP_UNPACK_START 0X3
251 #define FSR_STATE_BRINGUP_IMR_RESTORE 0x4
252 #define FSR_STATE_BRINGUP_FW_ENTERED FSR_STATE_FW_ENTERED
253
254 /* ROM status/error values */
255 #define HDA_DSP_ROM_CSE_ERROR 40
256 #define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41
257 #define HDA_DSP_ROM_IMR_TO_SMALL 42
258 #define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43
259 #define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44
260 #define HDA_DSP_ROM_IPC_FATAL_ERROR 45
261 #define HDA_DSP_ROM_L2_CACHE_ERROR 46
262 #define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47
263 #define HDA_DSP_ROM_API_PTR_INVALID 50
264 #define HDA_DSP_ROM_BASEFW_INCOMPAT 51
265 #define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000
266 #define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000
267 #define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000
268 #define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000
269 #define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000
270 #define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55
271
272 #define HDA_DSP_ROM_IPC_CONTROL 0x01000000
273 #define HDA_DSP_ROM_IPC_PURGE_FW 0x00004000
274
275 /* various timeout values */
276 #define HDA_DSP_PU_TIMEOUT 50
277 #define HDA_DSP_PD_TIMEOUT 50
278 #define HDA_DSP_RESET_TIMEOUT_US 50000
279 #define HDA_DSP_BASEFW_TIMEOUT_US 3000000
280 #define HDA_DSP_INIT_TIMEOUT_US 500000
281 #define HDA_DSP_CTRL_RESET_TIMEOUT 100
282 #define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */
283 #define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */
284 #define HDA_DSP_REG_POLL_RETRY_COUNT 50
285
286 #define HDA_DSP_ADSPIC_IPC BIT(0)
287 #define HDA_DSP_ADSPIS_IPC BIT(0)
288
289 /* Intel HD Audio General DSP Registers */
290 #define HDA_DSP_GEN_BASE 0x0
291 #define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04)
292 #define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08)
293 #define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C)
294 #define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10)
295 #define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14)
296
297 #define HDA_DSP_REG_ADSPIC2_SNDW BIT(5)
298 #define HDA_DSP_REG_ADSPIS2_SNDW BIT(5)
299
300 /* Intel HD Audio Inter-Processor Communication Registers */
301 #define HDA_DSP_IPC_BASE 0x40
302 #define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00)
303 #define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04)
304 #define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08)
305 #define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C)
306 #define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10)
307
308 /* Intel Vendor Specific Registers */
309 #define HDA_VS_INTEL_EM2 0x1030
310 #define HDA_VS_INTEL_EM2_L1SEN BIT(13)
311 #define HDA_VS_INTEL_LTRP 0x1048
312 #define HDA_VS_INTEL_LTRP_GB_MASK 0x3F
313
314 /* HIPCI */
315 #define HDA_DSP_REG_HIPCI_BUSY BIT(31)
316 #define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF
317
318 /* HIPCIE */
319 #define HDA_DSP_REG_HIPCIE_DONE BIT(30)
320 #define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF
321
322 /* HIPCCTL */
323 #define HDA_DSP_REG_HIPCCTL_DONE BIT(1)
324 #define HDA_DSP_REG_HIPCCTL_BUSY BIT(0)
325
326 /* HIPCT */
327 #define HDA_DSP_REG_HIPCT_BUSY BIT(31)
328 #define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF
329
330 /* HIPCTE */
331 #define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF
332
333 #define HDA_DSP_ADSPIC_CL_DMA BIT(1)
334 #define HDA_DSP_ADSPIS_CL_DMA BIT(1)
335
336 /* Delay before scheduling D0i3 entry */
337 #define BXT_D0I3_DELAY 5000
338
339 #define FW_CL_STREAM_NUMBER 0x1
340 #define HDA_FW_BOOT_ATTEMPTS 3
341
342 /* ADSPCS - Audio DSP Control & Status */
343
344 /*
345 * Core Reset - asserted high
346 * CRST Mask for a given core mask pattern, cm
347 */
348 #define HDA_DSP_ADSPCS_CRST_SHIFT 0
349 #define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT)
350
351 /*
352 * Core run/stall - when set to '1' core is stalled
353 * CSTALL Mask for a given core mask pattern, cm
354 */
355 #define HDA_DSP_ADSPCS_CSTALL_SHIFT 8
356 #define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT)
357
358 /*
359 * Set Power Active - when set to '1' turn cores on
360 * SPA Mask for a given core mask pattern, cm
361 */
362 #define HDA_DSP_ADSPCS_SPA_SHIFT 16
363 #define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT)
364
365 /*
366 * Current Power Active - power status of cores, set by hardware
367 * CPA Mask for a given core mask pattern, cm
368 */
369 #define HDA_DSP_ADSPCS_CPA_SHIFT 24
370 #define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT)
371
372 /*
373 * Mask for a given number of cores
374 * nc = number of supported cores
375 */
376 #define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0)
377
378 /* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/
379 #define CNL_DSP_IPC_BASE 0xc0
380 #define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00)
381 #define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04)
382 #define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08)
383 #define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10)
384 #define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14)
385 #define CNL_DSP_REG_HIPCIDD (CNL_DSP_IPC_BASE + 0x18)
386 #define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28)
387
388 /* HIPCI */
389 #define CNL_DSP_REG_HIPCIDR_BUSY BIT(31)
390 #define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF
391
392 /* HIPCIE */
393 #define CNL_DSP_REG_HIPCIDA_DONE BIT(31)
394 #define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF
395
396 /* HIPCCTL */
397 #define CNL_DSP_REG_HIPCCTL_DONE BIT(1)
398 #define CNL_DSP_REG_HIPCCTL_BUSY BIT(0)
399
400 /* HIPCT */
401 #define CNL_DSP_REG_HIPCTDR_BUSY BIT(31)
402 #define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF
403
404 /* HIPCTDA */
405 #define CNL_DSP_REG_HIPCTDA_DONE BIT(31)
406 #define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF
407
408 /* HIPCTDD */
409 #define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF
410
411 /* BDL */
412 #define HDA_DSP_BDL_SIZE 4096
413 #define HDA_DSP_MAX_BDL_ENTRIES \
414 (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl))
415
416 /* Number of DAIs */
417 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
418 #define SOF_SKL_NUM_DAIS 15
419 #else
420 #define SOF_SKL_NUM_DAIS 8
421 #endif
422
423 /* Intel HD Audio SRAM Window 0*/
424 #define HDA_DSP_SRAM_REG_ROM_STATUS_SKL 0x8000
425 #define HDA_ADSP_SRAM0_BASE_SKL 0x8000
426
427 /* Firmware status window */
428 #define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL
429 #define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4)
430
431 /* Host Device Memory Space */
432 #define APL_SSP_BASE_OFFSET 0x2000
433 #define CNL_SSP_BASE_OFFSET 0x10000
434
435 /* Host Device Memory Size of a Single SSP */
436 #define SSP_DEV_MEM_SIZE 0x1000
437
438 /* SSP Count of the Platform */
439 #define APL_SSP_COUNT 6
440 #define CNL_SSP_COUNT 3
441 #define ICL_SSP_COUNT 6
442 #define TGL_SSP_COUNT 3
443 #define MTL_SSP_COUNT 3
444
445 /* SSP Registers */
446 #define SSP_SSC1_OFFSET 0x4
447 #define SSP_SET_SCLK_CONSUMER BIT(25)
448 #define SSP_SET_SFRM_CONSUMER BIT(24)
449 #define SSP_SET_CBP_CFP (SSP_SET_SCLK_CONSUMER | SSP_SET_SFRM_CONSUMER)
450
451 #define HDA_IDISP_ADDR 2
452 #define HDA_IDISP_CODEC(x) ((x) & BIT(HDA_IDISP_ADDR))
453
454 struct sof_intel_dsp_bdl {
455 __le32 addr_l;
456 __le32 addr_h;
457 __le32 size;
458 __le32 ioc;
459 } __attribute((packed));
460
461 #define SOF_HDA_PLAYBACK_STREAMS 16
462 #define SOF_HDA_CAPTURE_STREAMS 16
463 #define SOF_HDA_PLAYBACK 0
464 #define SOF_HDA_CAPTURE 1
465
466 /* stream flags */
467 #define SOF_HDA_STREAM_DMI_L1_COMPATIBLE 1
468
469 /*
470 * Time in ms for opportunistic D0I3 entry delay.
471 * This has been deliberately chosen to be long to avoid race conditions.
472 * Could be optimized in future.
473 */
474 #define SOF_HDA_D0I3_WORK_DELAY_MS 5000
475
476 /* HDA DSP D0 substate */
477 enum sof_hda_D0_substate {
478 SOF_HDA_DSP_PM_D0I0, /* default D0 substate */
479 SOF_HDA_DSP_PM_D0I3, /* low power D0 substate */
480 };
481
482 /* represents DSP HDA controller frontend - i.e. host facing control */
483 struct sof_intel_hda_dev {
484 bool imrboot_supported;
485 bool skip_imr_boot;
486 bool booted_from_imr;
487
488 int boot_iteration;
489
490 struct hda_bus hbus;
491
492 /* hw config */
493 const struct sof_intel_dsp_desc *desc;
494
495 /* trace */
496 struct hdac_ext_stream *dtrace_stream;
497
498 /* if position update IPC needed */
499 u32 no_ipc_position;
500
501 /* the maximum number of streams (playback + capture) supported */
502 u32 stream_max;
503
504 /* PM related */
505 bool l1_support_changed;/* during suspend, is L1SEN changed or not */
506
507 /* DMIC device */
508 struct platform_device *dmic_dev;
509
510 /* delayed work to enter D0I3 opportunistically */
511 struct delayed_work d0i3_work;
512
513 /* ACPI information stored between scan and probe steps */
514 struct sdw_intel_acpi_info info;
515
516 /* sdw context allocated by SoundWire driver */
517 struct sdw_intel_ctx *sdw;
518
519 /* FW clock config, 0:HPRO, 1:LPRO */
520 bool clk_config_lpro;
521
522 wait_queue_head_t waitq;
523 bool code_loading;
524
525 /* Intel NHLT information */
526 struct nhlt_acpi_table *nhlt;
527
528 /*
529 * Pointing to the IPC message if immediate sending was not possible
530 * because the downlink communication channel was BUSY at the time.
531 * The message will be re-tried when the channel becomes free (the ACK
532 * is received from the DSP for the previous message)
533 */
534 struct snd_sof_ipc_msg *delayed_ipc_tx_msg;
535 };
536
sof_to_bus(struct snd_sof_dev * s)537 static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s)
538 {
539 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
540
541 return &hda->hbus.core;
542 }
543
sof_to_hbus(struct snd_sof_dev * s)544 static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s)
545 {
546 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
547
548 return &hda->hbus;
549 }
550
551 struct sof_intel_hda_stream {
552 struct snd_sof_dev *sdev;
553 struct hdac_ext_stream hext_stream;
554 struct sof_intel_stream sof_intel_stream;
555 int host_reserved; /* reserve host DMA channel */
556 u32 flags;
557 };
558
559 #define hstream_to_sof_hda_stream(hstream) \
560 container_of(hstream, struct sof_intel_hda_stream, hext_stream)
561
562 #define bus_to_sof_hda(bus) \
563 container_of(bus, struct sof_intel_hda_dev, hbus.core)
564
565 #define SOF_STREAM_SD_OFFSET(s) \
566 (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \
567 + SOF_HDA_ADSP_LOADER_BASE)
568
569 #define SOF_STREAM_SD_OFFSET_CRST 0x1
570
571 /*
572 * DSP Core services.
573 */
574 int hda_dsp_probe(struct snd_sof_dev *sdev);
575 int hda_dsp_remove(struct snd_sof_dev *sdev);
576 int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask);
577 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask);
578 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask);
579 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
580 unsigned int core_mask);
581 int hda_power_down_dsp(struct snd_sof_dev *sdev);
582 int hda_dsp_core_get(struct snd_sof_dev *sdev, int core);
583 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev);
584 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev);
585 bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, unsigned int core_mask);
586
587 int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
588 const struct sof_dsp_power_state *target_state);
589
590 int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state);
591 int hda_dsp_resume(struct snd_sof_dev *sdev);
592 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev);
593 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev);
594 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev);
595 int hda_dsp_shutdown_dma_flush(struct snd_sof_dev *sdev);
596 int hda_dsp_shutdown(struct snd_sof_dev *sdev);
597 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev);
598 void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
599 void hda_ipc_dump(struct snd_sof_dev *sdev);
600 void hda_ipc_irq_dump(struct snd_sof_dev *sdev);
601 void hda_dsp_d0i3_work(struct work_struct *work);
602 int hda_dsp_disable_interrupts(struct snd_sof_dev *sdev);
603
604 /*
605 * DSP PCM Operations.
606 */
607 u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate);
608 u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits);
609 int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
610 struct snd_pcm_substream *substream);
611 int hda_dsp_pcm_close(struct snd_sof_dev *sdev,
612 struct snd_pcm_substream *substream);
613 int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev,
614 struct snd_pcm_substream *substream,
615 struct snd_pcm_hw_params *params,
616 struct snd_sof_platform_stream_params *platform_params);
617 int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev,
618 struct snd_pcm_substream *substream);
619 int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev,
620 struct snd_pcm_substream *substream, int cmd);
621 snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev,
622 struct snd_pcm_substream *substream);
623 int hda_dsp_pcm_ack(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream);
624
625 /*
626 * DSP Stream Operations.
627 */
628
629 int hda_dsp_stream_init(struct snd_sof_dev *sdev);
630 void hda_dsp_stream_free(struct snd_sof_dev *sdev);
631 int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
632 struct hdac_ext_stream *hext_stream,
633 struct snd_dma_buffer *dmab,
634 struct snd_pcm_hw_params *params);
635 int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev,
636 struct hdac_ext_stream *hext_stream,
637 struct snd_dma_buffer *dmab,
638 struct snd_pcm_hw_params *params);
639 int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
640 struct hdac_ext_stream *hext_stream, int cmd);
641 irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context);
642 int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
643 struct snd_dma_buffer *dmab,
644 struct hdac_stream *hstream);
645 bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev);
646 bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev);
647
648 snd_pcm_uframes_t hda_dsp_stream_get_position(struct hdac_stream *hstream,
649 int direction, bool can_sleep);
650
651 struct hdac_ext_stream *
652 hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags);
653 int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag);
654 int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
655 struct hdac_ext_stream *hext_stream,
656 int enable, u32 size);
657
658 int hda_ipc_msg_data(struct snd_sof_dev *sdev,
659 struct snd_sof_pcm_stream *sps,
660 void *p, size_t sz);
661 int hda_set_stream_data_offset(struct snd_sof_dev *sdev,
662 struct snd_sof_pcm_stream *sps,
663 size_t posn_offset);
664
665 /*
666 * DSP IPC Operations.
667 */
668 int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev,
669 struct snd_sof_ipc_msg *msg);
670 void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev);
671 int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
672 int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
673
674 irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context);
675 int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir);
676
677 /*
678 * DSP Code loader.
679 */
680 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev);
681 int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev);
682 int hda_cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream);
683 struct hdac_ext_stream *hda_cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format,
684 unsigned int size, struct snd_dma_buffer *dmab,
685 int direction);
686 int hda_cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
687 struct hdac_ext_stream *hext_stream);
688 int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot);
689 #define HDA_CL_STREAM_FORMAT 0x40
690
691 /* pre and post fw run ops */
692 int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev);
693 int hda_dsp_post_fw_run(struct snd_sof_dev *sdev);
694
695 /* parse platform specific ext manifest ops */
696 int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev,
697 const struct sof_ext_man_elem_header *hdr);
698
699 /*
700 * HDA Controller Operations.
701 */
702 int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev);
703 void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable);
704 void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable);
705 int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset);
706 void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable);
707 int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable);
708 int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev);
709 void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev);
710 /*
711 * HDA bus operations.
712 */
713 void sof_hda_bus_init(struct snd_sof_dev *sdev, struct device *dev);
714 void sof_hda_bus_exit(struct snd_sof_dev *sdev);
715
716 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC)
717 /*
718 * HDA Codec operations.
719 */
720 void hda_codec_probe_bus(struct snd_sof_dev *sdev);
721 void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable);
722 void hda_codec_jack_check(struct snd_sof_dev *sdev);
723 void hda_codec_check_for_state_change(struct snd_sof_dev *sdev);
724 void hda_codec_init_cmd_io(struct snd_sof_dev *sdev);
725 void hda_codec_resume_cmd_io(struct snd_sof_dev *sdev);
726 void hda_codec_stop_cmd_io(struct snd_sof_dev *sdev);
727 void hda_codec_suspend_cmd_io(struct snd_sof_dev *sdev);
728 void hda_codec_detect_mask(struct snd_sof_dev *sdev);
729 void hda_codec_rirb_status_clear(struct snd_sof_dev *sdev);
730 bool hda_codec_check_rirb_status(struct snd_sof_dev *sdev);
731 void hda_codec_set_codec_wakeup(struct snd_sof_dev *sdev, bool status);
732 void hda_codec_device_remove(struct snd_sof_dev *sdev);
733
734 #else
735
hda_codec_probe_bus(struct snd_sof_dev * sdev)736 static inline void hda_codec_probe_bus(struct snd_sof_dev *sdev) { }
hda_codec_jack_wake_enable(struct snd_sof_dev * sdev,bool enable)737 static inline void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable) { }
hda_codec_jack_check(struct snd_sof_dev * sdev)738 static inline void hda_codec_jack_check(struct snd_sof_dev *sdev) { }
hda_codec_check_for_state_change(struct snd_sof_dev * sdev)739 static inline void hda_codec_check_for_state_change(struct snd_sof_dev *sdev) { }
hda_codec_init_cmd_io(struct snd_sof_dev * sdev)740 static inline void hda_codec_init_cmd_io(struct snd_sof_dev *sdev) { }
hda_codec_resume_cmd_io(struct snd_sof_dev * sdev)741 static inline void hda_codec_resume_cmd_io(struct snd_sof_dev *sdev) { }
hda_codec_stop_cmd_io(struct snd_sof_dev * sdev)742 static inline void hda_codec_stop_cmd_io(struct snd_sof_dev *sdev) { }
hda_codec_suspend_cmd_io(struct snd_sof_dev * sdev)743 static inline void hda_codec_suspend_cmd_io(struct snd_sof_dev *sdev) { }
hda_codec_detect_mask(struct snd_sof_dev * sdev)744 static inline void hda_codec_detect_mask(struct snd_sof_dev *sdev) { }
hda_codec_rirb_status_clear(struct snd_sof_dev * sdev)745 static inline void hda_codec_rirb_status_clear(struct snd_sof_dev *sdev) { }
hda_codec_check_rirb_status(struct snd_sof_dev * sdev)746 static inline bool hda_codec_check_rirb_status(struct snd_sof_dev *sdev) { return false; }
hda_codec_set_codec_wakeup(struct snd_sof_dev * sdev,bool status)747 static inline void hda_codec_set_codec_wakeup(struct snd_sof_dev *sdev, bool status) { }
hda_codec_device_remove(struct snd_sof_dev * sdev)748 static inline void hda_codec_device_remove(struct snd_sof_dev *sdev) { }
749
750 #endif /* CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC */
751
752 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) && IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
753
754 void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable);
755 int hda_codec_i915_init(struct snd_sof_dev *sdev);
756 int hda_codec_i915_exit(struct snd_sof_dev *sdev);
757
758 #else
759
hda_codec_i915_display_power(struct snd_sof_dev * sdev,bool enable)760 static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable) { }
hda_codec_i915_init(struct snd_sof_dev * sdev)761 static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; }
hda_codec_i915_exit(struct snd_sof_dev * sdev)762 static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; }
763
764 #endif
765
766 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
767
768 void hda_bus_ml_get_capabilities(struct hdac_bus *bus);
769 void hda_bus_ml_free(struct hdac_bus *bus);
770 void hda_bus_ml_put_all(struct hdac_bus *bus);
771 void hda_bus_ml_reset_losidv(struct hdac_bus *bus);
772 int hda_bus_ml_resume(struct hdac_bus *bus);
773 int hda_bus_ml_suspend(struct hdac_bus *bus);
774
775 #else
776
hda_bus_ml_get_capabilities(struct hdac_bus * bus)777 static inline void hda_bus_ml_get_capabilities(struct hdac_bus *bus) { }
hda_bus_ml_free(struct hdac_bus * bus)778 static inline void hda_bus_ml_free(struct hdac_bus *bus) { }
hda_bus_ml_put_all(struct hdac_bus * bus)779 static inline void hda_bus_ml_put_all(struct hdac_bus *bus) { }
hda_bus_ml_reset_losidv(struct hdac_bus * bus)780 static inline void hda_bus_ml_reset_losidv(struct hdac_bus *bus) { }
hda_bus_ml_resume(struct hdac_bus * bus)781 static inline int hda_bus_ml_resume(struct hdac_bus *bus) { return 0; }
hda_bus_ml_suspend(struct hdac_bus * bus)782 static inline int hda_bus_ml_suspend(struct hdac_bus *bus) { return 0; }
783
784 #endif /* CONFIG_SND_SOC_SOF_HDA */
785
786 /*
787 * Trace Control.
788 */
789 int hda_dsp_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
790 struct sof_ipc_dma_trace_params_ext *dtrace_params);
791 int hda_dsp_trace_release(struct snd_sof_dev *sdev);
792 int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
793
794 /*
795 * SoundWire support
796 */
797 #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
798
799 int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev);
800 int hda_sdw_startup(struct snd_sof_dev *sdev);
801 void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable);
802 void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable);
803 void hda_sdw_process_wakeen(struct snd_sof_dev *sdev);
804 bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev);
805
806 #else
807
hda_sdw_check_lcount_common(struct snd_sof_dev * sdev)808 static inline int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev)
809 {
810 return 0;
811 }
812
hda_sdw_startup(struct snd_sof_dev * sdev)813 static inline int hda_sdw_startup(struct snd_sof_dev *sdev)
814 {
815 return 0;
816 }
817
hda_common_enable_sdw_irq(struct snd_sof_dev * sdev,bool enable)818 static inline void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable)
819 {
820 }
821
hda_sdw_int_enable(struct snd_sof_dev * sdev,bool enable)822 static inline void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable)
823 {
824 }
825
hda_sdw_process_wakeen(struct snd_sof_dev * sdev)826 static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev)
827 {
828 }
829
hda_common_check_sdw_irq(struct snd_sof_dev * sdev)830 static inline bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev)
831 {
832 return false;
833 }
834
835 #endif
836
837 /* common dai driver */
838 extern struct snd_soc_dai_driver skl_dai[];
839 int hda_dsp_dais_suspend(struct snd_sof_dev *sdev);
840
841 /*
842 * Platform Specific HW abstraction Ops.
843 */
844 extern struct snd_sof_dsp_ops sof_hda_common_ops;
845
846 extern struct snd_sof_dsp_ops sof_skl_ops;
847 int sof_skl_ops_init(struct snd_sof_dev *sdev);
848 extern struct snd_sof_dsp_ops sof_apl_ops;
849 int sof_apl_ops_init(struct snd_sof_dev *sdev);
850 extern struct snd_sof_dsp_ops sof_cnl_ops;
851 int sof_cnl_ops_init(struct snd_sof_dev *sdev);
852 extern struct snd_sof_dsp_ops sof_tgl_ops;
853 int sof_tgl_ops_init(struct snd_sof_dev *sdev);
854 extern struct snd_sof_dsp_ops sof_icl_ops;
855 int sof_icl_ops_init(struct snd_sof_dev *sdev);
856 extern struct snd_sof_dsp_ops sof_mtl_ops;
857 int sof_mtl_ops_init(struct snd_sof_dev *sdev);
858
859 extern const struct sof_intel_dsp_desc skl_chip_info;
860 extern const struct sof_intel_dsp_desc apl_chip_info;
861 extern const struct sof_intel_dsp_desc cnl_chip_info;
862 extern const struct sof_intel_dsp_desc icl_chip_info;
863 extern const struct sof_intel_dsp_desc tgl_chip_info;
864 extern const struct sof_intel_dsp_desc tglh_chip_info;
865 extern const struct sof_intel_dsp_desc ehl_chip_info;
866 extern const struct sof_intel_dsp_desc jsl_chip_info;
867 extern const struct sof_intel_dsp_desc adls_chip_info;
868 extern const struct sof_intel_dsp_desc mtl_chip_info;
869
870 /* Probes support */
871 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
872 int hda_probes_register(struct snd_sof_dev *sdev);
873 void hda_probes_unregister(struct snd_sof_dev *sdev);
874 #else
hda_probes_register(struct snd_sof_dev * sdev)875 static inline int hda_probes_register(struct snd_sof_dev *sdev)
876 {
877 return 0;
878 }
879
hda_probes_unregister(struct snd_sof_dev * sdev)880 static inline void hda_probes_unregister(struct snd_sof_dev *sdev)
881 {
882 }
883 #endif /* CONFIG_SND_SOC_SOF_HDA_PROBES */
884
885 /* SOF client registration for HDA platforms */
886 int hda_register_clients(struct snd_sof_dev *sdev);
887 void hda_unregister_clients(struct snd_sof_dev *sdev);
888
889 /* machine driver select */
890 struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev);
891 void hda_set_mach_params(struct snd_soc_acpi_mach *mach,
892 struct snd_sof_dev *sdev);
893
894 /* PCI driver selection and probe */
895 int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id);
896
897 struct snd_sof_dai;
898 struct sof_ipc_dai_config;
899 int hda_ctrl_dai_widget_setup(struct snd_soc_dapm_widget *w, unsigned int quirk_flags,
900 struct snd_sof_dai_config_data *data);
901 int hda_ctrl_dai_widget_free(struct snd_soc_dapm_widget *w, unsigned int quirk_flags,
902 struct snd_sof_dai_config_data *data);
903
904 #define SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY (0) /* previous implementation */
905 #define SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS (1) /* recommended if VC0 only */
906 #define SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE (2) /* recommended with VC0 or VC1 */
907
908 extern int sof_hda_position_quirk;
909
910 void hda_set_dai_drv_ops(struct snd_sof_dev *sdev, struct snd_sof_dsp_ops *ops);
911 void hda_ops_free(struct snd_sof_dev *sdev);
912
913 /* SKL/KBL */
914 int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev);
915 int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask);
916
917 /* IPC4 */
918 irqreturn_t cnl_ipc4_irq_thread(int irq, void *context);
919 int cnl_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg);
920 irqreturn_t hda_dsp_ipc4_irq_thread(int irq, void *context);
921 bool hda_ipc4_tx_is_busy(struct snd_sof_dev *sdev);
922 void hda_dsp_ipc4_schedule_d0i3_work(struct sof_intel_hda_dev *hdev,
923 struct snd_sof_ipc_msg *msg);
924 int hda_dsp_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg);
925 void hda_ipc4_dump(struct snd_sof_dev *sdev);
926 extern struct sdw_intel_ops sdw_callback;
927
928 struct sof_ipc4_fw_library;
929 int hda_dsp_ipc4_load_library(struct snd_sof_dev *sdev,
930 struct sof_ipc4_fw_library *fw_lib, bool reload);
931 #endif
932