1 /*
2 * Copyright (c) 2014 Travis Geiselbrecht
3 *
4 * Use of this source code is governed by a MIT-style
5 * license that can be found in the LICENSE file or at
6 * https://opensource.org/licenses/MIT
7 */
8 #include <dev/cache/pl310.h>
9
10 #include <assert.h>
11 #include <lk/trace.h>
12 #include <lk/err.h>
13 #include <lk/reg.h>
14 #include <stdlib.h>
15 #include <arch.h>
16 #include <arch/arm/mmu.h>
17 #include <dev/cache/pl310_config.h>
18 #include <lk/init.h>
19
20 /* configuration of the pl310 comes from #define space */
21 #ifndef PL310_BASE
22 #error need to define PL310_BASE
23 #endif
24
25 #define LOCAL_TRACE 0
26
27 #define PL310_REG(reg) (*REG32(PL310_BASE + (reg)))
28
29 /* registers */
30 #define REG0_CACHE_ID 0x000
31 #define REG0_CACHE_TYPE 0x004
32 #define REG1_CONTROL 0x100
33 #define REG1_AUX_CONTROL 0x104
34 #define REG1_TAG_RAM_CONTROL 0x108
35 #define REG1_DATA_RAM_CONTROL 0x10c
36 #define REG2_EV_COUNTER_CTRL 0x200
37 #define REG2_EV_COUNTER1_CFG 0x204
38 #define REG2_EV_COUNTER0_CFG 0x208
39 #define REG2_EV_COUNTER1 0x20c
40 #define REG2_EV_COUNTER0 0x210
41 #define REG2_INT_MASK 0x214
42 #define REG2_INT_MASK_STATUS 0x218
43 #define REG2_INT_RAW_STATUS 0x21c
44 #define REG2_INT_CLEAR 0x220
45 #define REG7_CACHE_SYNC 0x730
46 #define REG7_INV_PA 0x770
47 #define REG7_INV_WAY 0x77c
48 #define REG7_CLEAN_PA 0x7b0
49 #define REG7_CLEAN_INDEX 0x7b8
50 #define REG7_CLEAN_WAY 0x7bc
51 #define REG7_CLEAN_INV_PA 0x7f0
52 #define REG7_CLEAN_INV_INDEX 0x7f8
53 #define REG7_CLEAN_INV_WAY 0x7fc
54 #define REG9_D_LOCKDOWN0 0x900
55 #define REG9_I_LOCKDOWN0 0x904
56 #define REG9_D_LOCKDOWN1 0x908
57 #define REG9_I_LOCKDOWN1 0x90c
58 #define REG9_D_LOCKDOWN2 0x910
59 #define REG9_I_LOCKDOWN2 0x914
60 #define REG9_D_LOCKDOWN3 0x918
61 #define REG9_I_LOCKDOWN3 0x91c
62 #define REG9_D_LOCKDOWN4 0x920
63 #define REG9_I_LOCKDOWN4 0x924
64 #define REG9_D_LOCKDOWN5 0x928
65 #define REG9_I_LOCKDOWN5 0x92c
66 #define REG9_D_LOCKDOWN6 0x930
67 #define REG9_I_LOCKDOWN6 0x934
68 #define REG9_D_LOCKDOWN7 0x938
69 #define REG9_I_LOCKDOWN7 0x93c
70 #define REG9_LOCK_LINE_EN 0x950
71 #define REG9_UNLOCK_WAY 0x954
72 #define REG12_ADDR_FILTERING_START 0xc00
73 #define REG12_ADDR_FILTERING_END 0xc04
74 #define REG15_DEBUG_CTRL 0xf40
75 #define REG15_PREFETCH_CTRL 0xf60
76 #define REG15_POWER_CTRL 0xf80
77
pl310_enabled(void)78 static inline bool pl310_enabled(void) {
79 return !!(PL310_REG(REG1_CONTROL) & 1);
80 }
81
pl310_init(uint level)82 static void pl310_init(uint level) {
83 /* make sure it's already disabled */
84 DEBUG_ASSERT(!pl310_enabled());
85
86 /* set tag and data ram latency */
87 PL310_REG(REG1_TAG_RAM_CONTROL) = PL310_TAG_RAM_LATENCY;
88 PL310_REG(REG1_DATA_RAM_CONTROL) = PL310_DATA_RAM_LATENCY;
89
90 /* configure */
91 /* early BRESP enable, instruction/data prefetch, exclusive cache, full line of zero */
92 PL310_REG(REG1_AUX_CONTROL) |= (1<<30)|(1<<29)|(1<<28)|(1<<12)|(1<<0);
93
94 /* flush all the ways */
95 PL310_REG(REG7_INV_WAY) = 0xffff;
96 }
97
98 /* run just before arch_early_init so the L2 is ready to go when
99 * the arch code starts up the caching system.
100 */
101 LK_INIT_HOOK(pl310_init, pl310_init, LK_INIT_LEVEL_ARCH_EARLY - 1);
102
pl310_set_enable(bool enable)103 status_t pl310_set_enable(bool enable) {
104 LTRACEF("enable %d\n", enable);
105
106 if (enable) {
107 if ((PL310_REG(REG1_CONTROL) & 1) == 0) {
108 /* if disabled */
109 pl310_invalidate();
110 PL310_REG(REG1_CONTROL) = 1;
111 }
112 } else {
113 if ((PL310_REG(REG1_CONTROL) & 1) == 1) {
114 /* if enabled */
115 pl310_flush_invalidate();
116 PL310_REG(REG1_CONTROL) = 0;
117 /* this seems to not always latch on the first try */
118 while (PL310_REG(REG1_CONTROL) & 1) {
119 PL310_REG(REG1_CONTROL) = 0;
120 }
121 }
122 }
123
124 return NO_ERROR;
125 }
126
pl310_invalidate(void)127 void pl310_invalidate(void) {
128 if (unlikely(!pl310_enabled()))
129 return;
130 PL310_REG(REG7_INV_WAY) = 0xffff;
131 while (PL310_REG(REG7_INV_WAY) != 0)
132 ;
133 }
134
pl310_flush_invalidate(void)135 void pl310_flush_invalidate(void) {
136 if (unlikely(!pl310_enabled()))
137 return;
138 PL310_REG(REG7_CLEAN_INV_WAY) = 0xffff;
139 while (PL310_REG(REG7_CLEAN_INV_WAY) != 0)
140 ;
141 }
142
pl310_sync_range(void)143 void pl310_sync_range(void) {
144 if (unlikely(!pl310_enabled()))
145 return;
146
147 PL310_REG(REG7_CACHE_SYNC) = 1;
148 }
149
150 #define PL310_LOOP_BODY(reg) \
151 if (unlikely(!pl310_enabled())) \
152 return; \
153 \
154 addr_t pa = 0; \
155 uint32_t last_pa_page = 1; \
156 addr_t last_va = start + len; \
157 start &= ~(CACHE_LINE - 1); \
158 while (start < last_va) { \
159 if (unlikely(pa / PAGE_SIZE != last_pa_page)) { \
160 /* get the physical address */ \
161 if (unlikely(arm_vtop(start, &pa))) \
162 return; \
163 last_pa_page = pa / PAGE_SIZE; \
164 } \
165 PL310_REG(reg) = pa; \
166 \
167 pa += CACHE_LINE; \
168 start += CACHE_LINE; \
169 } \
170 \
171 PL310_REG(REG7_CACHE_SYNC) = 1;
172
pl310_clean_range(addr_t start,size_t len)173 void pl310_clean_range(addr_t start, size_t len) {
174 LTRACEF("start 0x%lx, len %zd\n", start, len);
175 PL310_LOOP_BODY(REG7_CLEAN_PA);
176 }
177
pl310_clean_invalidate_range(addr_t start,size_t len)178 void pl310_clean_invalidate_range(addr_t start, size_t len) {
179 LTRACEF("start 0x%lx, len %zd\n", start, len);
180 PL310_LOOP_BODY(REG7_CLEAN_INV_PA);
181 }
182
pl310_invalidate_range(addr_t start,size_t len)183 void pl310_invalidate_range(addr_t start, size_t len) {
184 LTRACEF("start 0x%lx, len %zd\n", start, len);
185 PL310_LOOP_BODY(REG7_INV_PA);
186 }
187
pl310_pin_cache_range(addr_t start,size_t len)188 void pl310_pin_cache_range(addr_t start, size_t len) {
189 len = ROUNDUP(len, CACHE_LINE);
190
191 arch_disable_ints();
192
193 arch_clean_invalidate_cache_range(start, len);
194
195 PL310_REG(REG9_LOCK_LINE_EN) = 1;
196 DSB;
197
198 while (len > 0) {
199 asm volatile("pld [%0]" :: "r"(start) : "memory");
200 start += CACHE_LINE;
201 len -= CACHE_LINE;
202 }
203
204 DSB;
205 PL310_REG(REG9_LOCK_LINE_EN) = 0;
206
207 arch_enable_ints();
208 }
209
210