1 /*
2 * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef NRF_I2S_H__
33 #define NRF_I2S_H__
34
35 #include <nrfx.h>
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 #ifndef NRF_I2S0
42 #define NRF_I2S0 NRF_I2S
43 #endif
44
45 /**
46 * @defgroup nrf_i2s_hal I2S HAL
47 * @{
48 * @ingroup nrf_i2s
49 * @brief Hardware access layer for managing the Inter-IC Sound (I2S) peripheral.
50 */
51
52 #if defined(I2S_CONFIG_CLKCONFIG_CLKSRC_Msk) || defined(__NRFX_DOXYGEN__)
53 /** @brief Symbol indicating whether clock source configuration is available. */
54 #define NRF_I2S_HAS_CLKCONFIG 1
55 #else
56 #define NRF_I2S_HAS_CLKCONFIG 0
57 #endif
58
59 /**
60 * @brief This value can be provided as a parameter for the @ref nrf_i2s_pins_set
61 * function call to specify that the given I2S signal (SDOUT, SDIN, or MCK)
62 * shall not be connected to a physical pin.
63 */
64 #define NRF_I2S_PIN_NOT_CONNECTED 0xFFFFFFFF
65
66
67 /** @brief I2S tasks. */
68 typedef enum
69 {
70 NRF_I2S_TASK_START = offsetof(NRF_I2S_Type, TASKS_START), ///< Starts continuous I2S transfer. Also starts the MCK generator if this is enabled.
71 NRF_I2S_TASK_STOP = offsetof(NRF_I2S_Type, TASKS_STOP) ///< Stops I2S transfer. Also stops the MCK generator.
72 } nrf_i2s_task_t;
73
74 /** @brief I2S events. */
75 typedef enum
76 {
77 NRF_I2S_EVENT_RXPTRUPD = offsetof(NRF_I2S_Type, EVENTS_RXPTRUPD), ///< The RXD.PTR register has been copied to internal double buffers.
78 NRF_I2S_EVENT_TXPTRUPD = offsetof(NRF_I2S_Type, EVENTS_TXPTRUPD), ///< The TXD.PTR register has been copied to internal double buffers.
79 NRF_I2S_EVENT_STOPPED = offsetof(NRF_I2S_Type, EVENTS_STOPPED), ///< I2S transfer stopped.
80 #if defined(I2S_INTENSET_FRAMESTART_Msk) || defined(__NRFX_DOXYGEN_)
81 NRF_I2S_EVENT_FRAMESTART = offsetof(NRF_I2S_Type, EVENTS_FRAMESTART) ///< Frame start event, generated on the active edge of LRCK.
82 #endif
83 } nrf_i2s_event_t;
84
85 /** @brief I2S interrupts. */
86 typedef enum
87 {
88 NRF_I2S_INT_RXPTRUPD_MASK = I2S_INTENSET_RXPTRUPD_Msk, ///< Interrupt on RXPTRUPD event.
89 NRF_I2S_INT_TXPTRUPD_MASK = I2S_INTENSET_TXPTRUPD_Msk, ///< Interrupt on TXPTRUPD event.
90 NRF_I2S_INT_STOPPED_MASK = I2S_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
91 #if defined(I2S_INTENSET_FRAMESTART_Msk) || defined(__NRFX_DOXYGEN_)
92 NRF_I2S_INT_FRAMESTART_MASK = I2S_INTENCLR_FRAMESTART_Msk ///< Interrupt on FRAMESTART event.
93 #endif
94 } nrf_i2s_int_mask_t;
95
96 /** @brief I2S modes of operation. */
97 typedef enum
98 {
99 NRF_I2S_MODE_MASTER = I2S_CONFIG_MODE_MODE_Master, ///< Master mode.
100 NRF_I2S_MODE_SLAVE = I2S_CONFIG_MODE_MODE_Slave ///< Slave mode.
101 } nrf_i2s_mode_t;
102
103 /** @brief I2S master clock generator settings. */
104 typedef enum
105 {
106 NRF_I2S_MCK_DISABLED = 0, ///< MCK disabled.
107 #if defined(I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2) || defined(__NRFX_DOXYGEN__)
108 // [conversion to 'int' needed to prevent compilers from complaining
109 // that the provided value (0x80000000UL) is out of range of "int"]
110 NRF_I2S_MCK_32MDIV2 = (int)I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2, ///< 32 MHz / 2 = 16.0 MHz.
111 #endif
112 #if defined(I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3) || defined(__NRFX_DOXYGEN__)
113 NRF_I2S_MCK_32MDIV3 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3, ///< 32 MHz / 3 = 10.6666667 MHz.
114 #endif
115 #if defined(I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4) || defined(__NRFX_DOXYGEN__)
116 NRF_I2S_MCK_32MDIV4 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4, ///< 32 MHz / 4 = 8.0 MHz.
117 #endif
118 #if defined(I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5) || defined(__NRFX_DOXYGEN__)
119 NRF_I2S_MCK_32MDIV5 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5, ///< 32 MHz / 5 = 6.4 MHz.
120 #endif
121 #if defined(I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6) || defined(__NRFX_DOXYGEN__)
122 NRF_I2S_MCK_32MDIV6 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6, ///< 32 MHz / 6 = 5.3333333 MHz.
123 #endif
124 NRF_I2S_MCK_32MDIV8 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8, ///< 32 MHz / 8 = 4.0 MHz.
125 NRF_I2S_MCK_32MDIV10 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10, ///< 32 MHz / 10 = 3.2 MHz.
126 NRF_I2S_MCK_32MDIV11 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11, ///< 32 MHz / 11 = 2.9090909 MHz.
127 NRF_I2S_MCK_32MDIV15 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15, ///< 32 MHz / 15 = 2.1333333 MHz.
128 NRF_I2S_MCK_32MDIV16 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16, ///< 32 MHz / 16 = 2.0 MHz.
129 NRF_I2S_MCK_32MDIV21 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21, ///< 32 MHz / 21 = 1.5238095 MHz.
130 NRF_I2S_MCK_32MDIV23 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23, ///< 32 MHz / 23 = 1.3913043 MHz.
131 NRF_I2S_MCK_32MDIV30 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30, ///< 32 MHz / 30 = 1.0666667 MHz.
132 NRF_I2S_MCK_32MDIV31 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31, ///< 32 MHz / 31 = 1.0322581 MHz.
133 NRF_I2S_MCK_32MDIV32 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32, ///< 32 MHz / 32 = 1.0 MHz.
134 NRF_I2S_MCK_32MDIV42 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42, ///< 32 MHz / 42 = 0.7619048 MHz.
135 NRF_I2S_MCK_32MDIV63 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63, ///< 32 MHz / 63 = 0.5079365 MHz.
136 NRF_I2S_MCK_32MDIV125 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 ///< 32 MHz / 125 = 0.256 MHz.
137 } nrf_i2s_mck_t;
138
139 /** @brief I2S MCK/LRCK ratios. */
140 typedef enum
141 {
142 NRF_I2S_RATIO_32X = I2S_CONFIG_RATIO_RATIO_32X, ///< LRCK = MCK / 32.
143 NRF_I2S_RATIO_48X = I2S_CONFIG_RATIO_RATIO_48X, ///< LRCK = MCK / 48.
144 NRF_I2S_RATIO_64X = I2S_CONFIG_RATIO_RATIO_64X, ///< LRCK = MCK / 64.
145 NRF_I2S_RATIO_96X = I2S_CONFIG_RATIO_RATIO_96X, ///< LRCK = MCK / 96.
146 NRF_I2S_RATIO_128X = I2S_CONFIG_RATIO_RATIO_128X, ///< LRCK = MCK / 128.
147 NRF_I2S_RATIO_192X = I2S_CONFIG_RATIO_RATIO_192X, ///< LRCK = MCK / 192.
148 NRF_I2S_RATIO_256X = I2S_CONFIG_RATIO_RATIO_256X, ///< LRCK = MCK / 256.
149 NRF_I2S_RATIO_384X = I2S_CONFIG_RATIO_RATIO_384X, ///< LRCK = MCK / 384.
150 NRF_I2S_RATIO_512X = I2S_CONFIG_RATIO_RATIO_512X ///< LRCK = MCK / 512.
151 } nrf_i2s_ratio_t;
152
153 /** @brief I2S sample widths. */
154 typedef enum
155 {
156 NRF_I2S_SWIDTH_8BIT = I2S_CONFIG_SWIDTH_SWIDTH_8Bit, ///< 8 bit.
157 NRF_I2S_SWIDTH_16BIT = I2S_CONFIG_SWIDTH_SWIDTH_16Bit, ///< 16 bit.
158 NRF_I2S_SWIDTH_24BIT = I2S_CONFIG_SWIDTH_SWIDTH_24Bit, ///< 24 bit.
159 #if defined(I2S_CONFIG_SWIDTH_SWIDTH_32Bit) || defined(__NRFX_DOXYGEN__)
160 NRF_I2S_SWIDTH_32BIT = I2S_CONFIG_SWIDTH_SWIDTH_32Bit, ///< 32 bit.
161 #endif
162 #if defined(I2S_CONFIG_SWIDTH_SWIDTH_8BitIn16) || defined(__NRFX_DOXYGEN__)
163 NRF_I2S_SWIDTH_8BIT_IN16BIT = I2S_CONFIG_SWIDTH_SWIDTH_8BitIn16, ///< 8 bit sample in a 16-bit half-frame.
164 #endif
165 #if defined(I2S_CONFIG_SWIDTH_SWIDTH_8BitIn32) || defined(__NRFX_DOXYGEN__)
166 NRF_I2S_SWIDTH_8BIT_IN32BIT = I2S_CONFIG_SWIDTH_SWIDTH_8BitIn32, ///< 8 bit sample in a 32-bit half-frame.
167 #endif
168 #if defined(I2S_CONFIG_SWIDTH_SWIDTH_16BitIn32) || defined(__NRFX_DOXYGEN__)
169 NRF_I2S_SWIDTH_16BIT_IN32BIT = I2S_CONFIG_SWIDTH_SWIDTH_16BitIn32, ///< 16 bit sample in a 32-bit half-frame.
170 #endif
171 #if defined(I2S_CONFIG_SWIDTH_SWIDTH_24BitIn32) || defined(__NRFX_DOXYGEN__)
172 NRF_I2S_SWIDTH_24BIT_IN32BIT = I2S_CONFIG_SWIDTH_SWIDTH_24BitIn32, ///< 24 bit sample in a 32-bit half-frame.
173 #endif
174 } nrf_i2s_swidth_t;
175
176 /** @brief I2S alignments of sample within a frame. */
177 typedef enum
178 {
179 NRF_I2S_ALIGN_LEFT = I2S_CONFIG_ALIGN_ALIGN_Left, ///< Left-aligned.
180 NRF_I2S_ALIGN_RIGHT = I2S_CONFIG_ALIGN_ALIGN_Right ///< Right-aligned.
181 } nrf_i2s_align_t;
182
183 /** @brief I2S frame formats. */
184 typedef enum
185 {
186 NRF_I2S_FORMAT_I2S = I2S_CONFIG_FORMAT_FORMAT_I2S, ///< Original I2S format.
187 NRF_I2S_FORMAT_ALIGNED = I2S_CONFIG_FORMAT_FORMAT_Aligned ///< Alternate (left-aligned or right-aligned) format.
188 } nrf_i2s_format_t;
189
190 /** @brief I2S enabled channels. */
191 typedef enum
192 {
193 NRF_I2S_CHANNELS_STEREO = I2S_CONFIG_CHANNELS_CHANNELS_Stereo, ///< Stereo.
194 NRF_I2S_CHANNELS_LEFT = I2S_CONFIG_CHANNELS_CHANNELS_Left, ///< Left only.
195 NRF_I2S_CHANNELS_RIGHT = I2S_CONFIG_CHANNELS_CHANNELS_Right ///< Right only.
196 } nrf_i2s_channels_t;
197
198 #if NRF_I2S_HAS_CLKCONFIG
199 /** @brief I2S Clock source selection. */
200 typedef enum
201 {
202 NRF_I2S_CLKSRC_PCLK32M = I2S_CONFIG_CLKCONFIG_CLKSRC_PCLK32M, ///< 32MHz peripheral clock.
203 NRF_I2S_CLKSRC_ACLK = I2S_CONFIG_CLKCONFIG_CLKSRC_ACLK ///< Audio PLL clock.
204 } nrf_i2s_clksrc_t;
205 #endif
206
207 /**
208 * @brief Function for activating the specified I2S task.
209 *
210 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
211 * @param[in] task Task to be activated.
212 */
213 NRF_STATIC_INLINE void nrf_i2s_task_trigger(NRF_I2S_Type * p_reg,
214 nrf_i2s_task_t task);
215
216 /**
217 * @brief Function for getting the address of the specified I2S task register.
218 *
219 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
220 * @param[in] task Specified task.
221 *
222 * @return Address of the specified task register.
223 */
224 NRF_STATIC_INLINE uint32_t nrf_i2s_task_address_get(NRF_I2S_Type const * p_reg,
225 nrf_i2s_task_t task);
226
227 /**
228 * @brief Function for clearing the specified I2S event.
229 *
230 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
231 * @param[in] event Event to clear.
232 */
233 NRF_STATIC_INLINE void nrf_i2s_event_clear(NRF_I2S_Type * p_reg,
234 nrf_i2s_event_t event);
235
236 /**
237 * @brief Function for retrieving the state of the I2S event.
238 *
239 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
240 * @param[in] event Event to be checked.
241 *
242 * @retval true The event has been generated.
243 * @retval false The event has not been generated.
244 */
245 NRF_STATIC_INLINE bool nrf_i2s_event_check(NRF_I2S_Type const * p_reg,
246 nrf_i2s_event_t event);
247
248 /**
249 * @brief Function for getting the address of the specified I2S event register.
250 *
251 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
252 * @param[in] event Specified event.
253 *
254 * @return Address of the specified event register.
255 */
256 NRF_STATIC_INLINE uint32_t nrf_i2s_event_address_get(NRF_I2S_Type const * p_reg,
257 nrf_i2s_event_t event);
258
259 /**
260 * @brief Function for enabling specified interrupts.
261 *
262 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
263 * @param[in] mask Mask of interrupts to be enabled.
264 */
265 NRF_STATIC_INLINE void nrf_i2s_int_enable(NRF_I2S_Type * p_reg, uint32_t mask);
266
267 /**
268 * @brief Function for disabling specified interrupts.
269 *
270 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
271 * @param[in] mask Mask of interrupts to be disabled.
272 */
273 NRF_STATIC_INLINE void nrf_i2s_int_disable(NRF_I2S_Type * p_reg, uint32_t mask);
274
275 /**
276 * @brief Function for checking if the specified interrupts are enabled.
277 *
278 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
279 * @param[in] mask Mask of interrupts to be checked.
280 *
281 * @return Mask of enabled interrupts.
282 */
283 NRF_STATIC_INLINE uint32_t nrf_i2s_int_enable_check(NRF_I2S_Type const * p_reg, uint32_t mask);
284
285 /**
286 * @brief Function for enabling the I2S peripheral.
287 *
288 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
289 */
290 NRF_STATIC_INLINE void nrf_i2s_enable(NRF_I2S_Type * p_reg);
291
292 /**
293 * @brief Function for disabling the I2S peripheral.
294 *
295 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
296 */
297 NRF_STATIC_INLINE void nrf_i2s_disable(NRF_I2S_Type * p_reg);
298
299 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
300 /**
301 * @brief Function for setting the subscribe configuration for a given
302 * I2S task.
303 *
304 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
305 * @param[in] task Task for which to set the configuration.
306 * @param[in] channel Channel through which to subscribe events.
307 */
308 NRF_STATIC_INLINE void nrf_i2s_subscribe_set(NRF_I2S_Type * p_reg,
309 nrf_i2s_task_t task,
310 uint8_t channel);
311
312 /**
313 * @brief Function for clearing the subscribe configuration for a given
314 * I2S task.
315 *
316 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
317 * @param[in] task Task for which to clear the configuration.
318 */
319 NRF_STATIC_INLINE void nrf_i2s_subscribe_clear(NRF_I2S_Type * p_reg,
320 nrf_i2s_task_t task);
321
322 /**
323 * @brief Function for setting the publish configuration for a given
324 * I2S event.
325 *
326 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
327 * @param[in] event Event for which to set the configuration.
328 * @param[in] channel Channel through which to publish the event.
329 */
330 NRF_STATIC_INLINE void nrf_i2s_publish_set(NRF_I2S_Type * p_reg,
331 nrf_i2s_event_t event,
332 uint8_t channel);
333
334 /**
335 * @brief Function for clearing the publish configuration for a given
336 * I2S event.
337 *
338 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
339 * @param[in] event Event for which to clear the configuration.
340 */
341 NRF_STATIC_INLINE void nrf_i2s_publish_clear(NRF_I2S_Type * p_reg,
342 nrf_i2s_event_t event);
343 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
344
345 /**
346 * @brief Function for configuring I2S pins.
347 *
348 * Usage of the SDOUT, SDIN, and MCK signals is optional.
349 * If a given signal is not needed, pass the @ref NRF_I2S_PIN_NOT_CONNECTED
350 * value instead of its pin number.
351 *
352 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
353 * @param[in] sck_pin SCK pin number.
354 * @param[in] lrck_pin LRCK pin number.
355 * @param[in] mck_pin MCK pin number.
356 * @param[in] sdout_pin SDOUT pin number.
357 * @param[in] sdin_pin SDIN pin number.
358 */
359 NRF_STATIC_INLINE void nrf_i2s_pins_set(NRF_I2S_Type * p_reg,
360 uint32_t sck_pin,
361 uint32_t lrck_pin,
362 uint32_t mck_pin,
363 uint32_t sdout_pin,
364 uint32_t sdin_pin);
365
366 /**
367 * @brief Function for getting the SCK pin selection.
368 *
369 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
370 *
371 * @return SCK pin selection.
372 */
373 NRF_STATIC_INLINE uint32_t nrf_i2s_sck_pin_get(NRF_I2S_Type const * p_reg);
374
375 /**
376 * @brief Function for getting the LRCK pin selection.
377 *
378 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
379 *
380 * @return LRCK pin selection.
381 */
382 NRF_STATIC_INLINE uint32_t nrf_i2s_lrck_pin_get(NRF_I2S_Type const * p_reg);
383
384 /**
385 * @brief Function for getting the MCK pin selection.
386 *
387 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
388 *
389 * @return MCK pin selection.
390 */
391 NRF_STATIC_INLINE uint32_t nrf_i2s_mck_pin_get(NRF_I2S_Type const * p_reg);
392
393 /**
394 * @brief Function for getting the SDOUT pin selection.
395 *
396 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
397 *
398 * @return SDOUT pin selection.
399 */
400 NRF_STATIC_INLINE uint32_t nrf_i2s_sdout_pin_get(NRF_I2S_Type const * p_reg);
401
402 /**
403 * @brief Function for getting the SDIN pin selection.
404 *
405 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
406 *
407 * @return SDIN pin selection.
408 */
409 NRF_STATIC_INLINE uint32_t nrf_i2s_sdin_pin_get(NRF_I2S_Type const * p_reg);
410
411 /**
412 * @brief Function for setting the I2S peripheral configuration.
413 *
414 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
415 * @param[in] mode Mode of operation (master or slave).
416 * @param[in] format I2S frame format.
417 * @param[in] alignment Alignment of sample within a frame.
418 * @param[in] sample_width Sample width.
419 * @param[in] channels Enabled channels.
420 * @param[in] mck_setup Master clock generator setup.
421 * @param[in] ratio MCK/LRCK ratio.
422 *
423 * @retval true The configuration has been set successfully.
424 * @retval false The specified configuration is not allowed.
425 */
426 NRF_STATIC_INLINE bool nrf_i2s_configure(NRF_I2S_Type * p_reg,
427 nrf_i2s_mode_t mode,
428 nrf_i2s_format_t format,
429 nrf_i2s_align_t alignment,
430 nrf_i2s_swidth_t sample_width,
431 nrf_i2s_channels_t channels,
432 nrf_i2s_mck_t mck_setup,
433 nrf_i2s_ratio_t ratio);
434
435 /**
436 * @brief Function for setting up the I2S transfer.
437 *
438 * This function sets up the RX and TX buffers and enables reception or
439 * transmission (or both) accordingly. If the transfer in a given direction is not
440 * required, pass NULL instead of the pointer to the corresponding buffer.
441 *
442 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
443 * @param[in] size Size of the buffers (in 32-bit words).
444 * @param[in] p_rx_buffer Pointer to the receive buffer.
445 * Pass NULL to disable reception.
446 * @param[in] p_tx_buffer Pointer to the transmit buffer.
447 * Pass NULL to disable transmission.
448 */
449 NRF_STATIC_INLINE void nrf_i2s_transfer_set(NRF_I2S_Type * p_reg,
450 uint16_t size,
451 uint32_t * p_rx_buffer,
452 uint32_t const * p_tx_buffer);
453
454 /**
455 * @brief Function for setting the pointer to the receive buffer.
456 *
457 * @note The size of the buffer can be set only by calling
458 * @ref nrf_i2s_transfer_set.
459 *
460 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
461 * @param[in] p_buffer Pointer to the receive buffer.
462 */
463 NRF_STATIC_INLINE void nrf_i2s_rx_buffer_set(NRF_I2S_Type * p_reg,
464 uint32_t * p_buffer);
465
466 /**
467 * @brief Function for getting the pointer to the receive buffer.
468 *
469 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
470 *
471 * @return Pointer to the receive buffer.
472 */
473 NRF_STATIC_INLINE uint32_t * nrf_i2s_rx_buffer_get(NRF_I2S_Type const * p_reg);
474
475 /**
476 * @brief Function for setting the pointer to the transmit buffer.
477 *
478 * @note The size of the buffer can be set only by calling
479 * @ref nrf_i2s_transfer_set.
480 *
481 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
482 * @param[in] p_buffer Pointer to the transmit buffer.
483 */
484 NRF_STATIC_INLINE void nrf_i2s_tx_buffer_set(NRF_I2S_Type * p_reg,
485 uint32_t const * p_buffer);
486
487 /**
488 * @brief Function for getting the pointer to the transmit buffer.
489 *
490 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
491 *
492 * @return Pointer to the transmit buffer.
493 */
494 NRF_STATIC_INLINE uint32_t * nrf_i2s_tx_buffer_get(NRF_I2S_Type const * p_reg);
495
496 #if NRF_I2S_HAS_CLKCONFIG
497 /**
498 * @brief Function for configuring I2S Clock.
499 *
500 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
501 * @param[in] clksrc I2S Clock source selection.
502 * @param[in] enable_bypass Bypass clock generator. MCK will be equal to source input.
503 * If bypass is enabled the MCKFREQ setting has no effect.
504 */
505 NRF_STATIC_INLINE void nrf_i2s_clk_configure(NRF_I2S_Type * p_reg,
506 nrf_i2s_clksrc_t clksrc,
507 bool enable_bypass);
508 #endif
509
510 #ifndef NRF_DECLARE_ONLY
511
nrf_i2s_task_trigger(NRF_I2S_Type * p_reg,nrf_i2s_task_t task)512 NRF_STATIC_INLINE void nrf_i2s_task_trigger(NRF_I2S_Type * p_reg,
513 nrf_i2s_task_t task)
514 {
515 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
516 }
517
nrf_i2s_task_address_get(NRF_I2S_Type const * p_reg,nrf_i2s_task_t task)518 NRF_STATIC_INLINE uint32_t nrf_i2s_task_address_get(NRF_I2S_Type const * p_reg,
519 nrf_i2s_task_t task)
520 {
521 return ((uint32_t)p_reg + (uint32_t)task);
522 }
523
nrf_i2s_event_clear(NRF_I2S_Type * p_reg,nrf_i2s_event_t event)524 NRF_STATIC_INLINE void nrf_i2s_event_clear(NRF_I2S_Type * p_reg,
525 nrf_i2s_event_t event)
526 {
527 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
528 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
529 }
530
nrf_i2s_event_check(NRF_I2S_Type const * p_reg,nrf_i2s_event_t event)531 NRF_STATIC_INLINE bool nrf_i2s_event_check(NRF_I2S_Type const * p_reg,
532 nrf_i2s_event_t event)
533 {
534 return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
535 }
536
nrf_i2s_event_address_get(NRF_I2S_Type const * p_reg,nrf_i2s_event_t event)537 NRF_STATIC_INLINE uint32_t nrf_i2s_event_address_get(NRF_I2S_Type const * p_reg,
538 nrf_i2s_event_t event)
539 {
540 return ((uint32_t)p_reg + (uint32_t)event);
541 }
542
nrf_i2s_int_enable(NRF_I2S_Type * p_reg,uint32_t mask)543 NRF_STATIC_INLINE void nrf_i2s_int_enable(NRF_I2S_Type * p_reg, uint32_t mask)
544 {
545 p_reg->INTENSET = mask;
546 }
547
nrf_i2s_int_disable(NRF_I2S_Type * p_reg,uint32_t mask)548 NRF_STATIC_INLINE void nrf_i2s_int_disable(NRF_I2S_Type * p_reg, uint32_t mask)
549 {
550 p_reg->INTENCLR = mask;
551 }
552
nrf_i2s_int_enable_check(NRF_I2S_Type const * p_reg,uint32_t mask)553 NRF_STATIC_INLINE uint32_t nrf_i2s_int_enable_check(NRF_I2S_Type const * p_reg, uint32_t mask)
554 {
555 return p_reg->INTENSET & mask;
556 }
557
nrf_i2s_enable(NRF_I2S_Type * p_reg)558 NRF_STATIC_INLINE void nrf_i2s_enable(NRF_I2S_Type * p_reg)
559 {
560 p_reg->ENABLE = (I2S_ENABLE_ENABLE_Enabled << I2S_ENABLE_ENABLE_Pos);
561 }
562
nrf_i2s_disable(NRF_I2S_Type * p_reg)563 NRF_STATIC_INLINE void nrf_i2s_disable(NRF_I2S_Type * p_reg)
564 {
565 p_reg->ENABLE = (I2S_ENABLE_ENABLE_Disabled << I2S_ENABLE_ENABLE_Pos);
566 }
567
568 #if defined(DPPI_PRESENT)
nrf_i2s_subscribe_set(NRF_I2S_Type * p_reg,nrf_i2s_task_t task,uint8_t channel)569 NRF_STATIC_INLINE void nrf_i2s_subscribe_set(NRF_I2S_Type * p_reg,
570 nrf_i2s_task_t task,
571 uint8_t channel)
572 {
573 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
574 ((uint32_t)channel | I2S_SUBSCRIBE_START_EN_Msk);
575 }
576
nrf_i2s_subscribe_clear(NRF_I2S_Type * p_reg,nrf_i2s_task_t task)577 NRF_STATIC_INLINE void nrf_i2s_subscribe_clear(NRF_I2S_Type * p_reg,
578 nrf_i2s_task_t task)
579 {
580 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
581 }
582
nrf_i2s_publish_set(NRF_I2S_Type * p_reg,nrf_i2s_event_t event,uint8_t channel)583 NRF_STATIC_INLINE void nrf_i2s_publish_set(NRF_I2S_Type * p_reg,
584 nrf_i2s_event_t event,
585 uint8_t channel)
586 {
587 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
588 ((uint32_t)channel | I2S_PUBLISH_STOPPED_EN_Msk);
589 }
590
nrf_i2s_publish_clear(NRF_I2S_Type * p_reg,nrf_i2s_event_t event)591 NRF_STATIC_INLINE void nrf_i2s_publish_clear(NRF_I2S_Type * p_reg,
592 nrf_i2s_event_t event)
593 {
594 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
595 }
596 #endif // defined(DPPI_PRESENT)
597
nrf_i2s_pins_set(NRF_I2S_Type * p_reg,uint32_t sck_pin,uint32_t lrck_pin,uint32_t mck_pin,uint32_t sdout_pin,uint32_t sdin_pin)598 NRF_STATIC_INLINE void nrf_i2s_pins_set(NRF_I2S_Type * p_reg,
599 uint32_t sck_pin,
600 uint32_t lrck_pin,
601 uint32_t mck_pin,
602 uint32_t sdout_pin,
603 uint32_t sdin_pin)
604 {
605 p_reg->PSEL.SCK = sck_pin;
606 p_reg->PSEL.LRCK = lrck_pin;
607 p_reg->PSEL.MCK = mck_pin;
608 p_reg->PSEL.SDOUT = sdout_pin;
609 p_reg->PSEL.SDIN = sdin_pin;
610 }
611
nrf_i2s_sck_pin_get(NRF_I2S_Type const * p_reg)612 NRF_STATIC_INLINE uint32_t nrf_i2s_sck_pin_get(NRF_I2S_Type const * p_reg)
613 {
614 return p_reg->PSEL.SCK;
615 }
616
nrf_i2s_lrck_pin_get(NRF_I2S_Type const * p_reg)617 NRF_STATIC_INLINE uint32_t nrf_i2s_lrck_pin_get(NRF_I2S_Type const * p_reg)
618 {
619 return p_reg->PSEL.LRCK;
620 }
621
nrf_i2s_mck_pin_get(NRF_I2S_Type const * p_reg)622 NRF_STATIC_INLINE uint32_t nrf_i2s_mck_pin_get(NRF_I2S_Type const * p_reg)
623 {
624 return p_reg->PSEL.MCK;
625 }
626
nrf_i2s_sdout_pin_get(NRF_I2S_Type const * p_reg)627 NRF_STATIC_INLINE uint32_t nrf_i2s_sdout_pin_get(NRF_I2S_Type const * p_reg)
628 {
629 return p_reg->PSEL.SDOUT;
630 }
631
nrf_i2s_sdin_pin_get(NRF_I2S_Type const * p_reg)632 NRF_STATIC_INLINE uint32_t nrf_i2s_sdin_pin_get(NRF_I2S_Type const * p_reg)
633 {
634 return p_reg->PSEL.SDIN;
635 }
636
nrf_i2s_configure(NRF_I2S_Type * p_reg,nrf_i2s_mode_t mode,nrf_i2s_format_t format,nrf_i2s_align_t alignment,nrf_i2s_swidth_t sample_width,nrf_i2s_channels_t channels,nrf_i2s_mck_t mck_setup,nrf_i2s_ratio_t ratio)637 NRF_STATIC_INLINE bool nrf_i2s_configure(NRF_I2S_Type * p_reg,
638 nrf_i2s_mode_t mode,
639 nrf_i2s_format_t format,
640 nrf_i2s_align_t alignment,
641 nrf_i2s_swidth_t sample_width,
642 nrf_i2s_channels_t channels,
643 nrf_i2s_mck_t mck_setup,
644 nrf_i2s_ratio_t ratio)
645 {
646 if (mode == NRF_I2S_MODE_MASTER)
647 {
648 // The MCK/LRCK ratio must be a multiple of 2 * sample width.
649 if (((sample_width == NRF_I2S_SWIDTH_16BIT) &&
650 (ratio == NRF_I2S_RATIO_48X))
651 ||
652 ((sample_width == NRF_I2S_SWIDTH_24BIT) &&
653 ((ratio == NRF_I2S_RATIO_32X) ||
654 (ratio == NRF_I2S_RATIO_64X) ||
655 (ratio == NRF_I2S_RATIO_128X) ||
656 (ratio == NRF_I2S_RATIO_256X) ||
657 (ratio == NRF_I2S_RATIO_512X))))
658 {
659 return false;
660 }
661 }
662
663 p_reg->CONFIG.MODE = mode;
664 p_reg->CONFIG.FORMAT = format;
665 p_reg->CONFIG.ALIGN = alignment;
666 p_reg->CONFIG.SWIDTH = sample_width;
667 p_reg->CONFIG.CHANNELS = channels;
668 p_reg->CONFIG.RATIO = ratio;
669
670 if (mck_setup == NRF_I2S_MCK_DISABLED)
671 {
672 p_reg->CONFIG.MCKEN =
673 (I2S_CONFIG_MCKEN_MCKEN_Disabled << I2S_CONFIG_MCKEN_MCKEN_Pos);
674 }
675 else
676 {
677 p_reg->CONFIG.MCKFREQ = mck_setup;
678 p_reg->CONFIG.MCKEN =
679 (I2S_CONFIG_MCKEN_MCKEN_Enabled << I2S_CONFIG_MCKEN_MCKEN_Pos);
680 }
681
682 return true;
683 }
684
nrf_i2s_transfer_set(NRF_I2S_Type * p_reg,uint16_t size,uint32_t * p_buffer_rx,uint32_t const * p_buffer_tx)685 NRF_STATIC_INLINE void nrf_i2s_transfer_set(NRF_I2S_Type * p_reg,
686 uint16_t size,
687 uint32_t * p_buffer_rx,
688 uint32_t const * p_buffer_tx)
689 {
690 p_reg->RXTXD.MAXCNT = size;
691
692 nrf_i2s_rx_buffer_set(p_reg, p_buffer_rx);
693 p_reg->CONFIG.RXEN = (p_buffer_rx != NULL) ? 1 : 0;
694
695 nrf_i2s_tx_buffer_set(p_reg, p_buffer_tx);
696 p_reg->CONFIG.TXEN = (p_buffer_tx != NULL) ? 1 : 0;
697 }
698
nrf_i2s_rx_buffer_set(NRF_I2S_Type * p_reg,uint32_t * p_buffer)699 NRF_STATIC_INLINE void nrf_i2s_rx_buffer_set(NRF_I2S_Type * p_reg,
700 uint32_t * p_buffer)
701 {
702 p_reg->RXD.PTR = (uint32_t)p_buffer;
703 }
704
nrf_i2s_rx_buffer_get(NRF_I2S_Type const * p_reg)705 NRF_STATIC_INLINE uint32_t * nrf_i2s_rx_buffer_get(NRF_I2S_Type const * p_reg)
706 {
707 return (uint32_t *)(p_reg->RXD.PTR);
708 }
709
nrf_i2s_tx_buffer_set(NRF_I2S_Type * p_reg,uint32_t const * p_buffer)710 NRF_STATIC_INLINE void nrf_i2s_tx_buffer_set(NRF_I2S_Type * p_reg,
711 uint32_t const * p_buffer)
712 {
713 p_reg->TXD.PTR = (uint32_t)p_buffer;
714 }
715
nrf_i2s_tx_buffer_get(NRF_I2S_Type const * p_reg)716 NRF_STATIC_INLINE uint32_t * nrf_i2s_tx_buffer_get(NRF_I2S_Type const * p_reg)
717 {
718 return (uint32_t *)(p_reg->TXD.PTR);
719 }
720
721 #if NRF_I2S_HAS_CLKCONFIG
nrf_i2s_clk_configure(NRF_I2S_Type * p_reg,nrf_i2s_clksrc_t clksrc,bool enable_bypass)722 NRF_STATIC_INLINE void nrf_i2s_clk_configure(NRF_I2S_Type * p_reg,
723 nrf_i2s_clksrc_t clksrc,
724 bool enable_bypass)
725 {
726 p_reg->CONFIG.CLKCONFIG = ((uint32_t) clksrc << I2S_CONFIG_CLKCONFIG_CLKSRC_Pos) |
727 ((uint32_t) enable_bypass << I2S_CONFIG_CLKCONFIG_BYPASS_Pos);
728 }
729 #endif
730
731 #endif // NRF_DECLARE_ONLY
732
733 /** @} */
734
735 #ifdef __cplusplus
736 }
737 #endif
738
739 #endif // NRF_I2S_H__
740