1 /*
2  * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice, this
9  *    list of conditions and the following disclaimer.
10  *
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * 3. Neither the name of the copyright holder nor the names of its
16  *    contributors may be used to endorse or promote products derived from this
17  *    software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 #ifndef NRF_MPU_H__
33 #define NRF_MPU_H__
34 
35 #include <nrfx.h>
36 
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40 
41 /**
42  * @defgroup nrf_mpu_hal MPU HAL
43  * @{
44  * @ingroup nrf_mpu
45  * @brief   Hardware access layer for managing the Memory Protection Unit (MPU) peripheral.
46  */
47 
48 /**
49  * @brief Macro for getting MPU region configuration mask for the specified peripheral.
50  *
51  * @param[in] base_addr Peripheral base address.
52  *
53  * @return MPU configuration mask for the specified peripheral.
54  */
55 #define NRF_MPU_PERIPHERAL_MASK_GET(base_addr) (1UL << NRFX_PERIPHERAL_ID_GET(base_addr))
56 
57 /**
58  * @brief Function for setting the size of the RAM region 0.
59  *
60  * When memory protection is enabled, the Memory Protection Unit enforces
61  * runtime protection and readback protection of resources classified as region 0.
62  * See the product specification for more information.
63  *
64  * @param[in] p_reg Pointer to the structure of registers of the peripheral.
65  * @param[in] size  Size of the RAM region 0, in bytes. Must be word-aligned.
66  */
67 NRF_STATIC_INLINE void nrf_mpu_region0_ram_size_set(NRF_MPU_Type * p_reg, uint32_t size);
68 
69 /**
70  * @brief Function for configuring specified peripherals in the memory region 0.
71  *
72  * When the memory protection is enabled, the Memory Protection Unit enforces
73  * runtime protection and readback protection of resources classified as region 0.
74  * See the product specification for more information.
75  *
76  * After reset, all peripherals are configured as *not* assigned to region 0.
77  *
78  * @param[in] p_reg           Pointer to the structure of registers of the peripheral.
79  * @param[in] peripheral_mask Mask that specifies peripherals to be configured in the memory region 0.
80  *                            Compose this mask using @ref NRF_MPU_PERIPHERAL_MASK_GET macro.
81  */
82 NRF_STATIC_INLINE void nrf_mpu_region0_peripherals_set(NRF_MPU_Type * p_reg,
83                                                        uint32_t       peripheral_mask);
84 
85 /**
86  * @brief Function for getting the bitmask that specifies peripherals configured in the memory region 0.
87  *
88  * @param[in] p_reg Pointer to the structure of registers of the peripheral.
89  *
90  * @return Bitmask representing peripherals configured in region 0.
91  */
92 NRF_STATIC_INLINE uint32_t nrf_mpu_region0_peripherals_get(NRF_MPU_Type const * p_reg);
93 
94 /**
95  * @brief Function for enabling protection for specified non-volatile memory blocks.
96  *
97  * Blocks are arranged into groups of 32 blocks each. Each block size is 4 kB.
98  * Any attempt to write or erase a protected block will result in hard fault.
99  * The memory block protection can be disabled only by resetting the device.
100  *
101  * @param[in] p_reg      Pointer to the structure of registers of the peripheral.
102  * @param[in] group_idx  Non-volatile memory group containing memory blocks to protect.
103  * @param[in] block_mask Non-volatile memory blocks to protect. Each bit in bitmask represents
104  *                       one memory block in the specified group.
105  */
106 NRF_STATIC_INLINE void nrf_mpu_nvm_blocks_protection_enable(NRF_MPU_Type * p_reg,
107                                                             uint8_t        group_idx,
108                                                             uint32_t       block_mask);
109 
110 /**
111  * @brief Function for setting the non-volatile memory (NVM) protection during debug.
112  *
113  * NVM protection during debug is disabled by default.
114  *
115  * @param[in] p_reg  Pointer to the structure of registers of the peripheral.
116  * @param[in] enable True if NVM protection during debug is to be enabled, false otherwise.
117  */
118 NRF_STATIC_INLINE void nrf_mpu_nvm_protection_in_debug_set(NRF_MPU_Type * p_reg,
119                                                            bool           enable);
120 
121 #ifndef NRF_DECLARE_ONLY
122 
nrf_mpu_region0_ram_size_set(NRF_MPU_Type * p_reg,uint32_t size)123 NRF_STATIC_INLINE void nrf_mpu_region0_ram_size_set(NRF_MPU_Type * p_reg, uint32_t size)
124 {
125     NRFX_ASSERT(nrfx_is_word_aligned((const void *)size));
126     p_reg->RLENR0 = size;
127 }
128 
nrf_mpu_region0_peripherals_set(NRF_MPU_Type * p_reg,uint32_t peripheral_mask)129 NRF_STATIC_INLINE void nrf_mpu_region0_peripherals_set(NRF_MPU_Type * p_reg,
130                                                        uint32_t       peripheral_mask)
131 {
132     p_reg->PERR0 = peripheral_mask;
133 }
134 
nrf_mpu_region0_peripherals_get(NRF_MPU_Type const * p_reg)135 NRF_STATIC_INLINE uint32_t nrf_mpu_region0_peripherals_get(NRF_MPU_Type const * p_reg)
136 {
137     return p_reg->PERR0;
138 }
139 
nrf_mpu_nvm_blocks_protection_enable(NRF_MPU_Type * p_reg,uint8_t group_idx,uint32_t block_mask)140 NRF_STATIC_INLINE void nrf_mpu_nvm_blocks_protection_enable(NRF_MPU_Type * p_reg,
141                                                             uint8_t        group_idx,
142                                                             uint32_t       block_mask)
143 {
144     switch (group_idx)
145     {
146         case 0:
147             p_reg->PROTENSET0 = block_mask;
148             break;
149 
150         case 1:
151             p_reg->PROTENSET1 = block_mask;
152             break;
153 
154         default:
155             NRFX_ASSERT(false);
156             break;
157     }
158 }
159 
nrf_mpu_nvm_protection_in_debug_set(NRF_MPU_Type * p_reg,bool enable)160 NRF_STATIC_INLINE void nrf_mpu_nvm_protection_in_debug_set(NRF_MPU_Type * p_reg,
161                                                            bool           enable)
162 {
163     p_reg->DISABLEINDEBUG =
164         (enable ? 0 : MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk);
165 }
166 
167 #endif // NRF_DECLARE_ONLY
168 
169 /** @} */
170 
171 #ifdef __cplusplus
172 }
173 #endif
174 
175 #endif // NRF_MPU_H__
176