1 /*
2 * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef NRF_POWER_H__
33 #define NRF_POWER_H__
34
35 #include <nrfx.h>
36 #include <nrf_erratas.h>
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 /**
43 * @defgroup nrf_power_hal POWER HAL
44 * @{
45 * @ingroup nrf_power
46 * @brief Hardware access layer for managing the POWER peripheral.
47 */
48
49 #if defined(POWER_INTENSET_SLEEPENTER_Msk) || defined(__NRFX_DOXYGEN__)
50 /** @brief Symbol indicating whether sleep events are present. */
51 #define NRF_POWER_HAS_SLEEPEVT 1
52 #else
53 #define NRF_POWER_HAS_SLEEPEVT 0
54 #endif
55
56 #if defined(POWER_USBREGSTATUS_VBUSDETECT_Msk) || defined(__NRFX_DOXYGEN__)
57 /** @brief Symbol indicating whether the POWER peripheral controls the USB regulator. */
58 #define NRF_POWER_HAS_USBREG 1
59 #else
60 #define NRF_POWER_HAS_USBREG 0
61 #endif
62
63 #if defined(POWER_DCDCEN0_DCDCEN_Msk) || defined(__NRFX_DOXYGEN__)
64 /** @brief Symbol indicating whether DCDCEN for REG0 is present. */
65 #define NRF_POWER_HAS_DCDCEN_VDDH 1
66 #else
67 #define NRF_POWER_HAS_DCDCEN_VDDH 0
68 #endif
69
70 #if defined(POWER_DCDCEN_DCDCEN_Msk) || defined(__NRFX_DOXYGEN__)
71 /** @brief Symbol indicating whether DCDCEN for REG1 is present. */
72 #define NRF_POWER_HAS_DCDCEN 1
73 #else
74 #define NRF_POWER_HAS_DCDCEN 0
75 #endif
76
77 #if defined(POWER_INTENSET_POFWARN_Msk) || defined(__NRFX_DOXYGEN__)
78 /** @brief Symbol indicating whether power failure event is present. */
79 #define NRF_POWER_HAS_POFWARN 1
80 #else
81 #define NRF_POWER_HAS_POFWARN 0
82 #endif
83
84 #if defined(POWER_POFCON_THRESHOLD_Msk) || defined(__NRFX_DOXYGEN__)
85 /** @brief Symbol indicating whether power failure comparator is present. */
86 #define NRF_POWER_HAS_POFCON 1
87 #else
88 #define NRF_POWER_HAS_POFCON 0
89 #endif
90
91 #if defined(POWER_POFCON_THRESHOLDVDDH_Msk) || defined(__NRFX_DOXYGEN__)
92 /** @brief Symbol indicating whether power failure comparator for VDDH is present. */
93 #define NRF_POWER_HAS_POFCON_VDDH 1
94 #else
95 #define NRF_POWER_HAS_POFCON_VDDH 0
96 #endif
97
98 #if defined(POWER_RESETREAS_RESETPIN_Msk) || defined(__NRFX_DOXYGEN__)
99 /** @brief Auxiliary definition to mark the fact that RESETREAS register is present in POWER */
100 #define NRF_POWER_HAS_RESETREAS 1
101 #else
102 #define NRF_POWER_HAS_RESETREAS 0
103 #endif
104
105 #if defined(POWER_MAINREGSTATUS_MAINREGSTATUS_Msk) || defined(__NRFX_DOXYGEN__)
106 /** @brief Symbol indicating whether MAINREGSTATUS register is present. */
107 #define NRF_POWER_HAS_MAINREGSTATUS 1
108 #else
109 #define NRF_POWER_HAS_MAINREGSTATUS 0
110 #endif
111
112 /** @brief POWER tasks. */
113 typedef enum
114 {
115 NRF_POWER_TASK_CONSTLAT = offsetof(NRF_POWER_Type, TASKS_CONSTLAT), /**< Enable constant latency mode. */
116 NRF_POWER_TASK_LOWPWR = offsetof(NRF_POWER_Type, TASKS_LOWPWR ), /**< Enable low-power mode (variable latency). */
117 } nrf_power_task_t;
118
119 /** @brief POWER events. */
120 typedef enum
121 {
122 #if NRF_POWER_HAS_POFWARN
123 NRF_POWER_EVENT_POFWARN = offsetof(NRF_POWER_Type, EVENTS_POFWARN ), /**< Power failure warning. */
124 #endif
125 #if NRF_POWER_HAS_SLEEPEVT
126 NRF_POWER_EVENT_SLEEPENTER = offsetof(NRF_POWER_Type, EVENTS_SLEEPENTER ), /**< CPU entered WFI/WFE sleep. */
127 NRF_POWER_EVENT_SLEEPEXIT = offsetof(NRF_POWER_Type, EVENTS_SLEEPEXIT ), /**< CPU exited WFI/WFE sleep. */
128 #endif
129 #if NRF_POWER_HAS_USBREG
130 NRF_POWER_EVENT_USBDETECTED = offsetof(NRF_POWER_Type, EVENTS_USBDETECTED), /**< Voltage supply detected on VBUS. */
131 NRF_POWER_EVENT_USBREMOVED = offsetof(NRF_POWER_Type, EVENTS_USBREMOVED ), /**< Voltage supply removed from VBUS. */
132 NRF_POWER_EVENT_USBPWRRDY = offsetof(NRF_POWER_Type, EVENTS_USBPWRRDY ), /**< USB 3.3 V supply ready. */
133 #endif
134 } nrf_power_event_t;
135
136 /** @brief POWER interrupts. */
137 typedef enum
138 {
139 #if NRF_POWER_HAS_POFWARN
140 NRF_POWER_INT_POFWARN_MASK = POWER_INTENSET_POFWARN_Msk , /**< Write '1' to Enable interrupt for POFWARN event. */
141 #endif
142 #if NRF_POWER_HAS_SLEEPEVT
143 NRF_POWER_INT_SLEEPENTER_MASK = POWER_INTENSET_SLEEPENTER_Msk , /**< Write '1' to Enable interrupt for SLEEPENTER event. */
144 NRF_POWER_INT_SLEEPEXIT_MASK = POWER_INTENSET_SLEEPEXIT_Msk , /**< Write '1' to Enable interrupt for SLEEPEXIT event. */
145 #endif
146 #if NRF_POWER_HAS_USBREG
147 NRF_POWER_INT_USBDETECTED_MASK = POWER_INTENSET_USBDETECTED_Msk, /**< Write '1' to Enable interrupt for USBDETECTED event. */
148 NRF_POWER_INT_USBREMOVED_MASK = POWER_INTENSET_USBREMOVED_Msk , /**< Write '1' to Enable interrupt for USBREMOVED event. */
149 NRF_POWER_INT_USBPWRRDY_MASK = POWER_INTENSET_USBPWRRDY_Msk , /**< Write '1' to Enable interrupt for USBPWRRDY event. */
150 #endif
151 } nrf_power_int_mask_t;
152
153 /** @brief Reset reason. */
154 #if NRF_POWER_HAS_RESETREAS
155 typedef enum
156 {
157 NRF_POWER_RESETREAS_RESETPIN_MASK = POWER_RESETREAS_RESETPIN_Msk, /**< Bit mask of RESETPIN field. */
158 NRF_POWER_RESETREAS_DOG_MASK = POWER_RESETREAS_DOG_Msk , /**< Bit mask of DOG field. */
159 NRF_POWER_RESETREAS_SREQ_MASK = POWER_RESETREAS_SREQ_Msk , /**< Bit mask of SREQ field. */
160 NRF_POWER_RESETREAS_LOCKUP_MASK = POWER_RESETREAS_LOCKUP_Msk , /**< Bit mask of LOCKUP field. */
161 NRF_POWER_RESETREAS_OFF_MASK = POWER_RESETREAS_OFF_Msk , /**< Bit mask of OFF field. */
162 #if defined(POWER_RESETREAS_LPCOMP_Msk) || defined(__NRFX_DOXYGEN__)
163 NRF_POWER_RESETREAS_LPCOMP_MASK = POWER_RESETREAS_LPCOMP_Msk , /**< Bit mask of LPCOMP field. */
164 #endif
165 NRF_POWER_RESETREAS_DIF_MASK = POWER_RESETREAS_DIF_Msk , /**< Bit mask of DIF field. */
166 #if defined(POWER_RESETREAS_NFC_Msk) || defined(__NRFX_DOXYGEN__)
167 NRF_POWER_RESETREAS_NFC_MASK = POWER_RESETREAS_NFC_Msk , /**< Bit mask of NFC field. */
168 #endif
169 #if defined(POWER_RESETREAS_VBUS_Msk) || defined(__NRFX_DOXYGEN__)
170 NRF_POWER_RESETREAS_VBUS_MASK = POWER_RESETREAS_VBUS_Msk , /**< Bit mask of VBUS field. */
171 #endif
172 } nrf_power_resetreas_mask_t;
173 #endif // NRF_POWER_HAS_RESETREAS
174
175 #if NRF_POWER_HAS_USBREG
176 /**
177 * @brief USBREGSTATUS register bit masks
178 *
179 * @sa nrf_power_usbregstatus_get
180 */
181 typedef enum
182 {
183 NRF_POWER_USBREGSTATUS_VBUSDETECT_MASK = POWER_USBREGSTATUS_VBUSDETECT_Msk, /**< USB detected or removed. */
184 NRF_POWER_USBREGSTATUS_OUTPUTRDY_MASK = POWER_USBREGSTATUS_OUTPUTRDY_Msk /**< USB 3.3 V supply ready. */
185 } nrf_power_usbregstatus_mask_t;
186 #endif // NRF_POWER_HAS_USBREG
187
188 #if defined(POWER_RAMSTATUS_RAMBLOCK0_Msk) || defined(__NRFX_DOXYGEN__)
189 /**
190 * @brief Numbers of RAM blocks
191 *
192 * @sa nrf_power_ramblock_mask_t
193 * @note
194 * RAM blocks must be used in nRF51.
195 * In newer SoCs, RAM is divided into segments and this functionality is not supported.
196 * See the PS for mapping between the internal RAM and RAM blocks, because this
197 * mapping is not 1:1, and functions related to old style blocks must not be used.
198 */
199 typedef enum
200 {
201 NRF_POWER_RAMBLOCK0 = POWER_RAMSTATUS_RAMBLOCK0_Pos,
202 NRF_POWER_RAMBLOCK1 = POWER_RAMSTATUS_RAMBLOCK1_Pos,
203 #if defined(POWER_RAMSTATUS_RAMBLOCK2_Pos) || defined(__NRFX_DOXYGEN__)
204 NRF_POWER_RAMBLOCK2 = POWER_RAMSTATUS_RAMBLOCK2_Pos,
205 #endif
206 #if defined(POWER_RAMSTATUS_RAMBLOCK3_Pos) || defined(__NRFX_DOXYGEN__)
207 NRF_POWER_RAMBLOCK3 = POWER_RAMSTATUS_RAMBLOCK3_Pos
208 #endif
209 } nrf_power_ramblock_t;
210
211 /**
212 * @brief Masks of RAM blocks.
213 *
214 * @sa nrf_power_ramblock_t
215 */
216 typedef enum
217 {
218 NRF_POWER_RAMBLOCK0_MASK = POWER_RAMSTATUS_RAMBLOCK0_Msk,
219 NRF_POWER_RAMBLOCK1_MASK = POWER_RAMSTATUS_RAMBLOCK1_Msk,
220 #if defined(POWER_RAMSTATUS_RAMBLOCK2_Msk) || defined(__NRFX_DOXYGEN__)
221 NRF_POWER_RAMBLOCK2_MASK = POWER_RAMSTATUS_RAMBLOCK2_Msk,
222 #endif
223 #if defined(POWER_RAMSTATUS_RAMBLOCK3_Msk) || defined(__NRFX_DOXYGEN__)
224 NRF_POWER_RAMBLOCK3_MASK = POWER_RAMSTATUS_RAMBLOCK3_Msk
225 #endif
226 } nrf_power_ramblock_mask_t;
227 #endif // defined(POWER_RAMSTATUS_RAMBLOCK0_Msk) || defined(__NRFX_DOXYGEN__)
228
229 /**
230 * @brief RAM power state position of the bits
231 *
232 * @sa nrf_power_onoffram_mask_t
233 */
234 typedef enum
235 {
236 NRF_POWER_ONRAM0, /**< Keep RAM block 0 ON or OFF in System ON mode. */
237 NRF_POWER_OFFRAM0, /**< Keep retention on RAM block 0 when RAM block is switched OFF. */
238 NRF_POWER_ONRAM1, /**< Keep RAM block 1 ON or OFF in System ON mode. */
239 NRF_POWER_OFFRAM1, /**< Keep retention on RAM block 1 when RAM block is switched OFF. */
240 NRF_POWER_ONRAM2, /**< Keep RAM block 2 ON or OFF in System ON mode. */
241 NRF_POWER_OFFRAM2, /**< Keep retention on RAM block 2 when RAM block is switched OFF. */
242 NRF_POWER_ONRAM3, /**< Keep RAM block 3 ON or OFF in System ON mode. */
243 NRF_POWER_OFFRAM3, /**< Keep retention on RAM block 3 when RAM block is switched OFF. */
244 }nrf_power_onoffram_t;
245
246 /**
247 * @brief RAM power state bit masks
248 *
249 * @sa nrf_power_onoffram_t
250 */
251 typedef enum
252 {
253 NRF_POWER_ONRAM0_MASK = 1U << NRF_POWER_ONRAM0, /**< Keep RAM block 0 ON or OFF in System ON mode. */
254 NRF_POWER_OFFRAM0_MASK = 1U << NRF_POWER_OFFRAM0, /**< Keep retention on RAM block 0 when RAM block is switched OFF. */
255 NRF_POWER_ONRAM1_MASK = 1U << NRF_POWER_ONRAM1, /**< Keep RAM block 1 ON or OFF in System ON mode. */
256 NRF_POWER_OFFRAM1_MASK = 1U << NRF_POWER_OFFRAM1, /**< Keep retention on RAM block 1 when RAM block is switched OFF. */
257 NRF_POWER_ONRAM2_MASK = 1U << NRF_POWER_ONRAM2, /**< Keep RAM block 2 ON or OFF in System ON mode. */
258 NRF_POWER_OFFRAM2_MASK = 1U << NRF_POWER_OFFRAM2, /**< Keep retention on RAM block 2 when RAM block is switched OFF. */
259 NRF_POWER_ONRAM3_MASK = 1U << NRF_POWER_ONRAM3, /**< Keep RAM block 3 ON or OFF in System ON mode. */
260 NRF_POWER_OFFRAM3_MASK = 1U << NRF_POWER_OFFRAM3, /**< Keep retention on RAM block 3 when RAM block is switched OFF. */
261 }nrf_power_onoffram_mask_t;
262
263 #if NRF_POWER_HAS_POFCON
264 /** @brief Power failure comparator thresholds. */
265 typedef enum
266 {
267 NRF_POWER_POFTHR_V21 = POWER_POFCON_THRESHOLD_V21, /**< Set threshold to 2.1 V. */
268 NRF_POWER_POFTHR_V23 = POWER_POFCON_THRESHOLD_V23, /**< Set threshold to 2.3 V. */
269 NRF_POWER_POFTHR_V25 = POWER_POFCON_THRESHOLD_V25, /**< Set threshold to 2.5 V. */
270 NRF_POWER_POFTHR_V27 = POWER_POFCON_THRESHOLD_V27, /**< Set threshold to 2.7 V. */
271 #if defined(POWER_POFCON_THRESHOLD_V17) || defined(__NRFX_DOXYGEN__)
272 NRF_POWER_POFTHR_V17 = POWER_POFCON_THRESHOLD_V17, /**< Set threshold to 1.7 V. */
273 NRF_POWER_POFTHR_V18 = POWER_POFCON_THRESHOLD_V18, /**< Set threshold to 1.8 V. */
274 NRF_POWER_POFTHR_V19 = POWER_POFCON_THRESHOLD_V19, /**< Set threshold to 1.9 V. */
275 NRF_POWER_POFTHR_V20 = POWER_POFCON_THRESHOLD_V20, /**< Set threshold to 2.0 V. */
276 NRF_POWER_POFTHR_V22 = POWER_POFCON_THRESHOLD_V22, /**< Set threshold to 2.2 V. */
277 NRF_POWER_POFTHR_V24 = POWER_POFCON_THRESHOLD_V24, /**< Set threshold to 2.4 V. */
278 NRF_POWER_POFTHR_V26 = POWER_POFCON_THRESHOLD_V26, /**< Set threshold to 2.6 V. */
279 NRF_POWER_POFTHR_V28 = POWER_POFCON_THRESHOLD_V28, /**< Set threshold to 2.8 V. */
280 #endif // defined(POWER_POFCON_THRESHOLD_V17) || defined(__NRFX_DOXYGEN__)
281 } nrf_power_pof_thr_t;
282 #endif // NRF_POWER_HAS_POFCON
283
284 #if NRF_POWER_HAS_POFCON_VDDH
285 /** @brief Power failure comparator thresholds for VDDH. */
286 typedef enum
287 {
288 NRF_POWER_POFTHRVDDH_V27 = POWER_POFCON_THRESHOLDVDDH_V27, /**< Set threshold to 2.7 V. */
289 NRF_POWER_POFTHRVDDH_V28 = POWER_POFCON_THRESHOLDVDDH_V28, /**< Set threshold to 2.8 V. */
290 NRF_POWER_POFTHRVDDH_V29 = POWER_POFCON_THRESHOLDVDDH_V29, /**< Set threshold to 2.9 V. */
291 NRF_POWER_POFTHRVDDH_V30 = POWER_POFCON_THRESHOLDVDDH_V30, /**< Set threshold to 3.0 V. */
292 NRF_POWER_POFTHRVDDH_V31 = POWER_POFCON_THRESHOLDVDDH_V31, /**< Set threshold to 3.1 V. */
293 NRF_POWER_POFTHRVDDH_V32 = POWER_POFCON_THRESHOLDVDDH_V32, /**< Set threshold to 3.2 V. */
294 NRF_POWER_POFTHRVDDH_V33 = POWER_POFCON_THRESHOLDVDDH_V33, /**< Set threshold to 3.3 V. */
295 NRF_POWER_POFTHRVDDH_V34 = POWER_POFCON_THRESHOLDVDDH_V34, /**< Set threshold to 3.4 V. */
296 NRF_POWER_POFTHRVDDH_V35 = POWER_POFCON_THRESHOLDVDDH_V35, /**< Set threshold to 3.5 V. */
297 NRF_POWER_POFTHRVDDH_V36 = POWER_POFCON_THRESHOLDVDDH_V36, /**< Set threshold to 3.6 V. */
298 NRF_POWER_POFTHRVDDH_V37 = POWER_POFCON_THRESHOLDVDDH_V37, /**< Set threshold to 3.7 V. */
299 NRF_POWER_POFTHRVDDH_V38 = POWER_POFCON_THRESHOLDVDDH_V38, /**< Set threshold to 3.8 V. */
300 NRF_POWER_POFTHRVDDH_V39 = POWER_POFCON_THRESHOLDVDDH_V39, /**< Set threshold to 3.9 V. */
301 NRF_POWER_POFTHRVDDH_V40 = POWER_POFCON_THRESHOLDVDDH_V40, /**< Set threshold to 4.0 V. */
302 NRF_POWER_POFTHRVDDH_V41 = POWER_POFCON_THRESHOLDVDDH_V41, /**< Set threshold to 4.1 V. */
303 NRF_POWER_POFTHRVDDH_V42 = POWER_POFCON_THRESHOLDVDDH_V42, /**< Set threshold to 4.2 V. */
304 } nrf_power_pof_thrvddh_t;
305 #endif // NRF_POWER_HAS_POFCON_VDDH
306
307 #if NRF_POWER_HAS_MAINREGSTATUS
308 /** @brief Main regulator status. */
309 typedef enum
310 {
311 NRF_POWER_MAINREGSTATUS_NORMAL = POWER_MAINREGSTATUS_MAINREGSTATUS_Normal, /**< Normal voltage mode. Voltage supplied on VDD. */
312 NRF_POWER_MAINREGSTATUS_HIGH = POWER_MAINREGSTATUS_MAINREGSTATUS_High /**< High voltage mode. Voltage supplied on VDDH. */
313 } nrf_power_mainregstatus_t;
314 #endif
315
316 #if defined(POWER_RAM_POWER_S0POWER_Msk) || defined(__NRFX_DOXYGEN__)
317 /**
318 * @brief Bit positions for RAMPOWER register
319 *
320 * All possible bits described, even if they are not used in selected MCU.
321 */
322 typedef enum
323 {
324 /** Keep RAM section S0 ON in System ON mode */
325 NRF_POWER_RAMPOWER_S0POWER = POWER_RAM_POWER_S0POWER_Pos,
326 NRF_POWER_RAMPOWER_S1POWER, /**< Keep RAM section S1 ON in System ON mode. */
327 NRF_POWER_RAMPOWER_S2POWER, /**< Keep RAM section S2 ON in System ON mode. */
328 NRF_POWER_RAMPOWER_S3POWER, /**< Keep RAM section S3 ON in System ON mode. */
329 NRF_POWER_RAMPOWER_S4POWER, /**< Keep RAM section S4 ON in System ON mode. */
330 NRF_POWER_RAMPOWER_S5POWER, /**< Keep RAM section S5 ON in System ON mode. */
331 NRF_POWER_RAMPOWER_S6POWER, /**< Keep RAM section S6 ON in System ON mode. */
332 NRF_POWER_RAMPOWER_S7POWER, /**< Keep RAM section S7 ON in System ON mode. */
333 NRF_POWER_RAMPOWER_S8POWER, /**< Keep RAM section S8 ON in System ON mode. */
334 NRF_POWER_RAMPOWER_S9POWER, /**< Keep RAM section S9 ON in System ON mode. */
335 NRF_POWER_RAMPOWER_S10POWER, /**< Keep RAM section S10 ON in System ON mode. */
336 NRF_POWER_RAMPOWER_S11POWER, /**< Keep RAM section S11 ON in System ON mode. */
337 NRF_POWER_RAMPOWER_S12POWER, /**< Keep RAM section S12 ON in System ON mode. */
338 NRF_POWER_RAMPOWER_S13POWER, /**< Keep RAM section S13 ON in System ON mode. */
339 NRF_POWER_RAMPOWER_S14POWER, /**< Keep RAM section S14 ON in System ON mode. */
340 NRF_POWER_RAMPOWER_S15POWER, /**< Keep RAM section S15 ON in System ON mode. */
341
342 /** Keep section retention in OFF mode when section is OFF */
343 NRF_POWER_RAMPOWER_S0RETENTION = POWER_RAM_POWER_S0RETENTION_Pos,
344 NRF_POWER_RAMPOWER_S1RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
345 NRF_POWER_RAMPOWER_S2RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
346 NRF_POWER_RAMPOWER_S3RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
347 NRF_POWER_RAMPOWER_S4RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
348 NRF_POWER_RAMPOWER_S5RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
349 NRF_POWER_RAMPOWER_S6RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
350 NRF_POWER_RAMPOWER_S7RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
351 NRF_POWER_RAMPOWER_S8RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
352 NRF_POWER_RAMPOWER_S9RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
353 NRF_POWER_RAMPOWER_S10RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
354 NRF_POWER_RAMPOWER_S11RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
355 NRF_POWER_RAMPOWER_S12RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
356 NRF_POWER_RAMPOWER_S13RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
357 NRF_POWER_RAMPOWER_S14RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
358 NRF_POWER_RAMPOWER_S15RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
359 } nrf_power_rampower_t;
360
361 /**
362 * @brief Bit masks for RAMPOWER register
363 *
364 * All possible bits described, even if they are not used in selected MCU.
365 */
366 typedef enum
367 {
368 NRF_POWER_RAMPOWER_S0POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S0POWER ,
369 NRF_POWER_RAMPOWER_S1POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S1POWER ,
370 NRF_POWER_RAMPOWER_S2POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S2POWER ,
371 NRF_POWER_RAMPOWER_S3POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S3POWER ,
372 NRF_POWER_RAMPOWER_S4POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S4POWER ,
373 NRF_POWER_RAMPOWER_S5POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S5POWER ,
374 NRF_POWER_RAMPOWER_S7POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S7POWER ,
375 NRF_POWER_RAMPOWER_S8POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S8POWER ,
376 NRF_POWER_RAMPOWER_S9POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S9POWER ,
377 NRF_POWER_RAMPOWER_S10POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S10POWER,
378 NRF_POWER_RAMPOWER_S11POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S11POWER,
379 NRF_POWER_RAMPOWER_S12POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S12POWER,
380 NRF_POWER_RAMPOWER_S13POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S13POWER,
381 NRF_POWER_RAMPOWER_S14POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S14POWER,
382 NRF_POWER_RAMPOWER_S15POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S15POWER,
383
384 NRF_POWER_RAMPOWER_S0RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S0RETENTION ,
385 NRF_POWER_RAMPOWER_S1RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S1RETENTION ,
386 NRF_POWER_RAMPOWER_S2RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S2RETENTION ,
387 NRF_POWER_RAMPOWER_S3RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S3RETENTION ,
388 NRF_POWER_RAMPOWER_S4RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S4RETENTION ,
389 NRF_POWER_RAMPOWER_S5RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S5RETENTION ,
390 NRF_POWER_RAMPOWER_S7RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S7RETENTION ,
391 NRF_POWER_RAMPOWER_S8RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S8RETENTION ,
392 NRF_POWER_RAMPOWER_S9RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S9RETENTION ,
393 NRF_POWER_RAMPOWER_S10RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S10RETENTION,
394 NRF_POWER_RAMPOWER_S11RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S11RETENTION,
395 NRF_POWER_RAMPOWER_S12RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S12RETENTION,
396 NRF_POWER_RAMPOWER_S13RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S13RETENTION,
397 NRF_POWER_RAMPOWER_S14RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S14RETENTION,
398 NRF_POWER_RAMPOWER_S15RETENTION_MASK = (int)(1UL << NRF_POWER_RAMPOWER_S15RETENTION),
399 } nrf_power_rampower_mask_t;
400 #endif // defined(POWER_RAM_POWER_S0POWER_Msk) || defined(__NRFX_DOXYGEN__)
401
402 /**
403 * @brief Function for activating a specific POWER task.
404 *
405 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
406 * @param[in] task Task.
407 */
408 NRF_STATIC_INLINE void nrf_power_task_trigger(NRF_POWER_Type * p_reg, nrf_power_task_t task);
409
410 /**
411 * @brief Function for returning the address of a specific POWER task register.
412 *
413 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
414 * @param[in] task Task.
415 *
416 * @return Task address.
417 */
418 NRF_STATIC_INLINE uint32_t nrf_power_task_address_get(NRF_POWER_Type const * p_reg,
419 nrf_power_task_t task);
420
421 /**
422 * @brief Function for clearing a specific event.
423 *
424 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
425 * @param[in] event Event.
426 */
427 NRF_STATIC_INLINE void nrf_power_event_clear(NRF_POWER_Type * p_reg, nrf_power_event_t event);
428
429 /**
430 * @brief Function for retrieving the state of the POWER event.
431 *
432 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
433 * @param[in] event Event to be checked.
434 *
435 * @retval true The event has been generated.
436 * @retval false The event has not been generated.
437 */
438 NRF_STATIC_INLINE bool nrf_power_event_check(NRF_POWER_Type const * p_reg, nrf_power_event_t event);
439
440 /**
441 * @brief Function for getting and clearing the state of specific event
442 *
443 * This function checks the state of the event and clears it.
444 *
445 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
446 * @param[in] event Event.
447 *
448 * @retval true The event was set.
449 * @retval false The event was not set.
450 */
451 NRF_STATIC_INLINE bool nrf_power_event_get_and_clear(NRF_POWER_Type * p_reg,
452 nrf_power_event_t event);
453
454 /**
455 * @brief Function for returning the address of a specific POWER event register.
456 *
457 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
458 * @param[in] event Event.
459 *
460 * @return Address.
461 */
462 NRF_STATIC_INLINE uint32_t nrf_power_event_address_get(NRF_POWER_Type const * p_reg,
463 nrf_power_event_t event);
464
465 /**
466 * @brief Function for enabling selected interrupts.
467 *
468 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
469 * @param[in] mask Mask of interrupts to be enabled.
470 */
471 NRF_STATIC_INLINE void nrf_power_int_enable(NRF_POWER_Type * p_reg, uint32_t mask);
472
473 /**
474 * @brief Function for checking if the specified interrupts are enabled.
475 *
476 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
477 * @param[in] mask Mask of interrupts to be checked.
478 *
479 * @return Mask of enabled interrupts.
480 */
481 NRF_STATIC_INLINE uint32_t nrf_power_int_enable_check(NRF_POWER_Type const * p_reg, uint32_t mask);
482
483 /**
484 * @brief Function for retrieving the information about enabled interrupts.
485 *
486 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
487 *
488 * @return The flags of enabled interrupts.
489 */
490 NRF_STATIC_INLINE uint32_t nrf_power_int_enable_get(NRF_POWER_Type const * p_reg);
491
492 /**
493 * @brief Function for disabling selected interrupts.
494 *
495 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
496 * @param[in] mask Mask of interrupts to be disabled.
497 */
498 NRF_STATIC_INLINE void nrf_power_int_disable(NRF_POWER_Type * p_reg, uint32_t mask);
499
500 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
501 /**
502 * @brief Function for setting the subscribe configuration for a given
503 * POWER task.
504 *
505 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
506 * @param[in] task Task for which to set the configuration.
507 * @param[in] channel Channel through which to subscribe events.
508 */
509 NRF_STATIC_INLINE void nrf_power_subscribe_set(NRF_POWER_Type * p_reg,
510 nrf_power_task_t task,
511 uint8_t channel);
512
513 /**
514 * @brief Function for clearing the subscribe configuration for a given
515 * POWER task.
516 *
517 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
518 * @param[in] task Task for which to clear the configuration.
519 */
520 NRF_STATIC_INLINE void nrf_power_subscribe_clear(NRF_POWER_Type * p_reg, nrf_power_task_t task);
521
522 /**
523 * @brief Function for setting the publish configuration for a given
524 * POWER event.
525 *
526 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
527 * @param[in] event Event for which to set the configuration.
528 * @param[in] channel Channel through which to publish the event.
529 */
530 NRF_STATIC_INLINE void nrf_power_publish_set(NRF_POWER_Type * p_reg,
531 nrf_power_event_t event,
532 uint8_t channel);
533
534 /**
535 * @brief Function for clearing the publish configuration for a given
536 * POWER event.
537 *
538 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
539 * @param[in] event Event for which to clear the configuration.
540 */
541 NRF_STATIC_INLINE void nrf_power_publish_clear(NRF_POWER_Type * p_reg, nrf_power_event_t event);
542 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
543
544 #if NRF_POWER_HAS_RESETREAS
545 /**
546 * @brief Function for getting the reset reason bitmask.
547 *
548 * This function returns the reset reason bitmask.
549 * Unless cleared, the RESETREAS register is cumulative.
550 * A field is cleared by writing '1' to it (see @ref nrf_power_resetreas_clear).
551 * If none of the reset sources is flagged,
552 * the chip was reset from the on-chip reset generator,
553 * which indicates a power-on-reset or a brown out reset.
554 *
555 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
556 *
557 * @return The mask of reset reasons constructed with @ref nrf_power_resetreas_mask_t.
558 */
559 NRF_STATIC_INLINE uint32_t nrf_power_resetreas_get(NRF_POWER_Type const * p_reg);
560
561 /**
562 * @brief Function for clearing the selected reset reason field.
563 *
564 * This function clears the selected reset reason field.
565 *
566 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
567 * @param[in] mask The mask constructed from @ref nrf_power_resetreas_mask_t enumerator values.
568 *
569 * @sa nrf_power_resetreas_get
570 */
571 NRF_STATIC_INLINE void nrf_power_resetreas_clear(NRF_POWER_Type * p_reg, uint32_t mask);
572 #endif // NRF_POWER_HAS_RESETREAS
573
574 #if defined(POWER_POWERSTATUS_LTEMODEM_Msk) || defined(__NRFX_DOXYGEN__)
575 /**
576 * @brief Function for getting power status of the LTE Modem domain.
577 *
578 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
579 *
580 * @retval true The LTE Modem domain is powered on.
581 * @retval false The LTE Modem domain is powered off.
582 */
583 NRF_STATIC_INLINE bool nrf_power_powerstatus_get(NRF_POWER_Type const * p_reg);
584 #endif
585
586 #if defined(POWER_RAMSTATUS_RAMBLOCK0_Msk) || defined(__NRFX_DOXYGEN__)
587 /**
588 * @brief Function for getting the RAMSTATUS register.
589 *
590 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
591 *
592 * @return Value with bits set according to the masks in @ref nrf_power_ramblock_mask_t.
593 */
594 NRF_STATIC_INLINE uint32_t nrf_power_ramstatus_get(NRF_POWER_Type const * p_reg);
595 #endif // defined(POWER_RAMSTATUS_RAMBLOCK0_Msk) || defined(__NRFX_DOXYGEN__)
596
597 #if defined(POWER_SYSTEMOFF_SYSTEMOFF_Enter)
598 /**
599 * @brief Function for going into System OFF mode.
600 *
601 * This function puts the CPU in System OFF mode.
602 * The only way to wake up the CPU is by reset.
603 *
604 * @note This function never returns.
605 *
606 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
607 */
608 NRF_STATIC_INLINE void nrf_power_system_off(NRF_POWER_Type * p_reg);
609 #endif // defined(POWER_SYSTEMOFF_SYSTEMOFF_Enter)
610
611 #if NRF_POWER_HAS_POFCON
612 /**
613 * @brief Function for setting the power failure comparator configuration.
614 *
615 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
616 * @param[in] enable True if the power failure comparator is to be enabled, false otherwise.
617 * @param[in] thr voltage threshold value.
618 */
619 NRF_STATIC_INLINE void nrf_power_pofcon_set(NRF_POWER_Type * p_reg,
620 bool enable,
621 nrf_power_pof_thr_t thr);
622
623 /**
624 * @brief Function for getting the power failure comparator configuration.
625 *
626 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
627 * @param[out] p_enabled Function sets this boolean variable to true
628 * if power failure comparator is enabled.
629 * The pointer can be NULL if we do not need this information.
630 *
631 * @return Threshold setting for power failure comparator.
632 */
633 NRF_STATIC_INLINE nrf_power_pof_thr_t nrf_power_pofcon_get(NRF_POWER_Type const * p_reg,
634 bool * p_enabled);
635 #endif // NRF_POWER_HAS_POFCON
636
637 #if NRF_POWER_HAS_POFCON_VDDH
638 /**
639 * @brief Function for setting the VDDH power failure comparator threshold.
640 *
641 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
642 * @param[in] thr Threshold to be set.
643 */
644 NRF_STATIC_INLINE void nrf_power_pofcon_vddh_set(NRF_POWER_Type * p_reg,
645 nrf_power_pof_thrvddh_t thr);
646
647 /**
648 * @brief Function for getting the VDDH power failure comparator threshold.
649 *
650 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
651 *
652 * @return VDDH threshold currently configured.
653 */
654 NRF_STATIC_INLINE nrf_power_pof_thrvddh_t nrf_power_pofcon_vddh_get(NRF_POWER_Type const * p_reg);
655 #endif // NRF_POWER_HAS_POFCON_VDDH
656
657 /**
658 * @brief Function for setting the general purpose retention register.
659 *
660 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
661 * @param[in] val Value to be set in the register.
662 */
663 NRF_STATIC_INLINE void nrf_power_gpregret_set(NRF_POWER_Type * p_reg, uint8_t val);
664
665 /**
666 * @brief Function for getting general purpose retention register.
667 *
668 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
669 *
670 * @return The value from the register.
671 */
672 NRF_STATIC_INLINE uint8_t nrf_power_gpregret_get(NRF_POWER_Type const * p_reg);
673
674 #if defined(POWER_GPREGRET2_GPREGRET_Msk) || defined(__NRFX_DOXYGEN__)
675 /**
676 * @brief Function for setting the general purpose retention register 2.
677 *
678 * @note This register is not available in the nRF51 MCU family.
679 *
680 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
681 * @param[in] val Value to be set in the register.
682 */
683 NRF_STATIC_INLINE void nrf_power_gpregret2_set(NRF_POWER_Type * p_reg, uint8_t val);
684
685 /**
686 * @brief Function for getting the general purpose retention register 2.
687 *
688 * @note This register is not available in all MCUs.
689 *
690 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
691 *
692 * @return The value from the register.
693 */
694 NRF_STATIC_INLINE uint8_t nrf_power_gpregret2_get(NRF_POWER_Type const * p_reg);
695 #endif // defined(POWER_GPREGRET2_GPREGRET_Msk) || defined(__NRFX_DOXYGEN__)
696
697 /**
698 * @brief Function for getting value of the particular general purpose retention register
699 *
700 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
701 * @param[in] reg_num General purpose retention register number.
702 *
703 * @return The value from the register
704 */
705 NRF_STATIC_INLINE uint8_t nrf_power_gpregret_ext_get(NRF_POWER_Type const * p_reg, uint8_t reg_num);
706
707 /**
708 * @brief Function for setting particular general purpose retention register.
709 *
710 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
711 * @param[in] reg_num General purpose retention register number.
712 * @param[in] val Value to be set in the register
713 */
714 NRF_STATIC_INLINE void nrf_power_gpregret_ext_set(NRF_POWER_Type * p_reg,
715 uint8_t reg_num,
716 uint8_t val);
717
718 #if NRF_POWER_HAS_DCDCEN
719 /**
720 * @brief Enable or disable DCDC converter
721 *
722 * @note If the device consist of high voltage power input (VDDH), this setting
723 * will relate to the converter on low voltage side (1.3 V output).
724 *
725 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
726 * @param[in] enable True if DCDC converter is to be enabled, false otherwise.
727 */
728 NRF_STATIC_INLINE void nrf_power_dcdcen_set(NRF_POWER_Type * p_reg, bool enable);
729
730 /**
731 * @brief Function for getting the state of the DCDC converter.
732 *
733 * @note If the device consist of high voltage power input (VDDH), this setting
734 * will relate to the converter on low voltage side (1.3 V output).
735 *
736 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
737 *
738 * @retval true Converter is enabled.
739 * @retval false Converter is disabled.
740 */
741 NRF_STATIC_INLINE bool nrf_power_dcdcen_get(NRF_POWER_Type const * p_reg);
742 #endif // NRF_POWER_HAS_DCDCEN
743
744 #if defined(POWER_RAM_POWER_S0POWER_Msk) || defined(__NRFX_DOXYGEN__)
745 /**
746 * @brief Turn ON sections in the selected RAM block.
747 *
748 * This function turns ON several sections in one block and also block retention.
749 *
750 * @sa nrf_power_rampower_mask_t
751 * @sa nrf_power_rampower_mask_off
752 *
753 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
754 * @param[in] block RAM block index.
755 * @param[in] section_mask Mask of the sections created by merging
756 * @ref nrf_power_rampower_mask_t flags.
757 */
758 NRF_STATIC_INLINE void nrf_power_rampower_mask_on(NRF_POWER_Type * p_reg,
759 uint8_t block,
760 uint32_t section_mask);
761
762 /**
763 * @brief Turn ON sections in the selected RAM block.
764 *
765 * This function turns OFF several sections in one block and also block retention.
766 *
767 * @sa nrf_power_rampower_mask_t
768 * @sa nrf_power_rampower_mask_off
769 *
770 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
771 * @param[in] block RAM block index.
772 * @param[in] section_mask Mask of the sections created by merging
773 * @ref nrf_power_rampower_mask_t flags.
774 */
775 NRF_STATIC_INLINE void nrf_power_rampower_mask_off(NRF_POWER_Type * p_reg,
776 uint8_t block,
777 uint32_t section_mask);
778
779 /**
780 * @brief Function for getting the ON mask and retention sections in the selected RAM block.
781 *
782 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
783 * @param[in] block RAM block index.
784 *
785 * @return Mask of sections state composed from @ref nrf_power_rampower_mask_t flags.
786 */
787 NRF_STATIC_INLINE uint32_t nrf_power_rampower_mask_get(NRF_POWER_Type const * p_reg, uint8_t block);
788 #endif /* defined(POWER_RAM_POWER_S0POWER_Msk) || defined(__NRFX_DOXYGEN__) */
789
790 #if NRF_POWER_HAS_DCDCEN_VDDH
791 /**
792 * @brief Function for enabling or disabling the DCDC converter on VDDH.
793 *
794 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
795 * @param[in] enable True if DCDC converter on VDDH is to be enabled, false otherwise.
796 */
797 NRF_STATIC_INLINE void nrf_power_dcdcen_vddh_set(NRF_POWER_Type * p_reg, bool enable);
798
799 /**
800 * @brief Function for getting the state of DCDC converter on VDDH.
801 *
802 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
803 *
804 * @retval true Converter is enabled.
805 * @retval false Converter is disabled.
806 */
807 NRF_STATIC_INLINE bool nrf_power_dcdcen_vddh_get(NRF_POWER_Type const * p_reg);
808 #endif // NRF_POWER_HAS_DCDCEN_VDDH
809
810 #if NRF_POWER_HAS_MAINREGSTATUS
811 /**
812 * @brief Function for getting the main supply status.
813 *
814 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
815 *
816 * @return The current main supply status.
817 */
818 NRF_STATIC_INLINE
819 nrf_power_mainregstatus_t nrf_power_mainregstatus_get(NRF_POWER_Type const * p_reg);
820 #endif // NRF_POWER_HAS_MAINREGSTATUS
821
822 #if NRF_POWER_HAS_USBREG
823 /**
824 * @brief Function for getting the whole USBREGSTATUS register.
825 *
826 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
827 *
828 * @return The USBREGSTATUS register value.
829 * Use @ref nrf_power_usbregstatus_mask_t values for bit masking.
830 *
831 * @sa nrf_power_usbregstatus_vbusdet_get
832 * @sa nrf_power_usbregstatus_outrdy_get
833 */
834 NRF_STATIC_INLINE uint32_t nrf_power_usbregstatus_get(NRF_POWER_Type const * p_reg);
835
836 /**
837 * @brief Function for getting the VBUS input detection status.
838 *
839 * USBDETECTED and USBREMOVED events are derived from this information
840 *
841 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
842 *
843 * @retval false VBUS voltage below valid threshold.
844 * @retval true VBUS voltage above valid threshold.
845 *
846 * @sa nrf_power_usbregstatus_get
847 */
848 NRF_STATIC_INLINE bool nrf_power_usbregstatus_vbusdet_get(NRF_POWER_Type const * p_reg);
849
850 /**
851 * @brief Function for getting the state of the elapsed time for the USB supply output settling.
852 *
853 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
854 *
855 * @retval false USBREG output settling time not elapsed.
856 * @retval true USBREG output settling time elapsed
857 * (same information as USBPWRRDY event).
858 *
859 * @sa nrf_power_usbregstatus_get
860 */
861 NRF_STATIC_INLINE bool nrf_power_usbregstatus_outrdy_get(NRF_POWER_Type const * p_reg);
862 #endif // NRF_POWER_HAS_USBREG
863
864 #ifndef NRF_DECLARE_ONLY
865
nrf_power_task_trigger(NRF_POWER_Type * p_reg,nrf_power_task_t task)866 NRF_STATIC_INLINE void nrf_power_task_trigger(NRF_POWER_Type * p_reg, nrf_power_task_t task)
867 {
868 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
869 }
870
nrf_power_task_address_get(NRF_POWER_Type const * p_reg,nrf_power_task_t task)871 NRF_STATIC_INLINE uint32_t nrf_power_task_address_get(NRF_POWER_Type const * p_reg,
872 nrf_power_task_t task)
873 {
874 return ((uint32_t)p_reg + (uint32_t)task);
875 }
876
nrf_power_event_clear(NRF_POWER_Type * p_reg,nrf_power_event_t event)877 NRF_STATIC_INLINE void nrf_power_event_clear(NRF_POWER_Type * p_reg, nrf_power_event_t event)
878 {
879 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
880 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
881 }
882
nrf_power_event_check(NRF_POWER_Type const * p_reg,nrf_power_event_t event)883 NRF_STATIC_INLINE bool nrf_power_event_check(NRF_POWER_Type const * p_reg, nrf_power_event_t event)
884 {
885 return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
886 }
887
nrf_power_event_get_and_clear(NRF_POWER_Type * p_reg,nrf_power_event_t event)888 NRF_STATIC_INLINE bool nrf_power_event_get_and_clear(NRF_POWER_Type * p_reg,
889 nrf_power_event_t event)
890 {
891 bool ret = nrf_power_event_check(p_reg, event);
892 if (ret)
893 {
894 nrf_power_event_clear(p_reg, event);
895 }
896 return ret;
897 }
898
nrf_power_event_address_get(NRF_POWER_Type const * p_reg,nrf_power_event_t event)899 NRF_STATIC_INLINE uint32_t nrf_power_event_address_get(NRF_POWER_Type const * p_reg,
900 nrf_power_event_t event)
901 {
902 return ((uint32_t)p_reg + (uint32_t)event);
903 }
904
nrf_power_int_enable(NRF_POWER_Type * p_reg,uint32_t mask)905 NRF_STATIC_INLINE void nrf_power_int_enable(NRF_POWER_Type * p_reg, uint32_t mask)
906 {
907 p_reg->INTENSET = mask;
908 }
909
nrf_power_int_enable_check(NRF_POWER_Type const * p_reg,uint32_t mask)910 NRF_STATIC_INLINE uint32_t nrf_power_int_enable_check(NRF_POWER_Type const * p_reg, uint32_t mask)
911 {
912 return p_reg->INTENSET & mask;
913 }
914
nrf_power_int_enable_get(NRF_POWER_Type const * p_reg)915 NRF_STATIC_INLINE uint32_t nrf_power_int_enable_get(NRF_POWER_Type const * p_reg)
916 {
917 return p_reg->INTENSET;
918 }
919
nrf_power_int_disable(NRF_POWER_Type * p_reg,uint32_t mask)920 NRF_STATIC_INLINE void nrf_power_int_disable(NRF_POWER_Type * p_reg, uint32_t mask)
921 {
922 p_reg->INTENCLR = mask;
923 }
924
925 #if defined(DPPI_PRESENT)
nrf_power_subscribe_set(NRF_POWER_Type * p_reg,nrf_power_task_t task,uint8_t channel)926 NRF_STATIC_INLINE void nrf_power_subscribe_set(NRF_POWER_Type * p_reg,
927 nrf_power_task_t task,
928 uint8_t channel)
929 {
930 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
931 ((uint32_t)channel | POWER_SUBSCRIBE_CONSTLAT_EN_Msk);
932 }
933
nrf_power_subscribe_clear(NRF_POWER_Type * p_reg,nrf_power_task_t task)934 NRF_STATIC_INLINE void nrf_power_subscribe_clear(NRF_POWER_Type * p_reg, nrf_power_task_t task)
935 {
936 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
937 }
938
nrf_power_publish_set(NRF_POWER_Type * p_reg,nrf_power_event_t event,uint8_t channel)939 NRF_STATIC_INLINE void nrf_power_publish_set(NRF_POWER_Type * p_reg,
940 nrf_power_event_t event,
941 uint8_t channel)
942 {
943 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
944 ((uint32_t)channel | POWER_PUBLISH_SLEEPENTER_EN_Msk);
945 }
946
nrf_power_publish_clear(NRF_POWER_Type * p_reg,nrf_power_event_t event)947 NRF_STATIC_INLINE void nrf_power_publish_clear(NRF_POWER_Type * p_reg, nrf_power_event_t event)
948 {
949 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
950 }
951 #endif // defined(DPPI_PRESENT)
952
953 #if NRF_POWER_HAS_RESETREAS
nrf_power_resetreas_get(NRF_POWER_Type const * p_reg)954 NRF_STATIC_INLINE uint32_t nrf_power_resetreas_get(NRF_POWER_Type const * p_reg)
955 {
956 return p_reg->RESETREAS;
957 }
958
nrf_power_resetreas_clear(NRF_POWER_Type * p_reg,uint32_t mask)959 NRF_STATIC_INLINE void nrf_power_resetreas_clear(NRF_POWER_Type * p_reg, uint32_t mask)
960 {
961 p_reg->RESETREAS = mask;
962 }
963 #endif // NRF_POWER_HAS_RESETREAS
964
965 #if defined(POWER_POWERSTATUS_LTEMODEM_Msk)
nrf_power_powerstatus_get(NRF_POWER_Type const * p_reg)966 NRF_STATIC_INLINE bool nrf_power_powerstatus_get(NRF_POWER_Type const * p_reg)
967 {
968 return (p_reg->POWERSTATUS & POWER_POWERSTATUS_LTEMODEM_Msk) ==
969 (POWER_POWERSTATUS_LTEMODEM_ON << POWER_POWERSTATUS_LTEMODEM_Pos);
970 }
971 #endif // (POWER_POWERSTATUS_LTEMODEM_Msk)
972
973 #if defined(POWER_RAMSTATUS_RAMBLOCK0_Msk)
nrf_power_ramstatus_get(NRF_POWER_Type const * p_reg)974 NRF_STATIC_INLINE uint32_t nrf_power_ramstatus_get(NRF_POWER_Type const * p_reg)
975 {
976 return p_reg->RAMSTATUS;
977 }
978 #endif // defined(POWER_RAMSTATUS_RAMBLOCK0_Msk)
979
980 #if defined(POWER_SYSTEMOFF_SYSTEMOFF_Enter)
nrf_power_system_off(NRF_POWER_Type * p_reg)981 NRF_STATIC_INLINE void nrf_power_system_off(NRF_POWER_Type * p_reg)
982 {
983 p_reg->SYSTEMOFF = POWER_SYSTEMOFF_SYSTEMOFF_Enter;
984 __DSB();
985
986 /* Solution for simulated System OFF in debug mode */
987 while (true)
988 {
989 __WFE();
990 }
991 }
992 #endif // defined(POWER_SYSTEMOFF_SYSTEMOFF_Enter)
993
994 #if NRF_POWER_HAS_POFCON
nrf_power_pofcon_set(NRF_POWER_Type * p_reg,bool enable,nrf_power_pof_thr_t thr)995 NRF_STATIC_INLINE void nrf_power_pofcon_set(NRF_POWER_Type * p_reg,
996 bool enable,
997 nrf_power_pof_thr_t thr)
998 {
999 NRFX_ASSERT(thr == (thr & (POWER_POFCON_THRESHOLD_Msk >> POWER_POFCON_THRESHOLD_Pos)));
1000 #if NRF_POWER_HAS_POFCON_VDDH
1001 uint32_t pofcon = p_reg->POFCON;
1002 pofcon &= ~(POWER_POFCON_THRESHOLD_Msk | POWER_POFCON_POF_Msk);
1003 pofcon |=
1004 #else // NRF_POWER_HAS_POFCON_VDDH
1005 p_reg->POFCON =
1006 #endif
1007 (((uint32_t)thr) << POWER_POFCON_THRESHOLD_Pos) |
1008 (enable ?
1009 (POWER_POFCON_POF_Enabled << POWER_POFCON_POF_Pos)
1010 :
1011 (POWER_POFCON_POF_Disabled << POWER_POFCON_POF_Pos));
1012 #if NRF_POWER_HAS_POFCON_VDDH
1013 p_reg->POFCON = pofcon;
1014 #endif
1015 }
1016
nrf_power_pofcon_get(NRF_POWER_Type const * p_reg,bool * p_enabled)1017 NRF_STATIC_INLINE nrf_power_pof_thr_t nrf_power_pofcon_get(NRF_POWER_Type const * p_reg,
1018 bool * p_enabled)
1019 {
1020 uint32_t pofcon = p_reg->POFCON;
1021 if (NULL != p_enabled)
1022 {
1023 (*p_enabled) = ((pofcon & POWER_POFCON_POF_Msk) >> POWER_POFCON_POF_Pos)
1024 == POWER_POFCON_POF_Enabled;
1025 }
1026 return (nrf_power_pof_thr_t)((pofcon & POWER_POFCON_THRESHOLD_Msk) >>
1027 POWER_POFCON_THRESHOLD_Pos);
1028 }
1029 #endif // NRF_POWER_HAS_POFCON
1030
1031 #if NRF_POWER_HAS_POFCON_VDDH
nrf_power_pofcon_vddh_set(NRF_POWER_Type * p_reg,nrf_power_pof_thrvddh_t thr)1032 NRF_STATIC_INLINE void nrf_power_pofcon_vddh_set(NRF_POWER_Type * p_reg,
1033 nrf_power_pof_thrvddh_t thr)
1034 {
1035 NRFX_ASSERT(thr == (thr & (POWER_POFCON_THRESHOLDVDDH_Msk >> POWER_POFCON_THRESHOLDVDDH_Pos)));
1036 uint32_t pofcon = p_reg->POFCON;
1037 pofcon &= ~POWER_POFCON_THRESHOLDVDDH_Msk;
1038 pofcon |= (((uint32_t)thr) << POWER_POFCON_THRESHOLDVDDH_Pos);
1039 p_reg->POFCON = pofcon;
1040 }
1041
nrf_power_pofcon_vddh_get(NRF_POWER_Type const * p_reg)1042 NRF_STATIC_INLINE nrf_power_pof_thrvddh_t nrf_power_pofcon_vddh_get(NRF_POWER_Type const * p_reg)
1043 {
1044 return (nrf_power_pof_thrvddh_t)((p_reg->POFCON & POWER_POFCON_THRESHOLDVDDH_Msk) >>
1045 POWER_POFCON_THRESHOLDVDDH_Pos);
1046 }
1047 #endif // NRF_POWER_HAS_POFCON_VDDH
1048
nrf_power_gpregret_set(NRF_POWER_Type * p_reg,uint8_t val)1049 NRF_STATIC_INLINE void nrf_power_gpregret_set(NRF_POWER_Type * p_reg, uint8_t val)
1050 {
1051 volatile uint32_t * p_gpregret;
1052 if (sizeof(p_reg->GPREGRET) > sizeof(uint32_t))
1053 {
1054 p_gpregret = &((volatile uint32_t *)p_reg->GPREGRET)[0];
1055 }
1056 else
1057 {
1058 p_gpregret = &((volatile uint32_t *)&p_reg->GPREGRET)[0];
1059 }
1060 *p_gpregret = val;
1061 }
1062
nrf_power_gpregret_get(NRF_POWER_Type const * p_reg)1063 NRF_STATIC_INLINE uint8_t nrf_power_gpregret_get(NRF_POWER_Type const * p_reg)
1064 {
1065 volatile uint32_t * p_gpregret;
1066 if (sizeof(p_reg->GPREGRET) > sizeof(uint32_t))
1067 {
1068 p_gpregret = &((volatile uint32_t *)p_reg->GPREGRET)[0];
1069 }
1070 else
1071 {
1072 p_gpregret = &((volatile uint32_t *)&p_reg->GPREGRET)[0];
1073 }
1074 return *p_gpregret;
1075 }
1076
nrf_power_gpregret_ext_set(NRF_POWER_Type * p_reg,uint8_t reg_num,uint8_t val)1077 NRF_STATIC_INLINE void nrf_power_gpregret_ext_set(NRF_POWER_Type * p_reg,
1078 uint8_t reg_num,
1079 uint8_t val)
1080 {
1081 #if defined(NRF91_SERIES) || defined(NRF5340_XXAA_APPLICATION) || defined(NRF5340_XXAA_NETWORK)
1082 p_reg->GPREGRET[reg_num] = val;
1083 #else
1084 NRFX_ASSERT(reg_num < 1);
1085 p_reg->GPREGRET = val;
1086 #endif
1087 }
1088
nrf_power_gpregret_ext_get(NRF_POWER_Type const * p_reg,uint8_t reg_num)1089 NRF_STATIC_INLINE uint8_t nrf_power_gpregret_ext_get(NRF_POWER_Type const * p_reg, uint8_t reg_num)
1090 {
1091 #if defined(NRF91_SERIES) || defined(NRF5340_XXAA_APPLICATION) || defined(NRF5340_XXAA_NETWORK)
1092 return p_reg->GPREGRET[reg_num];
1093 #else
1094 NRFX_ASSERT(reg_num < 1);
1095 return p_reg->GPREGRET;
1096 #endif
1097 }
1098
1099 #if defined(POWER_GPREGRET2_GPREGRET_Msk)
nrf_power_gpregret2_set(NRF_POWER_Type * p_reg,uint8_t val)1100 NRF_STATIC_INLINE void nrf_power_gpregret2_set(NRF_POWER_Type * p_reg, uint8_t val)
1101 {
1102 p_reg->GPREGRET2 = val;
1103 }
1104
nrf_power_gpregret2_get(NRF_POWER_Type const * p_reg)1105 NRF_STATIC_INLINE uint8_t nrf_power_gpregret2_get(NRF_POWER_Type const * p_reg)
1106 {
1107 return p_reg->GPREGRET2;
1108 }
1109 #endif
1110
1111 #if NRF_POWER_HAS_DCDCEN
nrf_power_dcdcen_set(NRF_POWER_Type * p_reg,bool enable)1112 NRF_STATIC_INLINE void nrf_power_dcdcen_set(NRF_POWER_Type * p_reg, bool enable)
1113 {
1114 p_reg->DCDCEN = (enable ? POWER_DCDCEN_DCDCEN_Enabled : POWER_DCDCEN_DCDCEN_Disabled) <<
1115 POWER_DCDCEN_DCDCEN_Pos;
1116 }
1117
nrf_power_dcdcen_get(NRF_POWER_Type const * p_reg)1118 NRF_STATIC_INLINE bool nrf_power_dcdcen_get(NRF_POWER_Type const * p_reg)
1119 {
1120 return (p_reg->DCDCEN & POWER_DCDCEN_DCDCEN_Msk)
1121 ==
1122 (POWER_DCDCEN_DCDCEN_Enabled << POWER_DCDCEN_DCDCEN_Pos);
1123 }
1124 #endif // NRF_POWER_HAS_DCDCEN
1125
1126 #if defined(POWER_RAM_POWER_S0POWER_Msk)
nrf_power_rampower_mask_on(NRF_POWER_Type * p_reg,uint8_t block,uint32_t section_mask)1127 NRF_STATIC_INLINE void nrf_power_rampower_mask_on(NRF_POWER_Type * p_reg,
1128 uint8_t block,
1129 uint32_t section_mask)
1130 {
1131 p_reg->RAM[block].POWERSET = section_mask;
1132 }
1133
nrf_power_rampower_mask_off(NRF_POWER_Type * p_reg,uint8_t block,uint32_t section_mask)1134 NRF_STATIC_INLINE void nrf_power_rampower_mask_off(NRF_POWER_Type * p_reg,
1135 uint8_t block,
1136 uint32_t section_mask)
1137 {
1138 p_reg->RAM[block].POWERCLR = section_mask;
1139 }
1140
nrf_power_rampower_mask_get(NRF_POWER_Type const * p_reg,uint8_t block)1141 NRF_STATIC_INLINE uint32_t nrf_power_rampower_mask_get(NRF_POWER_Type const * p_reg, uint8_t block)
1142 {
1143 return p_reg->RAM[block].POWER;
1144 }
1145 #endif // defined(POWER_RAM_POWER_S0POWER_Msk)
1146
1147 #if NRF_POWER_HAS_DCDCEN_VDDH
nrf_power_dcdcen_vddh_set(NRF_POWER_Type * p_reg,bool enable)1148 NRF_STATIC_INLINE void nrf_power_dcdcen_vddh_set(NRF_POWER_Type * p_reg, bool enable)
1149 {
1150 if (nrf52_errata_197())
1151 {
1152 // Workaround for anomaly 197 "POWER: DCDC of REG0 not functional".
1153 *(volatile uint32_t *)0x40000638ul = 1ul;
1154 }
1155 p_reg->DCDCEN0 = (enable ? POWER_DCDCEN0_DCDCEN_Enabled : POWER_DCDCEN0_DCDCEN_Disabled) <<
1156 POWER_DCDCEN0_DCDCEN_Pos;
1157 }
1158
nrf_power_dcdcen_vddh_get(NRF_POWER_Type const * p_reg)1159 NRF_STATIC_INLINE bool nrf_power_dcdcen_vddh_get(NRF_POWER_Type const * p_reg)
1160 {
1161 return (p_reg->DCDCEN0 & POWER_DCDCEN0_DCDCEN_Msk)
1162 ==
1163 (POWER_DCDCEN0_DCDCEN_Enabled << POWER_DCDCEN0_DCDCEN_Pos);
1164 }
1165 #endif // NRF_POWER_HAS_DCDCEN_VDDH
1166
1167 #if NRF_POWER_HAS_MAINREGSTATUS
1168 NRF_STATIC_INLINE
nrf_power_mainregstatus_get(NRF_POWER_Type const * p_reg)1169 nrf_power_mainregstatus_t nrf_power_mainregstatus_get(NRF_POWER_Type const * p_reg)
1170 {
1171 return (nrf_power_mainregstatus_t)(((p_reg->MAINREGSTATUS) &
1172 POWER_MAINREGSTATUS_MAINREGSTATUS_Msk) >>
1173 POWER_MAINREGSTATUS_MAINREGSTATUS_Pos);
1174 }
1175 #endif // NRF_POWER_HAS_MAINREGSTATUS
1176
1177 #if NRF_POWER_HAS_USBREG
nrf_power_usbregstatus_get(NRF_POWER_Type const * p_reg)1178 NRF_STATIC_INLINE uint32_t nrf_power_usbregstatus_get(NRF_POWER_Type const * p_reg)
1179 {
1180 return p_reg->USBREGSTATUS;
1181 }
1182
nrf_power_usbregstatus_vbusdet_get(NRF_POWER_Type const * p_reg)1183 NRF_STATIC_INLINE bool nrf_power_usbregstatus_vbusdet_get(NRF_POWER_Type const * p_reg)
1184 {
1185 return (nrf_power_usbregstatus_get(p_reg) & NRF_POWER_USBREGSTATUS_VBUSDETECT_MASK) != 0;
1186 }
1187
nrf_power_usbregstatus_outrdy_get(NRF_POWER_Type const * p_reg)1188 NRF_STATIC_INLINE bool nrf_power_usbregstatus_outrdy_get(NRF_POWER_Type const * p_reg)
1189 {
1190 return (nrf_power_usbregstatus_get(p_reg) & NRF_POWER_USBREGSTATUS_OUTPUTRDY_MASK) != 0;
1191 }
1192 #endif // NRF_POWER_HAS_USBREG
1193
1194 #endif // NRF_DECLARE_ONLY
1195
1196 /** @} */
1197
1198 #ifdef __cplusplus
1199 }
1200 #endif
1201
1202 #endif // NRF_POWER_H__
1203