1 /*
2 * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef NRF_QSPI_H__
33 #define NRF_QSPI_H__
34
35 #include <nrfx.h>
36 #include <nrf_erratas.h>
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 /**
43 * @defgroup nrf_qspi_hal QSPI HAL
44 * @{
45 * @ingroup nrf_qspi
46 * @brief Hardware access layer for managing the QSPI peripheral.
47 */
48
49 #if defined(QSPI_XIPEN_XIPEN_Msk) || defined(__NRFX_DOXYGEN__)
50 /** @brief Symbol indicating whether XIP can be explicitly enabled or disabled via XIPEN register. */
51 #define NRF_QSPI_HAS_XIPEN 1
52 #else
53 #define NRF_QSPI_HAS_XIPEN 0
54 #endif
55
56 #if defined(QSPI_XIP_ENC_ENABLE_ENABLE_Msk) || defined(__NRFX_DOXYGEN__)
57 /** @brief Symbol indicating whether encryption for XIP is present. */
58 #define NRF_QSPI_HAS_XIP_ENC 1
59 #else
60 #define NRF_QSPI_HAS_XIP_ENC 0
61 #endif
62
63 #if defined(QSPI_DMA_ENC_ENABLE_ENABLE_Msk) || defined(__NRFX_DOXYGEN__)
64 /** @brief Symbol indicating whether encryption for EasyDMA is present. */
65 #define NRF_QSPI_HAS_DMA_ENC 1
66 #else
67 #define NRF_QSPI_HAS_DMA_ENC 0
68 #endif
69
70 #if defined(QSPI_IFCONFIG1_SPIMODE_MODE3) || defined(__NRFX_DOXYGEN__)
71 /** @brief Symbol indicating whether support for QSPI mode 1 is present. */
72 #define NRF_QSPI_HAS_MODE_1 1
73 #else
74 #define NRF_QSPI_HAS_MODE_1 0
75 #endif
76
77 #if defined(NRF53_SERIES) || defined(__NRFX_DOXYGEN__)
78 /** @brief Value representing QSPI base clock frequency. */
79 #define NRF_QSPI_BASE_CLOCK_FREQ 96000000uL
80 #else
81 #define NRF_QSPI_BASE_CLOCK_FREQ 32000000uL
82 #endif
83
84 /**
85 * @brief This value can be used as a parameter for the @ref nrf_qspi_pins_set
86 * function to specify that a given QSPI signal (SCK, CSN, IO0, IO1, IO2, or IO3)
87 * will not be connected to a physical pin.
88 */
89 #define NRF_QSPI_PIN_NOT_CONNECTED 0xFF
90
91 /** @brief Macro for setting proper values to pin registers. */
92 #define NRF_QSPI_PIN_VAL(pin) (pin) == NRF_QSPI_PIN_NOT_CONNECTED ? 0xFFFFFFFF : (pin)
93
94
95 /** @brief QSPI tasks. */
96 typedef enum
97 {
98 NRF_QSPI_TASK_ACTIVATE = offsetof(NRF_QSPI_Type, TASKS_ACTIVATE), /**< Activate the QSPI interface. */
99 NRF_QSPI_TASK_READSTART = offsetof(NRF_QSPI_Type, TASKS_READSTART), /**< Start transfer from external flash memory to internal RAM. */
100 NRF_QSPI_TASK_WRITESTART = offsetof(NRF_QSPI_Type, TASKS_WRITESTART), /**< Start transfer from internal RAM to external flash memory. */
101 NRF_QSPI_TASK_ERASESTART = offsetof(NRF_QSPI_Type, TASKS_ERASESTART), /**< Start external flash memory erase operation. */
102 NRF_QSPI_TASK_DEACTIVATE = offsetof(NRF_QSPI_Type, TASKS_DEACTIVATE), /**< Deactivate the QSPI interface. */
103 } nrf_qspi_task_t;
104
105 /** @brief QSPI events. */
106 typedef enum
107 {
108 NRF_QSPI_EVENT_READY = offsetof(NRF_QSPI_Type, EVENTS_READY) /**< QSPI peripheral is ready after it executes any task. */
109 } nrf_qspi_event_t;
110
111 /** @brief QSPI interrupts. */
112 typedef enum
113 {
114 NRF_QSPI_INT_READY_MASK = QSPI_INTENSET_READY_Msk /**< Interrupt on READY event. */
115 } nrf_qspi_int_mask_t;
116
117 /** @brief QSPI base clock frequency divider values. */
118 typedef enum
119 {
120 NRF_QSPI_FREQ_DIV1, /**< Divide by 1. */
121 NRF_QSPI_FREQ_DIV2, /**< Divide by 2. */
122 NRF_QSPI_FREQ_DIV3, /**< Divide by 3. */
123 NRF_QSPI_FREQ_DIV4, /**< Divide by 4. */
124 NRF_QSPI_FREQ_DIV5, /**< Divide by 5. */
125 NRF_QSPI_FREQ_DIV6, /**< Divide by 6. */
126 NRF_QSPI_FREQ_DIV7, /**< Divide by 7. */
127 NRF_QSPI_FREQ_DIV8, /**< Divide by 8. */
128 NRF_QSPI_FREQ_DIV9, /**< Divide by 9. */
129 NRF_QSPI_FREQ_DIV10, /**< Divide by 10. */
130 NRF_QSPI_FREQ_DIV11, /**< Divide by 11. */
131 NRF_QSPI_FREQ_DIV12, /**< Divide by 12. */
132 NRF_QSPI_FREQ_DIV13, /**< Divide by 13. */
133 NRF_QSPI_FREQ_DIV14, /**< Divide by 14. */
134 NRF_QSPI_FREQ_DIV15, /**< Divide by 15. */
135 NRF_QSPI_FREQ_DIV16, /**< Divide by 16. */
136 } nrf_qspi_frequency_t;
137
138 #if defined(NRF52_SERIES)
139 /** Symbols translation for backward compatibility. */
140 #define NRF_QSPI_FREQ_32MDIV1 NRF_QSPI_FREQ_DIV1
141 #define NRF_QSPI_FREQ_32MDIV2 NRF_QSPI_FREQ_DIV2
142 #define NRF_QSPI_FREQ_32MDIV3 NRF_QSPI_FREQ_DIV3
143 #define NRF_QSPI_FREQ_32MDIV4 NRF_QSPI_FREQ_DIV4
144 #define NRF_QSPI_FREQ_32MDIV5 NRF_QSPI_FREQ_DIV5
145 #define NRF_QSPI_FREQ_32MDIV6 NRF_QSPI_FREQ_DIV6
146 #define NRF_QSPI_FREQ_32MDIV7 NRF_QSPI_FREQ_DIV7
147 #define NRF_QSPI_FREQ_32MDIV8 NRF_QSPI_FREQ_DIV8
148 #define NRF_QSPI_FREQ_32MDIV9 NRF_QSPI_FREQ_DIV9
149 #define NRF_QSPI_FREQ_32MDIV10 NRF_QSPI_FREQ_DIV10
150 #define NRF_QSPI_FREQ_32MDIV11 NRF_QSPI_FREQ_DIV11
151 #define NRF_QSPI_FREQ_32MDIV12 NRF_QSPI_FREQ_DIV12
152 #define NRF_QSPI_FREQ_32MDIV13 NRF_QSPI_FREQ_DIV13
153 #define NRF_QSPI_FREQ_32MDIV14 NRF_QSPI_FREQ_DIV14
154 #define NRF_QSPI_FREQ_32MDIV15 NRF_QSPI_FREQ_DIV15
155 #define NRF_QSPI_FREQ_32MDIV16 NRF_QSPI_FREQ_DIV16
156 #endif
157
158 /** @brief Interface configuration for a read operation. */
159 typedef enum
160 {
161 NRF_QSPI_READOC_FASTREAD = QSPI_IFCONFIG0_READOC_FASTREAD, /**< Single data line SPI. FAST_READ (opcode 0x0B). */
162 NRF_QSPI_READOC_READ2O = QSPI_IFCONFIG0_READOC_READ2O, /**< Dual data line SPI. READ2O (opcode 0x3B). */
163 NRF_QSPI_READOC_READ2IO = QSPI_IFCONFIG0_READOC_READ2IO, /**< Dual data line SPI. READ2IO (opcode 0xBB). */
164 NRF_QSPI_READOC_READ4O = QSPI_IFCONFIG0_READOC_READ4O, /**< Quad data line SPI. READ4O (opcode 0x6B). */
165 NRF_QSPI_READOC_READ4IO = QSPI_IFCONFIG0_READOC_READ4IO /**< Quad data line SPI. READ4IO (opcode 0xEB). */
166 } nrf_qspi_readoc_t;
167
168 /** @brief Interface configuration for a write operation. */
169 typedef enum
170 {
171 NRF_QSPI_WRITEOC_PP = QSPI_IFCONFIG0_WRITEOC_PP, /**< Single data line SPI. PP (opcode 0x02). */
172 NRF_QSPI_WRITEOC_PP2O = QSPI_IFCONFIG0_WRITEOC_PP2O, /**< Dual data line SPI. PP2O (opcode 0xA2). */
173 NRF_QSPI_WRITEOC_PP4O = QSPI_IFCONFIG0_WRITEOC_PP4O, /**< Quad data line SPI. PP4O (opcode 0x32). */
174 NRF_QSPI_WRITEOC_PP4IO = QSPI_IFCONFIG0_WRITEOC_PP4IO, /**< Quad data line SPI. READ4O (opcode 0x38). */
175 } nrf_qspi_writeoc_t;
176
177 /** @brief Interface configuration for addressing mode. */
178 typedef enum
179 {
180 NRF_QSPI_ADDRMODE_24BIT = QSPI_IFCONFIG0_ADDRMODE_24BIT, /**< 24-bit addressing. */
181 NRF_QSPI_ADDRMODE_32BIT = QSPI_IFCONFIG0_ADDRMODE_32BIT /**< 32-bit addressing. */
182 } nrf_qspi_addrmode_t;
183
184 /** @brief QSPI SPI mode. Polarization and phase configuration. */
185 typedef enum
186 {
187 NRF_QSPI_MODE_0 = QSPI_IFCONFIG1_SPIMODE_MODE0, /**< Mode 0 (CPOL=0, CPHA=0). */
188 #if NRF_QSPI_HAS_MODE_1
189 NRF_QSPI_MODE_1 = QSPI_IFCONFIG1_SPIMODE_MODE3 /**< Mode 1 (CPOL=1, CPHA=1). */
190 #endif
191 } nrf_qspi_spi_mode_t;
192
193 /** @brief Addressing configuration mode. */
194 typedef enum
195 {
196 NRF_QSPI_ADDRCONF_MODE_NOINSTR = QSPI_ADDRCONF_MODE_NoInstr, /**< Do not send any instruction. */
197 NRF_QSPI_ADDRCONF_MODE_OPCODE = QSPI_ADDRCONF_MODE_Opcode, /**< Send opcode. */
198 NRF_QSPI_ADDRCONF_MODE_OPBYTE0 = QSPI_ADDRCONF_MODE_OpByte0, /**< Send opcode, byte0. */
199 NRF_QSPI_ADDRCONF_MODE_ALL = QSPI_ADDRCONF_MODE_All /**< Send opcode, byte0, byte1. */
200 } nrf_qspi_addrconfig_mode_t;
201
202 /** @brief Erasing data length. */
203 typedef enum
204 {
205 NRF_QSPI_ERASE_LEN_4KB = QSPI_ERASE_LEN_LEN_4KB, /**< Erase 4 kB block (flash command 0x20). */
206 NRF_QSPI_ERASE_LEN_64KB = QSPI_ERASE_LEN_LEN_64KB, /**< Erase 64 kB block (flash command 0xD8). */
207 NRF_QSPI_ERASE_LEN_ALL = QSPI_ERASE_LEN_LEN_All /**< Erase all (flash command 0xC7). */
208 } nrf_qspi_erase_len_t;
209
210 /** @brief Custom instruction length. */
211 typedef enum
212 {
213 NRF_QSPI_CINSTR_LEN_1B = QSPI_CINSTRCONF_LENGTH_1B, /**< Send opcode only. */
214 NRF_QSPI_CINSTR_LEN_2B = QSPI_CINSTRCONF_LENGTH_2B, /**< Send opcode, CINSTRDAT0.BYTE0. */
215 NRF_QSPI_CINSTR_LEN_3B = QSPI_CINSTRCONF_LENGTH_3B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE1. */
216 NRF_QSPI_CINSTR_LEN_4B = QSPI_CINSTRCONF_LENGTH_4B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE2. */
217 NRF_QSPI_CINSTR_LEN_5B = QSPI_CINSTRCONF_LENGTH_5B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE3. */
218 NRF_QSPI_CINSTR_LEN_6B = QSPI_CINSTRCONF_LENGTH_6B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE4. */
219 NRF_QSPI_CINSTR_LEN_7B = QSPI_CINSTRCONF_LENGTH_7B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE5. */
220 NRF_QSPI_CINSTR_LEN_8B = QSPI_CINSTRCONF_LENGTH_8B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE6. */
221 NRF_QSPI_CINSTR_LEN_9B = QSPI_CINSTRCONF_LENGTH_9B /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE7. */
222 } nrf_qspi_cinstr_len_t;
223
224 /** @brief Pin configuration. */
225 typedef struct
226 {
227 uint8_t sck_pin; /**< SCK pin number. */
228 uint8_t csn_pin; /**< Chip select pin number. */
229 uint8_t io0_pin; /**< IO0/MOSI pin number. */
230 uint8_t io1_pin; /**< IO1/MISO pin number. */
231 uint8_t io2_pin; /**< IO2 pin number (optional).
232 * Set to @ref NRF_QSPI_PIN_NOT_CONNECTED if this signal is not needed.
233 */
234 uint8_t io3_pin; /**< IO3 pin number (optional).
235 * Set to @ref NRF_QSPI_PIN_NOT_CONNECTED if this signal is not needed.
236 */
237 } nrf_qspi_pins_t;
238
239 /** @brief Custom instruction configuration. */
240 typedef struct
241 {
242 uint8_t opcode; /**< Opcode used in custom instruction transmission. */
243 nrf_qspi_cinstr_len_t length; /**< Length of the custom instruction data. */
244 bool io2_level; /**< I/O line level during transmission. */
245 bool io3_level; /**< I/O line level during transmission. */
246 bool wipwait; /**< Wait if a Wait in Progress bit is set in the memory status byte. */
247 bool wren; /**< Send write enable before instruction. */
248 } nrf_qspi_cinstr_conf_t;
249
250 /** @brief Addressing mode register configuration. See @ref nrf_qspi_addrconfig_set */
251 typedef struct
252 {
253 uint8_t opcode; /**< Opcode used to enter the proper addressing mode. */
254 uint8_t byte0; /**< Byte following the opcode. */
255 uint8_t byte1; /**< Byte following byte0. */
256 nrf_qspi_addrconfig_mode_t mode; /**< Extended addresing mode. */
257 bool wipwait; /**< Enable or disable waiting for complete operation execution. */
258 bool wren; /**< Send write enable before instruction. */
259 } nrf_qspi_addrconfig_conf_t;
260
261 /** @brief Structure with QSPI protocol interface configuration. */
262 typedef struct
263 {
264 nrf_qspi_readoc_t readoc; /**< Read operation code. */
265 nrf_qspi_writeoc_t writeoc; /**< Write operation code. */
266 nrf_qspi_addrmode_t addrmode; /**< Addresing mode (24-bit or 32-bit). */
267 bool dpmconfig; /**< Enable the Deep Power-down Mode (DPM) feature. */
268 } nrf_qspi_prot_conf_t;
269
270 /** @brief QSPI physical interface configuration. */
271 typedef struct
272 {
273 uint8_t sck_delay; /**< tSHSL, tWHSL, and tSHWL in number of 16 MHz periods (62.5ns). */
274 bool dpmen; /**< Enable the DPM feature. */
275 nrf_qspi_spi_mode_t spi_mode; /**< SPI phase and polarization. */
276 nrf_qspi_frequency_t sck_freq; /**< SCK frequency given as QSPI base clock frequency divider.
277 * To calculate @p sck_freq value corresponding to chosen frequency,
278 * use the following equation:
279 *
280 * sck_freq = (NRF_QSPI_BASE_CLOCK_FREQ / frequency) - 1
281 *
282 * @note Achievable frequencies are determined by available
283 * divider values and QSPI base clock frequency.
284 */
285 } nrf_qspi_phy_conf_t;
286
287
288 #if NRF_QSPI_HAS_XIP_ENC || NRF_QSPI_HAS_DMA_ENC
289 /** @brief QSPI encryption settings for XIP and DMA transfers. */
290 typedef struct
291 {
292 uint32_t key[4]; /**< AES 128-bit key, stored on 4 32-bit words. */
293 uint32_t nonce[3]; /**< AES 96-bit nonce, stored on 3 32-bit words. */
294 } nrf_qspi_encryption_t;
295 #endif
296
297 /**
298 * @brief Function for activating the specified QSPI task.
299 *
300 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
301 * @param[in] task Task to be activated.
302 */
303 NRF_STATIC_INLINE void nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg, nrf_qspi_task_t task);
304
305 /**
306 * @brief Function for getting the address of the specified QSPI task register.
307 *
308 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
309 * @param[in] task QSPI task.
310 *
311 * @return Address of the specified task register.
312 */
313 NRF_STATIC_INLINE uint32_t nrf_qspi_task_address_get(NRF_QSPI_Type const * p_reg,
314 nrf_qspi_task_t task);
315
316 /**
317 * @brief Function for clearing the specified QSPI event.
318 *
319 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
320 * @param[in] event Event to be cleared.
321 */
322 NRF_STATIC_INLINE void nrf_qspi_event_clear(NRF_QSPI_Type * p_reg, nrf_qspi_event_t event);
323
324 /**
325 * @brief Function for retrieving the state of the QSPI event.
326 *
327 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
328 * @param[in] event Event to be checked.
329 *
330 * @retval true The event has been generated.
331 * @retval false The event has not been generated.
332 */
333 NRF_STATIC_INLINE bool nrf_qspi_event_check(NRF_QSPI_Type const * p_reg, nrf_qspi_event_t event);
334
335 /**
336 * @brief Function for getting the address of the specified QSPI event register.
337 *
338 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
339 * @param[in] event The specified event.
340 *
341 * @return Address of the specified event register.
342 */
343 NRF_STATIC_INLINE uint32_t nrf_qspi_event_address_get(NRF_QSPI_Type const * p_reg,
344 nrf_qspi_event_t event);
345
346 /**
347 * @brief Function for enabling specified interrupts.
348 *
349 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
350 * @param[in] mask Mask of interrupts to be enabled.
351 */
352 NRF_STATIC_INLINE void nrf_qspi_int_enable(NRF_QSPI_Type * p_reg, uint32_t mask);
353
354 /**
355 * @brief Function for disabling specified interrupts.
356 *
357 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
358 * @param[in] mask Mask of interrupts to be disabled.
359 */
360 NRF_STATIC_INLINE void nrf_qspi_int_disable(NRF_QSPI_Type * p_reg, uint32_t mask);
361
362 /**
363 * @brief Function for checking if the specified interrupts are enabled.
364 *
365 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
366 * @param[in] mask Mask of interrupts to be checked.
367 *
368 * @return Mask of enabled interrupts.
369 */
370 NRF_STATIC_INLINE uint32_t nrf_qspi_int_enable_check(NRF_QSPI_Type const * p_reg, uint32_t mask);
371
372 /**
373 * @brief Function for enabling the QSPI peripheral.
374 *
375 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
376 */
377 NRF_STATIC_INLINE void nrf_qspi_enable(NRF_QSPI_Type * p_reg);
378
379 /**
380 * @brief Function for disabling the QSPI peripheral.
381 *
382 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
383 */
384 NRF_STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type * p_reg);
385
386 /**
387 * @brief Function for configuring QSPI pins.
388 *
389 * If a given signal is not needed, pass the @ref NRF_QSPI_PIN_NOT_CONNECTED
390 * value instead of its pin number.
391 *
392 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
393 * @param[in] p_pins Pointer to the pins configuration structure. See @ref nrf_qspi_pins_t.
394 */
395 NRF_STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type * p_reg,
396 nrf_qspi_pins_t const * p_pins);
397
398 /**
399 * @brief Function for setting the QSPI XIPOFFSET register.
400 *
401 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
402 * @param[in] xip_offset Address offset in the external memory for Execute in Place operation.
403 */
404 NRF_STATIC_INLINE void nrf_qspi_xip_offset_set(NRF_QSPI_Type * p_reg,
405 uint32_t xip_offset);
406
407 /**
408 * @brief Function for setting the QSPI IFCONFIG0 register.
409 *
410 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
411 * @param[in] p_config Pointer to the QSPI protocol interface configuration structure.
412 * See @ref nrf_qspi_prot_conf_t.
413 */
414 NRF_STATIC_INLINE void nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg,
415 nrf_qspi_prot_conf_t const * p_config);
416
417 /**
418 * @brief Function for setting the QSPI IFCONFIG1 register.
419 *
420 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
421 * @param[in] p_config Pointer to the QSPI physical interface configuration structure.
422 * See @ref nrf_qspi_phy_conf_t.
423 */
424 NRF_STATIC_INLINE void nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg,
425 nrf_qspi_phy_conf_t const * p_config);
426
427 /**
428 * @brief Function for setting the QSPI ADDRCONF register.
429 *
430 * This function must be executed before sending task NRF_QSPI_TASK_ACTIVATE. Data stored in the structure
431 * is sent during the start of the peripheral. Remember that the reset instruction can set
432 * addressing mode to default in the memory device. If memory reset is necessary before configuring
433 * the addressing mode, use custom instruction feature instead of this function.
434 * Case with reset: Enable the peripheral without setting ADDRCONF register, send reset instructions
435 * using a custom instruction feature (reset enable and then reset), set proper addressing mode
436 * using the custom instruction feature.
437 *
438 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
439 * @param[in] p_config Pointer to the addressing mode configuration structure.
440 * See @ref nrf_qspi_addrconfig_conf_t.
441 */
442 NRF_STATIC_INLINE void nrf_qspi_addrconfig_set(NRF_QSPI_Type * p_reg,
443 nrf_qspi_addrconfig_conf_t const * p_config);
444
445 /**
446 * @brief Function for setting write data into the peripheral register (without starting the process).
447 *
448 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
449 * @param[in] p_buffer Pointer to the writing buffer.
450 * @param[in] length Lenght of the writing data.
451 * @param[in] dest_addr Address in memory to write to.
452 */
453 NRF_STATIC_INLINE void nrf_qspi_write_buffer_set(NRF_QSPI_Type * p_reg,
454 void const * p_buffer,
455 uint32_t length,
456 uint32_t dest_addr);
457
458 /**
459 * @brief Function for setting read data into the peripheral register (without starting the process).
460 *
461 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
462 * @param[out] p_buffer Pointer to the reading buffer.
463 * @param[in] length Length of the read data.
464 * @param[in] src_addr Address in memory to read from.
465 */
466 NRF_STATIC_INLINE void nrf_qspi_read_buffer_set(NRF_QSPI_Type * p_reg,
467 void * p_buffer,
468 uint32_t length,
469 uint32_t src_addr);
470
471 /**
472 * @brief Function for setting erase data into the peripheral register (without starting the process).
473 *
474 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
475 * @param[in] erase_addr Start address to erase. Address must have padding set to 4 bytes.
476 * @param[in] len Size of erasing area.
477 */
478 NRF_STATIC_INLINE void nrf_qspi_erase_ptr_set(NRF_QSPI_Type * p_reg,
479 uint32_t erase_addr,
480 nrf_qspi_erase_len_t len);
481
482 /**
483 * @brief Function for getting the peripheral status register.
484 *
485 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
486 *
487 * @return Peripheral status register.
488 */
489 NRF_STATIC_INLINE uint32_t nrf_qspi_status_reg_get(NRF_QSPI_Type const * p_reg);
490
491 /**
492 * @brief Function for getting the device status register stored in the peripheral status register.
493 *
494 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
495 *
496 * @return Device status register (lower byte).
497 */
498 NRF_STATIC_INLINE uint8_t nrf_qspi_sreg_get(NRF_QSPI_Type const * p_reg);
499
500 /**
501 * @brief Function for checking if the peripheral is busy or not.
502 *
503 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
504 *
505 * @retval true The QSPI is busy.
506 * @retval false The QSPI is ready.
507 */
508 NRF_STATIC_INLINE bool nrf_qspi_busy_check(NRF_QSPI_Type const * p_reg);
509
510 /**
511 * @brief Function for setting registers sending with custom instruction transmission.
512 *
513 * This function can be ommited when using NRF_QSPI_CINSTR_LEN_1B as the length argument
514 * (sending only opcode without data).
515 *
516 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
517 * @param[in] length Length of the custom instruction data.
518 * @param[in] p_tx_data Pointer to the data to send with the custom instruction.
519 */
520 NRF_STATIC_INLINE void nrf_qspi_cinstrdata_set(NRF_QSPI_Type * p_reg,
521 nrf_qspi_cinstr_len_t length,
522 void const * p_tx_data);
523
524 /**
525 * @brief Function for getting data from register after custom instruction transmission.
526 *
527 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
528 * @param[in] length Length of the custom instruction data.
529 * @param[in] p_rx_data Pointer to the reading buffer.
530 */
531 NRF_STATIC_INLINE void nrf_qspi_cinstrdata_get(NRF_QSPI_Type const * p_reg,
532 nrf_qspi_cinstr_len_t length,
533 void * p_rx_data);
534
535 /**
536 * @brief Function for sending custom instruction to external memory.
537 *
538 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
539 * @param[in] p_config Pointer to the custom instruction configuration structure.
540 * See @ref nrf_qspi_cinstr_conf_t.
541 */
542 NRF_STATIC_INLINE void nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type * p_reg,
543 nrf_qspi_cinstr_conf_t const * p_config);
544
545 /**
546 * @brief Function for starting a custom instruction long transfer.
547 *
548 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
549 * @param[in] p_config Pointer to the custom instruction configuration structure.
550 * See @ref nrf_qspi_cinstr_conf_t.
551 */
552 NRF_STATIC_INLINE void nrf_qspi_cinstr_long_transfer_start(NRF_QSPI_Type * p_reg,
553 nrf_qspi_cinstr_conf_t const * p_config);
554
555 /**
556 * @brief Function for checking whether a custom instruction long transfer is ongoing.
557 *
558 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
559 *
560 * @retval true Custom instruction long transfer is ongoing.
561 * @retval false Custom instruction long transfer is not ongoing.
562 */
563 NRF_STATIC_INLINE bool nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI_Type const * p_reg);
564
565 /**
566 * @brief Function for continuing a custom instruction long transfer.
567 *
568 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
569 * @param[in] length Length of the custom instruction data.
570 * @param[in] finalize True if the custom instruction long transfer is to be finalized.
571 * False if the custom instruction long transfer is to be continued.
572 */
573 NRF_STATIC_INLINE void nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI_Type * p_reg,
574 nrf_qspi_cinstr_len_t length,
575 bool finalize);
576
577 #if NRF_QSPI_HAS_XIPEN
578 /**
579 * @brief Function for enabling or disabling Execute in Place (XIP) operation.
580 *
581 * @note XIP can be enabled after reset. See Product Specification.
582 *
583 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
584 * @param[in] enable True if XIP is to be enabled, false otherwise.
585 */
586 NRF_STATIC_INLINE void nrf_qspi_xip_set(NRF_QSPI_Type * p_reg, bool enable);
587 #endif
588
589 #if NRF_QSPI_HAS_XIP_ENC
590 /**
591 * @brief Function for configuring the XIP encryption.
592 *
593 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
594 * @param[in] p_cfg Pointer to encryption configuration structure.
595 */
596 NRF_STATIC_INLINE void nrf_qspi_xip_encryption_configure(NRF_QSPI_Type * p_reg,
597 nrf_qspi_encryption_t const * p_cfg);
598
599 /**
600 * @brief Function for enabling or disabling the XIP encryption.
601 *
602 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
603 * @param[in] enable True if XIP encryption is to be enabled, false otherwise.
604 */
605 NRF_STATIC_INLINE void nrf_qspi_xip_encryption_set(NRF_QSPI_Type * p_reg, bool enable);
606 #endif
607
608 #if NRF_QSPI_HAS_DMA_ENC
609 /**
610 * @brief Function for configuring the EasyDMA encryption.
611 *
612 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
613 * @param[in] p_cfg Pointer to encryption configuration structure.
614 */
615 NRF_STATIC_INLINE void nrf_qspi_dma_encryption_configure(NRF_QSPI_Type * p_reg,
616 nrf_qspi_encryption_t const * p_cfg);
617
618 /**
619 * @brief Function for enabling or disabling the EasyDMA encryption.
620 *
621 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
622 * @param[in] enable True if EasyDMA encryption is to be enabled, false otherwise.
623 */
624 NRF_STATIC_INLINE void nrf_qspi_dma_encryption_set(NRF_QSPI_Type * p_reg, bool enable);
625 #endif
626
627 #ifndef NRF_DECLARE_ONLY
628
nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg,nrf_qspi_task_t task)629 NRF_STATIC_INLINE void nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg, nrf_qspi_task_t task)
630 {
631 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
632 }
633
nrf_qspi_task_address_get(NRF_QSPI_Type const * p_reg,nrf_qspi_task_t task)634 NRF_STATIC_INLINE uint32_t nrf_qspi_task_address_get(NRF_QSPI_Type const * p_reg,
635 nrf_qspi_task_t task)
636 {
637 return ((uint32_t)p_reg + (uint32_t)task);
638 }
639
nrf_qspi_event_clear(NRF_QSPI_Type * p_reg,nrf_qspi_event_t event)640 NRF_STATIC_INLINE void nrf_qspi_event_clear(NRF_QSPI_Type * p_reg, nrf_qspi_event_t event)
641 {
642 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
643 }
644
nrf_qspi_event_check(NRF_QSPI_Type const * p_reg,nrf_qspi_event_t event)645 NRF_STATIC_INLINE bool nrf_qspi_event_check(NRF_QSPI_Type const * p_reg, nrf_qspi_event_t event)
646 {
647 return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
648 }
649
nrf_qspi_event_address_get(NRF_QSPI_Type const * p_reg,nrf_qspi_event_t event)650 NRF_STATIC_INLINE uint32_t nrf_qspi_event_address_get(NRF_QSPI_Type const * p_reg,
651 nrf_qspi_event_t event)
652 {
653 return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
654 }
655
nrf_qspi_int_enable(NRF_QSPI_Type * p_reg,uint32_t mask)656 NRF_STATIC_INLINE void nrf_qspi_int_enable(NRF_QSPI_Type * p_reg, uint32_t mask)
657 {
658 p_reg->INTENSET = mask;
659 }
660
nrf_qspi_int_disable(NRF_QSPI_Type * p_reg,uint32_t mask)661 NRF_STATIC_INLINE void nrf_qspi_int_disable(NRF_QSPI_Type * p_reg, uint32_t mask)
662 {
663 p_reg->INTENCLR = mask;
664 }
665
nrf_qspi_int_enable_check(NRF_QSPI_Type const * p_reg,uint32_t mask)666 NRF_STATIC_INLINE uint32_t nrf_qspi_int_enable_check(NRF_QSPI_Type const * p_reg, uint32_t mask)
667 {
668 return p_reg->INTENSET & mask;
669 }
670
nrf_qspi_enable(NRF_QSPI_Type * p_reg)671 NRF_STATIC_INLINE void nrf_qspi_enable(NRF_QSPI_Type * p_reg)
672 {
673 p_reg->ENABLE = (QSPI_ENABLE_ENABLE_Enabled << QSPI_ENABLE_ENABLE_Pos);
674 }
675
nrf_qspi_disable(NRF_QSPI_Type * p_reg)676 NRF_STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type * p_reg)
677 {
678 if (nrf52_errata_122())
679 {
680 // Workaround for anomaly 122: "QSPI: QSPI uses current after being disabled".
681 *(volatile uint32_t *)0x40029054ul = 1ul;
682 }
683 p_reg->ENABLE = (QSPI_ENABLE_ENABLE_Disabled << QSPI_ENABLE_ENABLE_Pos);
684 }
685
nrf_qspi_pins_set(NRF_QSPI_Type * p_reg,nrf_qspi_pins_t const * p_pins)686 NRF_STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type * p_reg, nrf_qspi_pins_t const * p_pins)
687 {
688 p_reg->PSEL.SCK = NRF_QSPI_PIN_VAL(p_pins->sck_pin);
689 p_reg->PSEL.CSN = NRF_QSPI_PIN_VAL(p_pins->csn_pin);
690 p_reg->PSEL.IO0 = NRF_QSPI_PIN_VAL(p_pins->io0_pin);
691 p_reg->PSEL.IO1 = NRF_QSPI_PIN_VAL(p_pins->io1_pin);
692 p_reg->PSEL.IO2 = NRF_QSPI_PIN_VAL(p_pins->io2_pin);
693 p_reg->PSEL.IO3 = NRF_QSPI_PIN_VAL(p_pins->io3_pin);
694 }
695
nrf_qspi_xip_offset_set(NRF_QSPI_Type * p_reg,uint32_t xip_offset)696 NRF_STATIC_INLINE void nrf_qspi_xip_offset_set(NRF_QSPI_Type * p_reg,
697 uint32_t xip_offset)
698 {
699 p_reg->XIPOFFSET = xip_offset;
700 }
701
nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg,nrf_qspi_prot_conf_t const * p_config)702 NRF_STATIC_INLINE void nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg,
703 nrf_qspi_prot_conf_t const * p_config)
704 {
705 uint32_t config = p_config->readoc;
706 config |= ((uint32_t)p_config->writeoc) << QSPI_IFCONFIG0_WRITEOC_Pos;
707 config |= ((uint32_t)p_config->addrmode) << QSPI_IFCONFIG0_ADDRMODE_Pos;
708 config |= (p_config->dpmconfig ? 1U : 0U ) << QSPI_IFCONFIG0_DPMENABLE_Pos;
709
710 p_reg->IFCONFIG0 = config;
711 }
712
nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg,nrf_qspi_phy_conf_t const * p_config)713 NRF_STATIC_INLINE void nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg,
714 nrf_qspi_phy_conf_t const * p_config)
715 {
716 // IFCONFIG1 mask for reserved fields in the register.
717 uint32_t config = p_reg->IFCONFIG1 & 0x00FFFF00;
718 config |= p_config->sck_delay;
719 config |= (p_config->dpmen ? 1U : 0U) << QSPI_IFCONFIG1_DPMEN_Pos;
720 config |= ((uint32_t)(p_config->spi_mode)) << QSPI_IFCONFIG1_SPIMODE_Pos;
721 config |= ((uint32_t)(p_config->sck_freq)) << QSPI_IFCONFIG1_SCKFREQ_Pos;
722
723 p_reg->IFCONFIG1 = config;
724 }
725
nrf_qspi_addrconfig_set(NRF_QSPI_Type * p_reg,nrf_qspi_addrconfig_conf_t const * p_config)726 NRF_STATIC_INLINE void nrf_qspi_addrconfig_set(NRF_QSPI_Type * p_reg,
727 nrf_qspi_addrconfig_conf_t const * p_config)
728 {
729 uint32_t config = p_config->opcode;
730 config |= ((uint32_t)p_config->byte0) << QSPI_ADDRCONF_BYTE0_Pos;
731 config |= ((uint32_t)p_config->byte1) << QSPI_ADDRCONF_BYTE1_Pos;
732 config |= ((uint32_t)(p_config->mode)) << QSPI_ADDRCONF_MODE_Pos;
733 config |= (p_config->wipwait ? 1U : 0U) << QSPI_ADDRCONF_WIPWAIT_Pos;
734 config |= (p_config->wren ? 1U : 0U) << QSPI_ADDRCONF_WREN_Pos;
735
736 p_reg->ADDRCONF = config;
737 }
738
nrf_qspi_write_buffer_set(NRF_QSPI_Type * p_reg,void const * p_buffer,uint32_t length,uint32_t dest_addr)739 NRF_STATIC_INLINE void nrf_qspi_write_buffer_set(NRF_QSPI_Type * p_reg,
740 void const * p_buffer,
741 uint32_t length,
742 uint32_t dest_addr)
743 {
744 p_reg->WRITE.DST = dest_addr;
745 p_reg->WRITE.SRC = (uint32_t) p_buffer;
746 p_reg->WRITE.CNT = length;
747 }
748
nrf_qspi_read_buffer_set(NRF_QSPI_Type * p_reg,void * p_buffer,uint32_t length,uint32_t src_addr)749 NRF_STATIC_INLINE void nrf_qspi_read_buffer_set(NRF_QSPI_Type * p_reg,
750 void * p_buffer,
751 uint32_t length,
752 uint32_t src_addr)
753 {
754 p_reg->READ.SRC = src_addr;
755 p_reg->READ.DST = (uint32_t) p_buffer;
756 p_reg->READ.CNT = length;
757 }
758
nrf_qspi_erase_ptr_set(NRF_QSPI_Type * p_reg,uint32_t erase_addr,nrf_qspi_erase_len_t len)759 NRF_STATIC_INLINE void nrf_qspi_erase_ptr_set(NRF_QSPI_Type * p_reg,
760 uint32_t erase_addr,
761 nrf_qspi_erase_len_t len)
762 {
763 p_reg->ERASE.PTR = erase_addr;
764 p_reg->ERASE.LEN = len;
765 }
766
nrf_qspi_status_reg_get(NRF_QSPI_Type const * p_reg)767 NRF_STATIC_INLINE uint32_t nrf_qspi_status_reg_get(NRF_QSPI_Type const * p_reg)
768 {
769 return p_reg->STATUS;
770 }
771
nrf_qspi_sreg_get(NRF_QSPI_Type const * p_reg)772 NRF_STATIC_INLINE uint8_t nrf_qspi_sreg_get(NRF_QSPI_Type const * p_reg)
773 {
774 return (uint8_t)(p_reg->STATUS & QSPI_STATUS_SREG_Msk) >> QSPI_STATUS_SREG_Pos;
775 }
776
nrf_qspi_busy_check(NRF_QSPI_Type const * p_reg)777 NRF_STATIC_INLINE bool nrf_qspi_busy_check(NRF_QSPI_Type const * p_reg)
778 {
779 return ((p_reg->STATUS & QSPI_STATUS_READY_Msk) >>
780 QSPI_STATUS_READY_Pos) == QSPI_STATUS_READY_BUSY;
781 }
782
nrf_qspi_cinstrdata_set(NRF_QSPI_Type * p_reg,nrf_qspi_cinstr_len_t length,void const * p_tx_data)783 NRF_STATIC_INLINE void nrf_qspi_cinstrdata_set(NRF_QSPI_Type * p_reg,
784 nrf_qspi_cinstr_len_t length,
785 void const * p_tx_data)
786 {
787 uint32_t reg = 0;
788 uint8_t const *p_tx_data_8 = (uint8_t const *) p_tx_data;
789
790 // Load custom instruction.
791 switch (length)
792 {
793 case NRF_QSPI_CINSTR_LEN_9B:
794 reg |= ((uint32_t)p_tx_data_8[7]) << QSPI_CINSTRDAT1_BYTE7_Pos;
795 /* fall-through */
796 case NRF_QSPI_CINSTR_LEN_8B:
797 reg |= ((uint32_t)p_tx_data_8[6]) << QSPI_CINSTRDAT1_BYTE6_Pos;
798 /* fall-through */
799 case NRF_QSPI_CINSTR_LEN_7B:
800 reg |= ((uint32_t)p_tx_data_8[5]) << QSPI_CINSTRDAT1_BYTE5_Pos;
801 /* fall-through */
802 case NRF_QSPI_CINSTR_LEN_6B:
803 reg |= ((uint32_t)p_tx_data_8[4]);
804 p_reg->CINSTRDAT1 = reg;
805 reg = 0;
806 /* fall-through */
807 case NRF_QSPI_CINSTR_LEN_5B:
808 reg |= ((uint32_t)p_tx_data_8[3]) << QSPI_CINSTRDAT0_BYTE3_Pos;
809 /* fall-through */
810 case NRF_QSPI_CINSTR_LEN_4B:
811 reg |= ((uint32_t)p_tx_data_8[2]) << QSPI_CINSTRDAT0_BYTE2_Pos;
812 /* fall-through */
813 case NRF_QSPI_CINSTR_LEN_3B:
814 reg |= ((uint32_t)p_tx_data_8[1]) << QSPI_CINSTRDAT0_BYTE1_Pos;
815 /* fall-through */
816 case NRF_QSPI_CINSTR_LEN_2B:
817 reg |= ((uint32_t)p_tx_data_8[0]);
818 p_reg->CINSTRDAT0 = reg;
819 /* fall-through */
820 case NRF_QSPI_CINSTR_LEN_1B:
821 /* Send only opcode. Case to avoid compiler warnings. */
822 break;
823 default:
824 break;
825 }
826 }
827
nrf_qspi_cinstrdata_get(NRF_QSPI_Type const * p_reg,nrf_qspi_cinstr_len_t length,void * p_rx_data)828 NRF_STATIC_INLINE void nrf_qspi_cinstrdata_get(NRF_QSPI_Type const * p_reg,
829 nrf_qspi_cinstr_len_t length,
830 void * p_rx_data)
831 {
832 uint8_t *p_rx_data_8 = (uint8_t *) p_rx_data;
833
834 uint32_t reg1 = p_reg->CINSTRDAT1;
835 uint32_t reg0 = p_reg->CINSTRDAT0;
836 switch (length)
837 {
838 case NRF_QSPI_CINSTR_LEN_9B:
839 p_rx_data_8[7] = (uint8_t)(reg1 >> QSPI_CINSTRDAT1_BYTE7_Pos);
840 /* fall-through */
841 case NRF_QSPI_CINSTR_LEN_8B:
842 p_rx_data_8[6] = (uint8_t)(reg1 >> QSPI_CINSTRDAT1_BYTE6_Pos);
843 /* fall-through */
844 case NRF_QSPI_CINSTR_LEN_7B:
845 p_rx_data_8[5] = (uint8_t)(reg1 >> QSPI_CINSTRDAT1_BYTE5_Pos);
846 /* fall-through */
847 case NRF_QSPI_CINSTR_LEN_6B:
848 p_rx_data_8[4] = (uint8_t)(reg1);
849 /* fall-through */
850 case NRF_QSPI_CINSTR_LEN_5B:
851 p_rx_data_8[3] = (uint8_t)(reg0 >> QSPI_CINSTRDAT0_BYTE3_Pos);
852 /* fall-through */
853 case NRF_QSPI_CINSTR_LEN_4B:
854 p_rx_data_8[2] = (uint8_t)(reg0 >> QSPI_CINSTRDAT0_BYTE2_Pos);
855 /* fall-through */
856 case NRF_QSPI_CINSTR_LEN_3B:
857 p_rx_data_8[1] = (uint8_t)(reg0 >> QSPI_CINSTRDAT0_BYTE1_Pos);
858 /* fall-through */
859 case NRF_QSPI_CINSTR_LEN_2B:
860 p_rx_data_8[0] = (uint8_t)(reg0);
861 /* fall-through */
862 case NRF_QSPI_CINSTR_LEN_1B:
863 /* Send only opcode. Case to avoid compiler warnings. */
864 break;
865 default:
866 break;
867 }
868 }
869
nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type * p_reg,nrf_qspi_cinstr_conf_t const * p_config)870 NRF_STATIC_INLINE void nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type * p_reg,
871 nrf_qspi_cinstr_conf_t const * p_config)
872 {
873 p_reg->CINSTRCONF = (((uint32_t)p_config->opcode << QSPI_CINSTRCONF_OPCODE_Pos) |
874 ((uint32_t)p_config->length << QSPI_CINSTRCONF_LENGTH_Pos) |
875 ((uint32_t)p_config->io2_level << QSPI_CINSTRCONF_LIO2_Pos) |
876 ((uint32_t)p_config->io3_level << QSPI_CINSTRCONF_LIO3_Pos) |
877 ((uint32_t)p_config->wipwait << QSPI_CINSTRCONF_WIPWAIT_Pos) |
878 ((uint32_t)p_config->wren << QSPI_CINSTRCONF_WREN_Pos));
879 }
880
nrf_qspi_cinstr_long_transfer_start(NRF_QSPI_Type * p_reg,nrf_qspi_cinstr_conf_t const * p_config)881 NRF_STATIC_INLINE void nrf_qspi_cinstr_long_transfer_start(NRF_QSPI_Type * p_reg,
882 nrf_qspi_cinstr_conf_t const * p_config)
883 {
884 p_reg->CINSTRCONF = (((uint32_t)p_config->opcode << QSPI_CINSTRCONF_OPCODE_Pos) |
885 ((uint32_t)p_config->length << QSPI_CINSTRCONF_LENGTH_Pos) |
886 ((uint32_t)p_config->io2_level << QSPI_CINSTRCONF_LIO2_Pos) |
887 ((uint32_t)p_config->io3_level << QSPI_CINSTRCONF_LIO3_Pos) |
888 ((uint32_t)p_config->wipwait << QSPI_CINSTRCONF_WIPWAIT_Pos) |
889 ((uint32_t)p_config->wren << QSPI_CINSTRCONF_WREN_Pos) |
890 (QSPI_CINSTRCONF_LFEN_Msk));
891 }
892
nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI_Type const * p_reg)893 NRF_STATIC_INLINE bool nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI_Type const * p_reg)
894 {
895 return (bool)((p_reg->CINSTRCONF & (QSPI_CINSTRCONF_LFEN_Msk | QSPI_CINSTRCONF_LFSTOP_Msk))
896 == QSPI_CINSTRCONF_LFEN_Msk);
897 }
898
nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI_Type * p_reg,nrf_qspi_cinstr_len_t length,bool finalize)899 NRF_STATIC_INLINE void nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI_Type * p_reg,
900 nrf_qspi_cinstr_len_t length,
901 bool finalize)
902 {
903 uint32_t mask = (((uint32_t)length << QSPI_CINSTRCONF_LENGTH_Pos) | (QSPI_CINSTRCONF_LFEN_Msk));
904 mask |= (finalize ? QSPI_CINSTRCONF_LFSTOP_Msk : 0);
905
906 p_reg->CINSTRCONF = mask;
907 }
908
909 #if NRF_QSPI_HAS_XIPEN
nrf_qspi_xip_set(NRF_QSPI_Type * p_reg,bool enable)910 NRF_STATIC_INLINE void nrf_qspi_xip_set(NRF_QSPI_Type * p_reg, bool enable)
911 {
912 p_reg->XIPEN = (enable ? QSPI_XIPEN_XIPEN_Enable << QSPI_XIPEN_XIPEN_Pos
913 : QSPI_XIPEN_XIPEN_Disable << QSPI_XIPEN_XIPEN_Pos);
914 }
915 #endif
916
917 #if NRF_QSPI_HAS_XIP_ENC
nrf_qspi_xip_encryption_configure(NRF_QSPI_Type * p_reg,nrf_qspi_encryption_t const * p_cfg)918 NRF_STATIC_INLINE void nrf_qspi_xip_encryption_configure(NRF_QSPI_Type * p_reg,
919 nrf_qspi_encryption_t const * p_cfg)
920 {
921 p_reg->XIP_ENC.KEY0 = p_cfg->key[0];
922 p_reg->XIP_ENC.KEY1 = p_cfg->key[1];
923 p_reg->XIP_ENC.KEY2 = p_cfg->key[2];
924 p_reg->XIP_ENC.KEY3 = p_cfg->key[3];
925 p_reg->XIP_ENC.NONCE0 = p_cfg->nonce[0];
926 p_reg->XIP_ENC.NONCE1 = p_cfg->nonce[1];
927 p_reg->XIP_ENC.NONCE2 = p_cfg->nonce[2];
928 }
929
nrf_qspi_xip_encryption_set(NRF_QSPI_Type * p_reg,bool enable)930 NRF_STATIC_INLINE void nrf_qspi_xip_encryption_set(NRF_QSPI_Type * p_reg, bool enable)
931 {
932 p_reg->XIP_ENC.ENABLE =
933 (enable ? QSPI_XIP_ENC_ENABLE_ENABLE_Enabled << QSPI_XIP_ENC_ENABLE_ENABLE_Pos
934 : QSPI_XIP_ENC_ENABLE_ENABLE_Disabled << QSPI_XIP_ENC_ENABLE_ENABLE_Pos);
935 }
936 #endif
937
938 #if NRF_QSPI_HAS_DMA_ENC
nrf_qspi_dma_encryption_configure(NRF_QSPI_Type * p_reg,nrf_qspi_encryption_t const * p_cfg)939 NRF_STATIC_INLINE void nrf_qspi_dma_encryption_configure(NRF_QSPI_Type * p_reg,
940 nrf_qspi_encryption_t const * p_cfg)
941 {
942 p_reg->DMA_ENC.KEY0 = p_cfg->key[0];
943 p_reg->DMA_ENC.KEY1 = p_cfg->key[1];
944 p_reg->DMA_ENC.KEY2 = p_cfg->key[2];
945 p_reg->DMA_ENC.KEY3 = p_cfg->key[3];
946 p_reg->DMA_ENC.NONCE0 = p_cfg->nonce[0];
947 p_reg->DMA_ENC.NONCE1 = p_cfg->nonce[1];
948 p_reg->DMA_ENC.NONCE2 = p_cfg->nonce[2];
949 }
950
nrf_qspi_dma_encryption_set(NRF_QSPI_Type * p_reg,bool enable)951 NRF_STATIC_INLINE void nrf_qspi_dma_encryption_set(NRF_QSPI_Type * p_reg, bool enable)
952 {
953 p_reg->DMA_ENC.ENABLE =
954 (enable ? QSPI_DMA_ENC_ENABLE_ENABLE_Enabled << QSPI_DMA_ENC_ENABLE_ENABLE_Pos
955 : QSPI_DMA_ENC_ENABLE_ENABLE_Disabled << QSPI_DMA_ENC_ENABLE_ENABLE_Pos);
956 }
957 #endif
958 #endif // NRF_DECLARE_ONLY
959
960 /** @} */
961
962 #ifdef __cplusplus
963 }
964 #endif
965
966 #endif // NRF_QSPI_H__
967