1 /*
2 * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef NRF_SPU_H__
33 #define NRF_SPU_H__
34
35 #include <nrfx.h>
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /**
42 * @defgroup nrf_spu_hal SPU HAL
43 * @{
44 * @ingroup nrf_spu
45 * @brief Hardware access layer for managing the System Protection Unit (SPU) peripheral.
46 */
47
48 /** @brief SPU events. */
49 typedef enum
50 {
51 NRF_SPU_EVENT_RAMACCERR = offsetof(NRF_SPU_Type, EVENTS_RAMACCERR), ///< A security violation has been detected for the RAM memory space.
52 NRF_SPU_EVENT_FLASHACCERR = offsetof(NRF_SPU_Type, EVENTS_FLASHACCERR), ///< A security violation has been detected for the Flash memory space.
53 NRF_SPU_EVENT_PERIPHACCERR = offsetof(NRF_SPU_Type, EVENTS_PERIPHACCERR) ///< A security violation has been detected on one or several peripherals.
54 } nrf_spu_event_t;
55
56 /** @brief SPU interrupts. */
57 typedef enum
58 {
59 NRF_SPU_INT_RAMACCERR_MASK = SPU_INTENSET_RAMACCERR_Msk, ///< Interrupt on RAMACCERR event.
60 NRF_SPU_INT_FLASHACCERR_MASK = SPU_INTENSET_FLASHACCERR_Msk, ///< Interrupt on FLASHACCERR event.
61 NRF_SPU_INT_PERIPHACCERR_MASK = SPU_INTENSET_PERIPHACCERR_Msk ///< Interrupt on PERIPHACCERR event.
62 } nrf_spu_int_mask_t;
63
64 /** @brief SPU Non-Secure Callable (NSC) region size. */
65 typedef enum
66 {
67 NRF_SPU_NSC_SIZE_DISABLED = 0, ///< Not defined as a non-secure callable region.
68 NRF_SPU_NSC_SIZE_32B = 1, ///< Non-Secure Callable region with a 32-byte size
69 NRF_SPU_NSC_SIZE_64B = 2, ///< Non-Secure Callable region with a 64-byte size
70 NRF_SPU_NSC_SIZE_128B = 3, ///< Non-Secure Callable region with a 128-byte size
71 NRF_SPU_NSC_SIZE_256B = 4, ///< Non-Secure Callable region with a 256-byte size
72 NRF_SPU_NSC_SIZE_512B = 5, ///< Non-Secure Callable region with a 512-byte size
73 NRF_SPU_NSC_SIZE_1024B = 6, ///< Non-Secure Callable region with a 1024-byte size
74 NRF_SPU_NSC_SIZE_2048B = 7, ///< Non-Secure Callable region with a 2048-byte size
75 NRF_SPU_NSC_SIZE_4096B = 8 ///< Non-Secure Callable region with a 4096-byte size
76 } nrf_spu_nsc_size_t;
77
78 /** @brief SPU memory region permissions. */
79 typedef enum
80 {
81 NRF_SPU_MEM_PERM_EXECUTE = SPU_FLASHREGION_PERM_EXECUTE_Msk, ///< Allow code execution from particular memory region.
82 NRF_SPU_MEM_PERM_WRITE = SPU_FLASHREGION_PERM_WRITE_Msk, ///< Allow write operation on particular memory region.
83 NRF_SPU_MEM_PERM_READ = SPU_FLASHREGION_PERM_READ_Msk ///< Allow read operation from particular memory region.
84 } nrf_spu_mem_perm_t;
85
86 /**
87 * @brief Function for clearing a specific SPU event.
88 *
89 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
90 * @param[in] event Event to clear.
91 */
92 NRF_STATIC_INLINE void nrf_spu_event_clear(NRF_SPU_Type * p_reg,
93 nrf_spu_event_t event);
94
95 /**
96 * @brief Function for retrieving the state of the SPU event.
97 *
98 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
99 * @param[in] event Event to be checked.
100 *
101 * @retval true The event has been generated.
102 * @retval false The event has not been generated.
103 */
104 NRF_STATIC_INLINE bool nrf_spu_event_check(NRF_SPU_Type const * p_reg,
105 nrf_spu_event_t event);
106
107 /**
108 * @brief Function for enabling specified interrupts.
109 *
110 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
111 * @param[in] mask Interrupts to be enabled.
112 */
113 NRF_STATIC_INLINE void nrf_spu_int_enable(NRF_SPU_Type * p_reg,
114 uint32_t mask);
115
116 /**
117 * @brief Function for disabling specified interrupts.
118 *
119 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
120 * @param[in] mask Interrupts to be disabled.
121 */
122 NRF_STATIC_INLINE void nrf_spu_int_disable(NRF_SPU_Type * p_reg,
123 uint32_t mask);
124
125 /**
126 * @brief Function for checking if the specified interrupts are enabled.
127 *
128 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
129 * @param[in] mask Mask of interrupts to be checked.
130 *
131 * @return Mask of enabled interrupts.
132 */
133 NRF_STATIC_INLINE uint32_t nrf_spu_int_enable_check(NRF_SPU_Type const * p_reg, uint32_t mask);
134
135 /**
136 * @brief Function for setting up publication configuration of a given SPU event.
137 *
138 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
139 * @param[in] event Event to configure.
140 * @param[in] channel Channel to connect with published event.
141 */
142 NRF_STATIC_INLINE void nrf_spu_publish_set(NRF_SPU_Type * p_reg,
143 nrf_spu_event_t event,
144 uint32_t channel);
145
146 /**
147 * @brief Function for clearing publication configuration of a given SPU event.
148 *
149 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
150 * @param[in] event Event to clear.
151 */
152 NRF_STATIC_INLINE void nrf_spu_publish_clear(NRF_SPU_Type * p_reg,
153 nrf_spu_event_t event);
154
155 /**
156 * @brief Function for retrieving the capabilities of the current device.
157 *
158 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
159 *
160 * @retval true ARM TrustZone support is available.
161 * @retval false ARM TrustZone support is not available.
162 */
163 NRF_STATIC_INLINE bool nrf_spu_tz_is_available(NRF_SPU_Type const * p_reg);
164
165 /**
166 * @brief Function for configuring the DPPI channels to be available in particular domains.
167 *
168 * Channels are configured as bitmask. Set one in bitmask to make channels available only in secure
169 * domain. Set zero to make it available in secure and non-secure domains.
170 *
171 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
172 * @param[in] dppi_id DPPI peripheral id.
173 * @param[in] channels_mask Bitmask with channels configuration.
174 * @param[in] lock_conf Lock configuration until next SoC reset.
175 */
176 NRF_STATIC_INLINE void nrf_spu_dppi_config_set(NRF_SPU_Type * p_reg,
177 uint8_t dppi_id,
178 uint32_t channels_mask,
179 bool lock_conf);
180
181 /**
182 * @brief Function for configuring the GPIO pins to be available in particular domains.
183 *
184 * GPIO pins are configured as bitmask. Set one in bitmask to make particular pin available only
185 * in secure domain. Set zero to make it available in secure and non-secure domains.
186 *
187 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
188 * @param[in] gpio_port Port number.
189 * @param[in] gpio_mask Bitmask with gpio configuration.
190 * @param[in] lock_conf Lock configuration until next SoC reset.
191 */
192 NRF_STATIC_INLINE void nrf_spu_gpio_config_set(NRF_SPU_Type * p_reg,
193 uint8_t gpio_port,
194 uint32_t gpio_mask,
195 bool lock_conf);
196
197 /**
198 * @brief Function for configuring non-secure callable flash region.
199 *
200 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
201 * @param[in] flash_nsc_id Non-secure callable flash region ID.
202 * @param[in] flash_nsc_size Non-secure callable flash region size.
203 * @param[in] region_number Flash region number.
204 * @param[in] lock_conf Lock configuration until next SoC reset.
205 */
206 NRF_STATIC_INLINE void nrf_spu_flashnsc_set(NRF_SPU_Type * p_reg,
207 uint8_t flash_nsc_id,
208 nrf_spu_nsc_size_t flash_nsc_size,
209 uint8_t region_number,
210 bool lock_conf);
211
212 /**
213 * @brief Function for configuring non-secure callable RAM region.
214 *
215 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
216 * @param[in] ram_nsc_id Non-secure callable RAM region ID.
217 * @param[in] ram_nsc_size Non-secure callable RAM region size.
218 * @param[in] region_number RAM region number.
219 * @param[in] lock_conf Lock configuration until next SoC reset.
220 */
221 NRF_STATIC_INLINE void nrf_spu_ramnsc_set(NRF_SPU_Type * p_reg,
222 uint8_t ram_nsc_id,
223 nrf_spu_nsc_size_t ram_nsc_size,
224 uint8_t region_number,
225 bool lock_conf);
226
227 /**
228 * @brief Function for configuring security for a particular flash region.
229 *
230 * Permissions parameter must be set by using the logical OR on the @ref nrf_spu_mem_perm_t values.
231 *
232 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
233 * @param[in] region_id Flash region index.
234 * @param[in] secure_attr Set region attribute to secure.
235 * @param[in] permissions Flash region permissions.
236 * @param[in] lock_conf Lock configuration until next SoC reset.
237 */
238 NRF_STATIC_INLINE void nrf_spu_flashregion_set(NRF_SPU_Type * p_reg,
239 uint8_t region_id,
240 bool secure_attr,
241 uint32_t permissions,
242 bool lock_conf);
243
244 /**
245 * @brief Function for configuring security for the RAM region.
246 *
247 * Permissions parameter must be set by using the logical OR on the @ref nrf_spu_mem_perm_t values.
248 *
249 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
250 * @param[in] region_id RAM region index.
251 * @param[in] secure_attr Set region attribute to secure.
252 * @param[in] permissions RAM region permissions.
253 * @param[in] lock_conf Lock configuration until next SoC reset.
254 */
255 NRF_STATIC_INLINE void nrf_spu_ramregion_set(NRF_SPU_Type * p_reg,
256 uint8_t region_id,
257 bool secure_attr,
258 uint32_t permissions,
259 bool lock_conf);
260
261 /**
262 * @brief Function for configuring access permissions of the peripheral.
263 *
264 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
265 * @param[in] peripheral_id ID number of a particular peripheral.
266 * @param[in] secure_attr Peripheral registers accessible only from secure domain.
267 * @param[in] secure_dma DMA transfers possible only from RAM memory in secure domain.
268 * @param[in] lock_conf Lock configuration until next SoC reset.
269 */
270 NRF_STATIC_INLINE void nrf_spu_peripheral_set(NRF_SPU_Type * p_reg,
271 uint32_t peripheral_id,
272 bool secure_attr,
273 bool secure_dma,
274 bool lock_conf);
275
276 /**
277 * @brief Function for configuring bus access permissions of the specified external domain.
278 *
279 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
280 * @param[in] domain_id ID number of a particular external domain.
281 * @param[in] secure_attr Specifies if the bus accesses from this domain have the secure attribute set.
282 * @param[in] lock_conf Specifies if the configuration should be locked until next SoC reset.
283 */
284 NRF_STATIC_INLINE void nrf_spu_extdomain_set(NRF_SPU_Type * p_reg,
285 uint32_t domain_id,
286 bool secure_attr,
287 bool lock_conf);
288
289 #ifndef NRF_DECLARE_ONLY
290
nrf_spu_event_clear(NRF_SPU_Type * p_reg,nrf_spu_event_t event)291 NRF_STATIC_INLINE void nrf_spu_event_clear(NRF_SPU_Type * p_reg,
292 nrf_spu_event_t event)
293 {
294 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
295 volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
296 (void)dummy;
297 }
298
nrf_spu_event_check(NRF_SPU_Type const * p_reg,nrf_spu_event_t event)299 NRF_STATIC_INLINE bool nrf_spu_event_check(NRF_SPU_Type const * p_reg,
300 nrf_spu_event_t event)
301 {
302 return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
303 }
304
nrf_spu_int_enable(NRF_SPU_Type * p_reg,uint32_t mask)305 NRF_STATIC_INLINE void nrf_spu_int_enable(NRF_SPU_Type * p_reg,
306 uint32_t mask)
307 {
308 p_reg->INTENSET = mask;
309 }
310
nrf_spu_int_disable(NRF_SPU_Type * p_reg,uint32_t mask)311 NRF_STATIC_INLINE void nrf_spu_int_disable(NRF_SPU_Type * p_reg,
312 uint32_t mask)
313 {
314 p_reg->INTENCLR = mask;
315 }
316
nrf_spu_int_enable_check(NRF_SPU_Type const * p_reg,uint32_t mask)317 NRF_STATIC_INLINE uint32_t nrf_spu_int_enable_check(NRF_SPU_Type const * p_reg, uint32_t mask)
318 {
319 return p_reg->INTENSET & mask;
320 }
321
nrf_spu_publish_set(NRF_SPU_Type * p_reg,nrf_spu_event_t event,uint32_t channel)322 NRF_STATIC_INLINE void nrf_spu_publish_set(NRF_SPU_Type * p_reg,
323 nrf_spu_event_t event,
324 uint32_t channel)
325 {
326 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
327 (channel | (SPU_PUBLISH_RAMACCERR_EN_Msk));
328 }
329
nrf_spu_publish_clear(NRF_SPU_Type * p_reg,nrf_spu_event_t event)330 NRF_STATIC_INLINE void nrf_spu_publish_clear(NRF_SPU_Type * p_reg,
331 nrf_spu_event_t event)
332 {
333 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
334 }
335
nrf_spu_tz_is_available(NRF_SPU_Type const * p_reg)336 NRF_STATIC_INLINE bool nrf_spu_tz_is_available(NRF_SPU_Type const * p_reg)
337 {
338 return (p_reg->CAP & SPU_CAP_TZM_Msk ? true : false);
339 }
340
nrf_spu_dppi_config_set(NRF_SPU_Type * p_reg,uint8_t dppi_id,uint32_t channels_mask,bool lock_conf)341 NRF_STATIC_INLINE void nrf_spu_dppi_config_set(NRF_SPU_Type * p_reg,
342 uint8_t dppi_id,
343 uint32_t channels_mask,
344 bool lock_conf)
345 {
346 NRFX_ASSERT(!(p_reg->DPPI[dppi_id].LOCK & SPU_DPPI_LOCK_LOCK_Msk));
347
348 p_reg->DPPI[dppi_id].PERM = channels_mask;
349
350 if (lock_conf)
351 {
352 p_reg->DPPI[dppi_id].LOCK = (SPU_DPPI_LOCK_LOCK_Msk);
353 }
354 }
355
nrf_spu_gpio_config_set(NRF_SPU_Type * p_reg,uint8_t gpio_port,uint32_t gpio_mask,bool lock_conf)356 NRF_STATIC_INLINE void nrf_spu_gpio_config_set(NRF_SPU_Type * p_reg,
357 uint8_t gpio_port,
358 uint32_t gpio_mask,
359 bool lock_conf)
360 {
361 NRFX_ASSERT(!(p_reg->GPIOPORT[gpio_port].LOCK & SPU_GPIOPORT_LOCK_LOCK_Msk));
362
363 p_reg->GPIOPORT[gpio_port].PERM = gpio_mask;
364
365 if (lock_conf)
366 {
367 p_reg->GPIOPORT[gpio_port].LOCK = (SPU_GPIOPORT_LOCK_LOCK_Msk);
368 }
369 }
370
nrf_spu_flashnsc_set(NRF_SPU_Type * p_reg,uint8_t flash_nsc_id,nrf_spu_nsc_size_t flash_nsc_size,uint8_t region_number,bool lock_conf)371 NRF_STATIC_INLINE void nrf_spu_flashnsc_set(NRF_SPU_Type * p_reg,
372 uint8_t flash_nsc_id,
373 nrf_spu_nsc_size_t flash_nsc_size,
374 uint8_t region_number,
375 bool lock_conf)
376 {
377 NRFX_ASSERT(!(p_reg->FLASHNSC[flash_nsc_id].REGION & SPU_FLASHNSC_REGION_LOCK_Msk));
378 NRFX_ASSERT(!(p_reg->FLASHNSC[flash_nsc_id].SIZE & SPU_FLASHNSC_SIZE_LOCK_Msk));
379
380 p_reg->FLASHNSC[flash_nsc_id].REGION = (uint32_t)region_number |
381 (lock_conf ? SPU_FLASHNSC_REGION_LOCK_Msk : 0);
382 p_reg->FLASHNSC[flash_nsc_id].SIZE = (uint32_t)flash_nsc_size |
383 (lock_conf ? SPU_FLASHNSC_SIZE_LOCK_Msk : 0);
384 }
385
nrf_spu_ramnsc_set(NRF_SPU_Type * p_reg,uint8_t ram_nsc_id,nrf_spu_nsc_size_t ram_nsc_size,uint8_t region_number,bool lock_conf)386 NRF_STATIC_INLINE void nrf_spu_ramnsc_set(NRF_SPU_Type * p_reg,
387 uint8_t ram_nsc_id,
388 nrf_spu_nsc_size_t ram_nsc_size,
389 uint8_t region_number,
390 bool lock_conf)
391 {
392 NRFX_ASSERT(!(p_reg->RAMNSC[ram_nsc_id].REGION & SPU_RAMNSC_REGION_LOCK_Msk));
393 NRFX_ASSERT(!(p_reg->RAMNSC[ram_nsc_id].SIZE & SPU_RAMNSC_SIZE_LOCK_Msk));
394
395 p_reg->RAMNSC[ram_nsc_id].REGION = (uint32_t)region_number |
396 (lock_conf ? SPU_RAMNSC_REGION_LOCK_Msk : 0);
397 p_reg->RAMNSC[ram_nsc_id].SIZE = (uint32_t)ram_nsc_size |
398 (lock_conf ? SPU_RAMNSC_SIZE_LOCK_Msk : 0);
399 }
400
nrf_spu_flashregion_set(NRF_SPU_Type * p_reg,uint8_t region_id,bool secure_attr,uint32_t permissions,bool lock_conf)401 NRF_STATIC_INLINE void nrf_spu_flashregion_set(NRF_SPU_Type * p_reg,
402 uint8_t region_id,
403 bool secure_attr,
404 uint32_t permissions,
405 bool lock_conf)
406 {
407 NRFX_ASSERT(!(p_reg->FLASHREGION[region_id].PERM & SPU_FLASHREGION_PERM_LOCK_Msk));
408
409 p_reg->FLASHREGION[region_id].PERM = permissions |
410 (secure_attr ? SPU_FLASHREGION_PERM_SECATTR_Msk : 0) |
411 (lock_conf ? SPU_FLASHREGION_PERM_LOCK_Msk : 0);
412 }
413
nrf_spu_ramregion_set(NRF_SPU_Type * p_reg,uint8_t region_id,bool secure_attr,uint32_t permissions,bool lock_conf)414 NRF_STATIC_INLINE void nrf_spu_ramregion_set(NRF_SPU_Type * p_reg,
415 uint8_t region_id,
416 bool secure_attr,
417 uint32_t permissions,
418 bool lock_conf)
419 {
420 NRFX_ASSERT(!(p_reg->RAMREGION[region_id].PERM & SPU_RAMREGION_PERM_LOCK_Msk));
421
422 p_reg->RAMREGION[region_id].PERM = permissions |
423 (secure_attr ? SPU_RAMREGION_PERM_SECATTR_Msk : 0) |
424 (lock_conf ? SPU_RAMREGION_PERM_LOCK_Msk : 0);
425 }
426
nrf_spu_peripheral_set(NRF_SPU_Type * p_reg,uint32_t peripheral_id,bool secure_attr,bool secure_dma,bool lock_conf)427 NRF_STATIC_INLINE void nrf_spu_peripheral_set(NRF_SPU_Type * p_reg,
428 uint32_t peripheral_id,
429 bool secure_attr,
430 bool secure_dma,
431 bool lock_conf)
432 {
433 NRFX_ASSERT(p_reg->PERIPHID[peripheral_id].PERM & SPU_PERIPHID_PERM_PRESENT_Msk);
434 NRFX_ASSERT(!(p_reg->PERIPHID[peripheral_id].PERM & SPU_PERIPHID_PERM_LOCK_Msk));
435
436 p_reg->PERIPHID[peripheral_id].PERM =
437 (secure_attr ? SPU_PERIPHID_PERM_SECATTR_Msk : 0) |
438 (secure_dma ? SPU_PERIPHID_PERM_DMASEC_Msk : 0) |
439 (lock_conf ? SPU_PERIPHID_PERM_LOCK_Msk : 0);
440 }
441
nrf_spu_extdomain_set(NRF_SPU_Type * p_reg,uint32_t domain_id,bool secure_attr,bool lock_conf)442 NRF_STATIC_INLINE void nrf_spu_extdomain_set(NRF_SPU_Type * p_reg,
443 uint32_t domain_id,
444 bool secure_attr,
445 bool lock_conf)
446 {
447 NRFX_ASSERT(!(p_reg->EXTDOMAIN[domain_id].PERM & SPU_EXTDOMAIN_PERM_LOCK_Msk));
448
449 p_reg->EXTDOMAIN[domain_id].PERM =
450 (secure_attr ? SPU_EXTDOMAIN_PERM_SECATTR_Msk : 0) |
451 (lock_conf ? SPU_EXTDOMAIN_PERM_LOCK_Msk : 0);
452 }
453
454 #endif // NRF_DECLARE_ONLY
455
456 /** @} */
457
458 #ifdef __cplusplus
459 }
460 #endif
461
462 #endif // NRF_SPU_H__
463