1 /**
2 ******************************************************************************
3 * @file system_stm32f4xx.c
4 * @author MCD Application Team
5 * @version V1.5.0
6 * @date 06-March-2015
7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
8 * This file contains the system clock configuration for STM32F4xx devices.
9 *
10 * 1. This file provides two functions and one global variable to be called from
11 * user application:
12 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
13 * and Divider factors, AHB/APBx prescalers and Flash settings),
14 * depending on the configuration made in the clock xls tool.
15 * This function is called at startup just after reset and
16 * before branch to main program. This call is made inside
17 * the "startup_stm32f4xx.s" file.
18 *
19 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
20 * by the user application to setup the SysTick
21 * timer or configure other parameters.
22 *
23 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
24 * be called whenever the core clock is changed
25 * during program execution.
26 *
27 * 2. After each device reset the HSI (16 MHz) is used as system clock source.
28 * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
29 * configure the system clock before to branch to main program.
30 *
31 * 3. If the system clock source selected by user fails to startup, the SystemInit()
32 * function will do nothing and HSI still used as system clock source. User can
33 * add some code to deal with this issue inside the SetSysClock() function.
34 *
35 * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
36 * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
37 * through PLL, and you are using different crystal you have to adapt the HSE
38 * value to your own configuration.
39 *
40 * 5. This file configures the system clock as follows:
41 *=============================================================================
42 *=============================================================================
43 * Supported STM32F40xxx/41xxx devices
44 *-----------------------------------------------------------------------------
45 * System Clock source | PLL (HSE)
46 *-----------------------------------------------------------------------------
47 * SYSCLK(Hz) | 168000000
48 *-----------------------------------------------------------------------------
49 * HCLK(Hz) | 168000000
50 *-----------------------------------------------------------------------------
51 * AHB Prescaler | 1
52 *-----------------------------------------------------------------------------
53 * APB1 Prescaler | 4
54 *-----------------------------------------------------------------------------
55 * APB2 Prescaler | 2
56 *-----------------------------------------------------------------------------
57 * HSE Frequency(Hz) | 25000000
58 *-----------------------------------------------------------------------------
59 * PLL_M | 25
60 *-----------------------------------------------------------------------------
61 * PLL_N | 336
62 *-----------------------------------------------------------------------------
63 * PLL_P | 2
64 *-----------------------------------------------------------------------------
65 * PLL_Q | 7
66 *-----------------------------------------------------------------------------
67 * PLLI2S_N | NA
68 *-----------------------------------------------------------------------------
69 * PLLI2S_R | NA
70 *-----------------------------------------------------------------------------
71 * I2S input clock | NA
72 *-----------------------------------------------------------------------------
73 * VDD(V) | 3.3
74 *-----------------------------------------------------------------------------
75 * Main regulator output voltage | Scale1 mode
76 *-----------------------------------------------------------------------------
77 * Flash Latency(WS) | 5
78 *-----------------------------------------------------------------------------
79 * Prefetch Buffer | ON
80 *-----------------------------------------------------------------------------
81 * Instruction cache | ON
82 *-----------------------------------------------------------------------------
83 * Data cache | ON
84 *-----------------------------------------------------------------------------
85 * Require 48MHz for USB OTG FS, | Disabled
86 * SDIO and RNG clock |
87 *-----------------------------------------------------------------------------
88 *=============================================================================
89 *=============================================================================
90 * Supported STM32F42xxx/43xxx devices
91 *-----------------------------------------------------------------------------
92 * System Clock source | PLL (HSE)
93 *-----------------------------------------------------------------------------
94 * SYSCLK(Hz) | 180000000
95 *-----------------------------------------------------------------------------
96 * HCLK(Hz) | 180000000
97 *-----------------------------------------------------------------------------
98 * AHB Prescaler | 1
99 *-----------------------------------------------------------------------------
100 * APB1 Prescaler | 4
101 *-----------------------------------------------------------------------------
102 * APB2 Prescaler | 2
103 *-----------------------------------------------------------------------------
104 * HSE Frequency(Hz) | 25000000
105 *-----------------------------------------------------------------------------
106 * PLL_M | 25
107 *-----------------------------------------------------------------------------
108 * PLL_N | 360
109 *-----------------------------------------------------------------------------
110 * PLL_P | 2
111 *-----------------------------------------------------------------------------
112 * PLL_Q | 7
113 *-----------------------------------------------------------------------------
114 * PLLI2S_N | NA
115 *-----------------------------------------------------------------------------
116 * PLLI2S_R | NA
117 *-----------------------------------------------------------------------------
118 * I2S input clock | NA
119 *-----------------------------------------------------------------------------
120 * VDD(V) | 3.3
121 *-----------------------------------------------------------------------------
122 * Main regulator output voltage | Scale1 mode
123 *-----------------------------------------------------------------------------
124 * Flash Latency(WS) | 5
125 *-----------------------------------------------------------------------------
126 * Prefetch Buffer | ON
127 *-----------------------------------------------------------------------------
128 * Instruction cache | ON
129 *-----------------------------------------------------------------------------
130 * Data cache | ON
131 *-----------------------------------------------------------------------------
132 * Require 48MHz for USB OTG FS, | Disabled
133 * SDIO and RNG clock |
134 *-----------------------------------------------------------------------------
135 *=============================================================================
136 *=============================================================================
137 * Supported STM32F401xx devices
138 *-----------------------------------------------------------------------------
139 * System Clock source | PLL (HSE)
140 *-----------------------------------------------------------------------------
141 * SYSCLK(Hz) | 84000000
142 *-----------------------------------------------------------------------------
143 * HCLK(Hz) | 84000000
144 *-----------------------------------------------------------------------------
145 * AHB Prescaler | 1
146 *-----------------------------------------------------------------------------
147 * APB1 Prescaler | 2
148 *-----------------------------------------------------------------------------
149 * APB2 Prescaler | 1
150 *-----------------------------------------------------------------------------
151 * HSE Frequency(Hz) | 25000000
152 *-----------------------------------------------------------------------------
153 * PLL_M | 25
154 *-----------------------------------------------------------------------------
155 * PLL_N | 336
156 *-----------------------------------------------------------------------------
157 * PLL_P | 4
158 *-----------------------------------------------------------------------------
159 * PLL_Q | 7
160 *-----------------------------------------------------------------------------
161 * PLLI2S_N | NA
162 *-----------------------------------------------------------------------------
163 * PLLI2S_R | NA
164 *-----------------------------------------------------------------------------
165 * I2S input clock | NA
166 *-----------------------------------------------------------------------------
167 * VDD(V) | 3.3
168 *-----------------------------------------------------------------------------
169 * Main regulator output voltage | Scale1 mode
170 *-----------------------------------------------------------------------------
171 * Flash Latency(WS) | 2
172 *-----------------------------------------------------------------------------
173 * Prefetch Buffer | ON
174 *-----------------------------------------------------------------------------
175 * Instruction cache | ON
176 *-----------------------------------------------------------------------------
177 * Data cache | ON
178 *-----------------------------------------------------------------------------
179 * Require 48MHz for USB OTG FS, | Disabled
180 * SDIO and RNG clock |
181 *-----------------------------------------------------------------------------
182 *=============================================================================
183 *=============================================================================
184 * Supported STM32F411xx devices
185 *-----------------------------------------------------------------------------
186 * System Clock source | PLL (HSI)
187 *-----------------------------------------------------------------------------
188 * SYSCLK(Hz) | 100000000
189 *-----------------------------------------------------------------------------
190 * HCLK(Hz) | 100000000
191 *-----------------------------------------------------------------------------
192 * AHB Prescaler | 1
193 *-----------------------------------------------------------------------------
194 * APB1 Prescaler | 2
195 *-----------------------------------------------------------------------------
196 * APB2 Prescaler | 1
197 *-----------------------------------------------------------------------------
198 * HSI Frequency(Hz) | 16000000
199 *-----------------------------------------------------------------------------
200 * PLL_M | 16
201 *-----------------------------------------------------------------------------
202 * PLL_N | 400
203 *-----------------------------------------------------------------------------
204 * PLL_P | 4
205 *-----------------------------------------------------------------------------
206 * PLL_Q | 7
207 *-----------------------------------------------------------------------------
208 * PLLI2S_N | NA
209 *-----------------------------------------------------------------------------
210 * PLLI2S_R | NA
211 *-----------------------------------------------------------------------------
212 * I2S input clock | NA
213 *-----------------------------------------------------------------------------
214 * VDD(V) | 3.3
215 *-----------------------------------------------------------------------------
216 * Main regulator output voltage | Scale1 mode
217 *-----------------------------------------------------------------------------
218 * Flash Latency(WS) | 3
219 *-----------------------------------------------------------------------------
220 * Prefetch Buffer | ON
221 *-----------------------------------------------------------------------------
222 * Instruction cache | ON
223 *-----------------------------------------------------------------------------
224 * Data cache | ON
225 *-----------------------------------------------------------------------------
226 * Require 48MHz for USB OTG FS, | Disabled
227 * SDIO and RNG clock |
228 *-----------------------------------------------------------------------------
229 *=============================================================================
230 *=============================================================================
231 * Supported STM32F446xx devices
232 *-----------------------------------------------------------------------------
233 * System Clock source | PLL (HSE)
234 *-----------------------------------------------------------------------------
235 * SYSCLK(Hz) | 180000000
236 *-----------------------------------------------------------------------------
237 * HCLK(Hz) | 180000000
238 *-----------------------------------------------------------------------------
239 * AHB Prescaler | 1
240 *-----------------------------------------------------------------------------
241 * APB1 Prescaler | 4
242 *-----------------------------------------------------------------------------
243 * APB2 Prescaler | 2
244 *-----------------------------------------------------------------------------
245 * HSE Frequency(Hz) | 8000000
246 *-----------------------------------------------------------------------------
247 * PLL_M | 8
248 *-----------------------------------------------------------------------------
249 * PLL_N | 360
250 *-----------------------------------------------------------------------------
251 * PLL_P | 2
252 *-----------------------------------------------------------------------------
253 * PLL_Q | 7
254 *-----------------------------------------------------------------------------
255 * PLL_R | NA
256 *-----------------------------------------------------------------------------
257 * PLLI2S_M | NA
258 *-----------------------------------------------------------------------------
259 * PLLI2S_N | NA
260 *-----------------------------------------------------------------------------
261 * PLLI2S_P | NA
262 *-----------------------------------------------------------------------------
263 * PLLI2S_Q | NA
264 *-----------------------------------------------------------------------------
265 * PLLI2S_R | NA
266 *-----------------------------------------------------------------------------
267 * I2S input clock | NA
268 *-----------------------------------------------------------------------------
269 * VDD(V) | 3.3
270 *-----------------------------------------------------------------------------
271 * Main regulator output voltage | Scale1 mode
272 *-----------------------------------------------------------------------------
273 * Flash Latency(WS) | 5
274 *-----------------------------------------------------------------------------
275 * Prefetch Buffer | ON
276 *-----------------------------------------------------------------------------
277 * Instruction cache | ON
278 *-----------------------------------------------------------------------------
279 * Data cache | ON
280 *-----------------------------------------------------------------------------
281 * Require 48MHz for USB OTG FS, | Disabled
282 * SDIO and RNG clock |
283 *-----------------------------------------------------------------------------
284 *=============================================================================
285 ******************************************************************************
286 * @attention
287 *
288 * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
289 *
290 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
291 * You may not use this file except in compliance with the License.
292 * You may obtain a copy of the License at:
293 *
294 * http://www.st.com/software_license_agreement_liberty_v2
295 *
296 * Unless required by applicable law or agreed to in writing, software
297 * distributed under the License is distributed on an "AS IS" BASIS,
298 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
299 * See the License for the specific language governing permissions and
300 * limitations under the License.
301 *
302 ******************************************************************************
303 */
304
305 /** @addtogroup CMSIS
306 * @{
307 */
308
309 /** @addtogroup stm32f4xx_system
310 * @{
311 */
312
313 /** @addtogroup STM32F4xx_System_Private_Includes
314 * @{
315 */
316
317 #include "stm32f4xx.h"
318
319 /**
320 * @}
321 */
322
323 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
324 * @{
325 */
326
327 /**
328 * @}
329 */
330
331 /** @addtogroup STM32F4xx_System_Private_Defines
332 * @{
333 */
334
335 /************************* Miscellaneous Configuration ************************/
336 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
337 on STM324xG_EVAL/STM324x7I_EVAL/STM324x9I_EVAL boards as data memory */
338 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx)
339 /* #define DATA_IN_ExtSRAM */
340 #endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx */
341
342 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
343 /* #define DATA_IN_ExtSDRAM */
344 #endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx */
345
346 #if defined(STM32F411xE)
347 /*!< Uncomment the following line if you need to clock the STM32F411xE by HSE Bypass
348 through STLINK MCO pin of STM32F103 microcontroller. The frequency cannot be changed
349 and is fixed at 8 MHz.
350 Hardware configuration needed for Nucleo Board:
351 � SB54, SB55 OFF
352 � R35 removed
353 � SB16, SB50 ON */
354 /* #define USE_HSE_BYPASS */
355
356 #if defined(USE_HSE_BYPASS)
357 #define HSE_BYPASS_INPUT_FREQUENCY 8000000
358 #endif /* USE_HSE_BYPASS */
359 #endif /* STM32F411xE */
360
361 /*!< Uncomment the following line if you need to relocate your vector Table in
362 Internal SRAM. */
363 /* #define VECT_TAB_SRAM */
364 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
365 This value must be a multiple of 0x200. */
366 /******************************************************************************/
367
368 /************************* PLL Parameters *************************************/
369 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx)
370 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
371 #define PLL_M 25
372 #elif defined (STM32F446xx)
373 #define PLL_M 8
374 #elif defined (STM32F411xE)
375
376 #if defined(USE_HSE_BYPASS)
377 #define PLL_M 8
378 #else
379 #define PLL_M 16
380 #endif /* USE_HSE_BYPASS */
381
382 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx */
383
384 /* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
385 #define PLL_Q 7
386
387 #if defined(STM32F446xx)
388 /* PLL division factor for I2S, SAI, SYSTEM and SPDIF: Clock = PLL_VCO / PLLR */
389 #define PLL_R 7
390 #endif /* STM32F446xx */
391
392 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
393 #define PLL_N 360
394 /* SYSCLK = PLL_VCO / PLL_P */
395 #define PLL_P 2
396 #endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx || STM32F446xx */
397
398 #if defined(STM32F401xx)
399 #define PLL_N 336
400 /* SYSCLK = PLL_VCO / PLL_P */
401 #define PLL_P 4
402 #endif /* STM32F401xx */
403
404 #if defined(STM32F411xE)
405 #define PLL_N 400
406 /* SYSCLK = PLL_VCO / PLL_P */
407 #define PLL_P 4
408 #endif /* STM32F411xx */
409
410 /******************************************************************************/
411
412 #ifdef PLL_M_VALUE
413 #undef PLL_M
414 #define PLL_M (PLL_M_VALUE)
415 #endif
416
417 #ifdef PLL_N_VALUE
418 #undef PLL_N
419 #define PLL_N (PLL_N_VALUE)
420 #endif
421
422 #ifdef PLL_P_VALUE
423 #undef PLL_P
424 #define PLL_P (PLL_P_VALUE)
425 #endif
426
427 /**
428 * @}
429 */
430
431 /** @addtogroup STM32F4xx_System_Private_Macros
432 * @{
433 */
434
435 /**
436 * @}
437 */
438
439 /** @addtogroup STM32F4xx_System_Private_Variables
440 * @{
441 */
442
443 #if defined(STM32F40_41xxx)
444 uint32_t SystemCoreClock = 168000000;
445 #endif /* STM32F40_41xxx */
446
447 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
448 uint32_t SystemCoreClock = 180000000;
449 #endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx */
450
451 #if defined(STM32F401xx)
452 uint32_t SystemCoreClock = 84000000;
453 #endif /* STM32F401xx */
454
455 #if defined(STM32F411xE)
456 uint32_t SystemCoreClock = 100000000;
457 #endif /* STM32F401xx */
458
459 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
460
461 /**
462 * @}
463 */
464
465 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
466 * @{
467 */
468
469 static void SetSysClock(void);
470
471 #if defined(DATA_IN_ExtSRAM) || defined(DATA_IN_ExtSDRAM)
472 static void SystemInit_ExtMemCtl(void);
473 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
474
475 /**
476 * @}
477 */
478
479 /** @addtogroup STM32F4xx_System_Private_Functions
480 * @{
481 */
482
483 /**
484 * @brief Setup the microcontroller system
485 * Initialize the Embedded Flash Interface, the PLL and update the
486 * SystemFrequency variable.
487 * @param None
488 * @retval None
489 */
SystemInit(void)490 void SystemInit(void)
491 {
492 /* FPU settings ------------------------------------------------------------*/
493 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
494 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
495 #endif
496 /* Reset the RCC clock configuration to the default reset state ------------*/
497 /* Set HSION bit */
498 RCC->CR |= (uint32_t)0x00000001;
499
500 /* Reset CFGR register */
501 RCC->CFGR = 0x00000000;
502
503 /* Reset HSEON, CSSON and PLLON bits */
504 RCC->CR &= (uint32_t)0xFEF6FFFF;
505
506 /* Reset PLLCFGR register */
507 RCC->PLLCFGR = 0x24003010;
508
509 /* Reset HSEBYP bit */
510 RCC->CR &= (uint32_t)0xFFFBFFFF;
511
512 /* Disable all interrupts */
513 RCC->CIR = 0x00000000;
514
515 #if defined(DATA_IN_ExtSRAM) || defined(DATA_IN_ExtSDRAM)
516 SystemInit_ExtMemCtl();
517 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
518
519 /* Configure the System clock source, PLL Multiplier and Divider factors,
520 AHB/APBx prescalers and Flash settings ----------------------------------*/
521 SetSysClock();
522 }
523
524 /**
525 * @brief Update SystemCoreClock variable according to Clock Register Values.
526 * The SystemCoreClock variable contains the core clock (HCLK), it can
527 * be used by the user application to setup the SysTick timer or configure
528 * other parameters.
529 *
530 * @note Each time the core clock (HCLK) changes, this function must be called
531 * to update SystemCoreClock variable value. Otherwise, any configuration
532 * based on this variable will be incorrect.
533 *
534 * @note - The system frequency computed by this function is not the real
535 * frequency in the chip. It is calculated based on the predefined
536 * constant and the selected clock source:
537 *
538 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
539 *
540 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
541 *
542 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
543 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
544 *
545 * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
546 * 16 MHz) but the real value may vary depending on the variations
547 * in voltage and temperature.
548 *
549 * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
550 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
551 * frequency of the crystal used. Otherwise, this function may
552 * have wrong result.
553 *
554 * - The result of this function could be not correct when using fractional
555 * value for HSE crystal.
556 *
557 * @param None
558 * @retval None
559 */
SystemCoreClockUpdate(void)560 void SystemCoreClockUpdate(void)
561 {
562 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
563 #if defined(STM32F446xx)
564 uint32_t pllr = 2;
565 #endif /* STM32F446xx */
566 /* Get SYSCLK source -------------------------------------------------------*/
567 tmp = RCC->CFGR & RCC_CFGR_SWS;
568
569 switch (tmp)
570 {
571 case 0x00: /* HSI used as system clock source */
572 SystemCoreClock = HSI_VALUE;
573 break;
574 case 0x04: /* HSE used as system clock source */
575 SystemCoreClock = HSE_VALUE;
576 break;
577 case 0x08: /* PLL P used as system clock source */
578 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
579 SYSCLK = PLL_VCO / PLL_P
580 */
581 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
582 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
583
584 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F446xx)
585 if (pllsource != 0)
586 {
587 /* HSE used as PLL clock source */
588 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
589 }
590 else
591 {
592 /* HSI used as PLL clock source */
593 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
594 }
595 #elif defined(STM32F411xE)
596 #if defined(USE_HSE_BYPASS)
597 if (pllsource != 0)
598 {
599 /* HSE used as PLL clock source */
600 pllvco = (HSE_BYPASS_INPUT_FREQUENCY / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
601 }
602 #else
603 if (pllsource == 0)
604 {
605 /* HSI used as PLL clock source */
606 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
607 }
608 #endif /* USE_HSE_BYPASS */
609 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F446xx */
610 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
611 SystemCoreClock = pllvco/pllp;
612 break;
613 #if defined(STM32F446xx)
614 case 0x0C: /* PLL R used as system clock source */
615 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
616 SYSCLK = PLL_VCO / PLL_R
617 */
618 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
619 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
620 if (pllsource != 0)
621 {
622 /* HSE used as PLL clock source */
623 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
624 }
625 else
626 {
627 /* HSI used as PLL clock source */
628 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
629 }
630
631 pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >>28) + 1 ) *2;
632 SystemCoreClock = pllvco/pllr;
633 break;
634 #endif /* STM32F446xx */
635 default:
636 SystemCoreClock = HSI_VALUE;
637 break;
638 }
639 /* Compute HCLK frequency --------------------------------------------------*/
640 /* Get HCLK prescaler */
641 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
642 /* HCLK frequency */
643 SystemCoreClock >>= tmp;
644 }
645
646 /**
647 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
648 * AHB/APBx prescalers and Flash settings
649 * @Note This function should be called only once the RCC clock configuration
650 * is reset to the default reset state (done in SystemInit() function).
651 * @param None
652 * @retval None
653 */
SetSysClock(void)654 static void SetSysClock(void)
655 {
656 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F446xx)
657 /******************************************************************************/
658 /* PLL (clocked by HSE) used as System clock source */
659 /******************************************************************************/
660 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
661
662 /* Enable HSE */
663 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
664
665 /* Wait till HSE is ready and if Time out is reached exit */
666 do
667 {
668 HSEStatus = RCC->CR & RCC_CR_HSERDY;
669 StartUpCounter++;
670 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
671
672 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
673 {
674 HSEStatus = (uint32_t)0x01;
675 }
676 else
677 {
678 HSEStatus = (uint32_t)0x00;
679 }
680
681 if (HSEStatus == (uint32_t)0x01)
682 {
683 /* Select regulator voltage output Scale 1 mode */
684 RCC->APB1ENR |= RCC_APB1ENR_PWREN;
685 PWR->CR |= PWR_CR_VOS;
686
687 /* HCLK = SYSCLK / 1*/
688 RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
689
690 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
691 /* PCLK2 = HCLK / 2*/
692 RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
693
694 /* PCLK1 = HCLK / 4*/
695 RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
696 #endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx || STM32F446xx */
697
698 #if defined(STM32F401xx)
699 /* PCLK2 = HCLK / 2*/
700 RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
701
702 /* PCLK1 = HCLK / 4*/
703 RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
704 #endif /* STM32F401xx */
705
706 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx)
707 /* Configure the main PLL */
708 RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
709 (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
710 #endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx || STM32F401xx */
711
712 #if defined(STM32F446xx)
713 /* Configure the main PLL */
714 RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
715 (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24) | (PLL_R << 28);
716 #endif /* STM32F446xx */
717
718 /* Enable the main PLL */
719 RCC->CR |= RCC_CR_PLLON;
720
721 /* Wait till the main PLL is ready */
722 while((RCC->CR & RCC_CR_PLLRDY) == 0)
723 {
724 }
725
726 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
727 /* Enable the Over-drive to extend the clock frequency to 180 Mhz */
728 PWR->CR |= PWR_CR_ODEN;
729 while((PWR->CSR & PWR_CSR_ODRDY) == 0)
730 {
731 }
732 PWR->CR |= PWR_CR_ODSWEN;
733 while((PWR->CSR & PWR_CSR_ODSWRDY) == 0)
734 {
735 }
736 /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
737 FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
738 #endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx */
739
740 #if defined(STM32F40_41xxx)
741 /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
742 FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
743 #endif /* STM32F40_41xxx */
744
745 #if defined(STM32F401xx)
746 /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
747 FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
748 #endif /* STM32F401xx */
749
750 /* Select the main PLL as system clock source */
751 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
752 RCC->CFGR |= RCC_CFGR_SW_PLL;
753
754 /* Wait till the main PLL is used as system clock source */
755 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
756 }
757 else
758 { /* If HSE fails to start-up, the application will have wrong clock
759 configuration. User can add here some code to deal with this error */
760 }
761 #elif defined(STM32F411xE)
762 #if defined(USE_HSE_BYPASS)
763 /******************************************************************************/
764 /* PLL (clocked by HSE) used as System clock source */
765 /******************************************************************************/
766 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
767
768 /* Enable HSE and HSE BYPASS */
769 RCC->CR |= ((uint32_t)RCC_CR_HSEON | RCC_CR_HSEBYP);
770
771 /* Wait till HSE is ready and if Time out is reached exit */
772 do
773 {
774 HSEStatus = RCC->CR & RCC_CR_HSERDY;
775 StartUpCounter++;
776 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
777
778 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
779 {
780 HSEStatus = (uint32_t)0x01;
781 }
782 else
783 {
784 HSEStatus = (uint32_t)0x00;
785 }
786
787 if (HSEStatus == (uint32_t)0x01)
788 {
789 /* Select regulator voltage output Scale 1 mode */
790 RCC->APB1ENR |= RCC_APB1ENR_PWREN;
791 PWR->CR |= PWR_CR_VOS;
792
793 /* HCLK = SYSCLK / 1*/
794 RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
795
796 /* PCLK2 = HCLK / 2*/
797 RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
798
799 /* PCLK1 = HCLK / 4*/
800 RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
801
802 /* Configure the main PLL */
803 RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
804 (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
805
806 /* Enable the main PLL */
807 RCC->CR |= RCC_CR_PLLON;
808
809 /* Wait till the main PLL is ready */
810 while((RCC->CR & RCC_CR_PLLRDY) == 0)
811 {
812 }
813
814 /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
815 FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
816
817 /* Select the main PLL as system clock source */
818 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
819 RCC->CFGR |= RCC_CFGR_SW_PLL;
820
821 /* Wait till the main PLL is used as system clock source */
822 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
823 {
824 }
825 }
826 else
827 { /* If HSE fails to start-up, the application will have wrong clock
828 configuration. User can add here some code to deal with this error */
829 }
830 #else /* HSI will be used as PLL clock source */
831 /* Select regulator voltage output Scale 1 mode */
832 RCC->APB1ENR |= RCC_APB1ENR_PWREN;
833 PWR->CR |= PWR_CR_VOS;
834
835 /* HCLK = SYSCLK / 1*/
836 RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
837
838 /* PCLK2 = HCLK / 2*/
839 RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
840
841 /* PCLK1 = HCLK / 4*/
842 RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
843
844 /* Configure the main PLL */
845 RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | (PLL_Q << 24);
846
847 /* Enable the main PLL */
848 RCC->CR |= RCC_CR_PLLON;
849
850 /* Wait till the main PLL is ready */
851 while((RCC->CR & RCC_CR_PLLRDY) == 0)
852 {
853 }
854
855 /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
856 FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
857
858 /* Select the main PLL as system clock source */
859 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
860 RCC->CFGR |= RCC_CFGR_SW_PLL;
861
862 /* Wait till the main PLL is used as system clock source */
863 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
864 {
865 }
866 #endif /* USE_HSE_BYPASS */
867 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx */
868 }
869
870 /**
871 * @brief Setup the external memory controller. Called in startup_stm32f4xx.s
872 * before jump to __main
873 * @param None
874 * @retval None
875 */
876 #ifdef DATA_IN_ExtSRAM
877 /**
878 * @brief Setup the external memory controller.
879 * Called in startup_stm32f4xx.s before jump to main.
880 * This function configures the external SRAM mounted on STM324xG_EVAL/STM324x7I boards
881 * This SRAM will be used as program data memory (including heap and stack).
882 * @param None
883 * @retval None
884 */
SystemInit_ExtMemCtl(void)885 void SystemInit_ExtMemCtl(void)
886 {
887 /*-- GPIOs Configuration -----------------------------------------------------*/
888 /*
889 +-------------------+--------------------+------------------+--------------+
890 + SRAM pins assignment +
891 +-------------------+--------------------+------------------+--------------+
892 | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 |
893 | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 |
894 | PD4 <-> FMC_NOE | PE3 <-> FMC_A19 | PF2 <-> FMC_A2 | PG2 <-> FMC_A12 |
895 | PD5 <-> FMC_NWE | PE4 <-> FMC_A20 | PF3 <-> FMC_A3 | PG3 <-> FMC_A13 |
896 | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF4 <-> FMC_A4 | PG4 <-> FMC_A14 |
897 | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF5 <-> FMC_A5 | PG5 <-> FMC_A15 |
898 | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF12 <-> FMC_A6 | PG9 <-> FMC_NE2 |
899 | PD11 <-> FMC_A16 | PE10 <-> FMC_D7 | PF13 <-> FMC_A7 |-----------------+
900 | PD12 <-> FMC_A17 | PE11 <-> FMC_D8 | PF14 <-> FMC_A8 |
901 | PD13 <-> FMC_A18 | PE12 <-> FMC_D9 | PF15 <-> FMC_A9 |
902 | PD14 <-> FMC_D0 | PE13 <-> FMC_D10 |-----------------+
903 | PD15 <-> FMC_D1 | PE14 <-> FMC_D11 |
904 | | PE15 <-> FMC_D12 |
905 +------------------+------------------+
906 */
907 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
908 RCC->AHB1ENR |= 0x00000078;
909
910 /* Connect PDx pins to FMC Alternate function */
911 GPIOD->AFR[0] = 0x00cc00cc;
912 GPIOD->AFR[1] = 0xcccccccc;
913 /* Configure PDx pins in Alternate function mode */
914 GPIOD->MODER = 0xaaaa0a0a;
915 /* Configure PDx pins speed to 100 MHz */
916 GPIOD->OSPEEDR = 0xffff0f0f;
917 /* Configure PDx pins Output type to push-pull */
918 GPIOD->OTYPER = 0x00000000;
919 /* No pull-up, pull-down for PDx pins */
920 GPIOD->PUPDR = 0x00000000;
921
922 /* Connect PEx pins to FMC Alternate function */
923 GPIOE->AFR[0] = 0xcccccccc;
924 GPIOE->AFR[1] = 0xcccccccc;
925 /* Configure PEx pins in Alternate function mode */
926 GPIOE->MODER = 0xaaaaaaaa;
927 /* Configure PEx pins speed to 100 MHz */
928 GPIOE->OSPEEDR = 0xffffffff;
929 /* Configure PEx pins Output type to push-pull */
930 GPIOE->OTYPER = 0x00000000;
931 /* No pull-up, pull-down for PEx pins */
932 GPIOE->PUPDR = 0x00000000;
933
934 /* Connect PFx pins to FMC Alternate function */
935 GPIOF->AFR[0] = 0x00cccccc;
936 GPIOF->AFR[1] = 0xcccc0000;
937 /* Configure PFx pins in Alternate function mode */
938 GPIOF->MODER = 0xaa000aaa;
939 /* Configure PFx pins speed to 100 MHz */
940 GPIOF->OSPEEDR = 0xff000fff;
941 /* Configure PFx pins Output type to push-pull */
942 GPIOF->OTYPER = 0x00000000;
943 /* No pull-up, pull-down for PFx pins */
944 GPIOF->PUPDR = 0x00000000;
945
946 /* Connect PGx pins to FMC Alternate function */
947 GPIOG->AFR[0] = 0x00cccccc;
948 GPIOG->AFR[1] = 0x000000c0;
949 /* Configure PGx pins in Alternate function mode */
950 GPIOG->MODER = 0x00080aaa;
951 /* Configure PGx pins speed to 100 MHz */
952 GPIOG->OSPEEDR = 0x000c0fff;
953 /* Configure PGx pins Output type to push-pull */
954 GPIOG->OTYPER = 0x00000000;
955 /* No pull-up, pull-down for PGx pins */
956 GPIOG->PUPDR = 0x00000000;
957
958 /*-- FMC Configuration ------------------------------------------------------*/
959 /* Enable the FMC/FSMC interface clock */
960 RCC->AHB3ENR |= 0x00000001;
961
962 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
963 /* Configure and enable Bank1_SRAM2 */
964 FMC_Bank1->BTCR[2] = 0x00001011;
965 FMC_Bank1->BTCR[3] = 0x00000201;
966 FMC_Bank1E->BWTR[2] = 0x0fffffff;
967 #endif /* STM32F427_437xx || STM32F429_439xx */
968
969 #if defined(STM32F40_41xxx)
970 /* Configure and enable Bank1_SRAM2 */
971 FSMC_Bank1->BTCR[2] = 0x00001011;
972 FSMC_Bank1->BTCR[3] = 0x00000201;
973 FSMC_Bank1E->BWTR[2] = 0x0fffffff;
974 #endif /* STM32F40_41xxx */
975
976 /*
977 Bank1_SRAM2 is configured as follow:
978 In case of FSMC configuration
979 NORSRAMTimingStructure.FSMC_AddressSetupTime = 1;
980 NORSRAMTimingStructure.FSMC_AddressHoldTime = 0;
981 NORSRAMTimingStructure.FSMC_DataSetupTime = 2;
982 NORSRAMTimingStructure.FSMC_BusTurnAroundDuration = 0;
983 NORSRAMTimingStructure.FSMC_CLKDivision = 0;
984 NORSRAMTimingStructure.FSMC_DataLatency = 0;
985 NORSRAMTimingStructure.FSMC_AccessMode = FMC_AccessMode_A;
986
987 FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
988 FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
989 FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
990 FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
991 FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
992 FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
993 FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
994 FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
995 FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
996 FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
997 FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
998 FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
999 FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
1000 FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &NORSRAMTimingStructure;
1001 FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &NORSRAMTimingStructure;
1002
1003 In case of FMC configuration
1004 NORSRAMTimingStructure.FMC_AddressSetupTime = 1;
1005 NORSRAMTimingStructure.FMC_AddressHoldTime = 0;
1006 NORSRAMTimingStructure.FMC_DataSetupTime = 2;
1007 NORSRAMTimingStructure.FMC_BusTurnAroundDuration = 0;
1008 NORSRAMTimingStructure.FMC_CLKDivision = 0;
1009 NORSRAMTimingStructure.FMC_DataLatency = 0;
1010 NORSRAMTimingStructure.FMC_AccessMode = FMC_AccessMode_A;
1011
1012 FMC_NORSRAMInitStructure.FMC_Bank = FMC_Bank1_NORSRAM2;
1013 FMC_NORSRAMInitStructure.FMC_DataAddressMux = FMC_DataAddressMux_Disable;
1014 FMC_NORSRAMInitStructure.FMC_MemoryType = FMC_MemoryType_SRAM;
1015 FMC_NORSRAMInitStructure.FMC_MemoryDataWidth = FMC_MemoryDataWidth_16b;
1016 FMC_NORSRAMInitStructure.FMC_BurstAccessMode = FMC_BurstAccessMode_Disable;
1017 FMC_NORSRAMInitStructure.FMC_AsynchronousWait = FMC_AsynchronousWait_Disable;
1018 FMC_NORSRAMInitStructure.FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low;
1019 FMC_NORSRAMInitStructure.FMC_WrapMode = FMC_WrapMode_Disable;
1020 FMC_NORSRAMInitStructure.FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState;
1021 FMC_NORSRAMInitStructure.FMC_WriteOperation = FMC_WriteOperation_Enable;
1022 FMC_NORSRAMInitStructure.FMC_WaitSignal = FMC_WaitSignal_Disable;
1023 FMC_NORSRAMInitStructure.FMC_ExtendedMode = FMC_ExtendedMode_Disable;
1024 FMC_NORSRAMInitStructure.FMC_WriteBurst = FMC_WriteBurst_Disable;
1025 FMC_NORSRAMInitStructure.FMC_ContinousClock = FMC_CClock_SyncOnly;
1026 FMC_NORSRAMInitStructure.FMC_ReadWriteTimingStruct = &NORSRAMTimingStructure;
1027 FMC_NORSRAMInitStructure.FMC_WriteTimingStruct = &NORSRAMTimingStructure;
1028 */
1029
1030 }
1031 #endif /* DATA_IN_ExtSRAM */
1032
1033 #ifdef DATA_IN_ExtSDRAM
1034 /**
1035 * @brief Setup the external memory controller.
1036 * Called in startup_stm32f4xx.s before jump to main.
1037 * This function configures the external SDRAM mounted on STM324x9I_EVAL board
1038 * This SDRAM will be used as program data memory (including heap and stack).
1039 * @param None
1040 * @retval None
1041 */
SystemInit_ExtMemCtl(void)1042 void SystemInit_ExtMemCtl(void)
1043 {
1044 register uint32_t tmpreg = 0, timeout = 0xFFFF;
1045 register uint32_t index;
1046
1047 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
1048 clock */
1049 RCC->AHB1ENR |= 0x000001FC;
1050
1051 /* Connect PCx pins to FMC Alternate function */
1052 GPIOC->AFR[0] = 0x0000000c;
1053 GPIOC->AFR[1] = 0x00007700;
1054 /* Configure PCx pins in Alternate function mode */
1055 GPIOC->MODER = 0x00a00002;
1056 /* Configure PCx pins speed to 50 MHz */
1057 GPIOC->OSPEEDR = 0x00a00002;
1058 /* Configure PCx pins Output type to push-pull */
1059 GPIOC->OTYPER = 0x00000000;
1060 /* No pull-up, pull-down for PCx pins */
1061 GPIOC->PUPDR = 0x00500000;
1062
1063 /* Connect PDx pins to FMC Alternate function */
1064 GPIOD->AFR[0] = 0x000000CC;
1065 GPIOD->AFR[1] = 0xCC000CCC;
1066 /* Configure PDx pins in Alternate function mode */
1067 GPIOD->MODER = 0xA02A000A;
1068 /* Configure PDx pins speed to 50 MHz */
1069 GPIOD->OSPEEDR = 0xA02A000A;
1070 /* Configure PDx pins Output type to push-pull */
1071 GPIOD->OTYPER = 0x00000000;
1072 /* No pull-up, pull-down for PDx pins */
1073 GPIOD->PUPDR = 0x00000000;
1074
1075 /* Connect PEx pins to FMC Alternate function */
1076 GPIOE->AFR[0] = 0xC00000CC;
1077 GPIOE->AFR[1] = 0xCCCCCCCC;
1078 /* Configure PEx pins in Alternate function mode */
1079 GPIOE->MODER = 0xAAAA800A;
1080 /* Configure PEx pins speed to 50 MHz */
1081 GPIOE->OSPEEDR = 0xAAAA800A;
1082 /* Configure PEx pins Output type to push-pull */
1083 GPIOE->OTYPER = 0x00000000;
1084 /* No pull-up, pull-down for PEx pins */
1085 GPIOE->PUPDR = 0x00000000;
1086
1087 /* Connect PFx pins to FMC Alternate function */
1088 GPIOF->AFR[0] = 0xcccccccc;
1089 GPIOF->AFR[1] = 0xcccccccc;
1090 /* Configure PFx pins in Alternate function mode */
1091 GPIOF->MODER = 0xAA800AAA;
1092 /* Configure PFx pins speed to 50 MHz */
1093 GPIOF->OSPEEDR = 0xAA800AAA;
1094 /* Configure PFx pins Output type to push-pull */
1095 GPIOF->OTYPER = 0x00000000;
1096 /* No pull-up, pull-down for PFx pins */
1097 GPIOF->PUPDR = 0x00000000;
1098
1099 /* Connect PGx pins to FMC Alternate function */
1100 GPIOG->AFR[0] = 0xcccccccc;
1101 GPIOG->AFR[1] = 0xcccccccc;
1102 /* Configure PGx pins in Alternate function mode */
1103 GPIOG->MODER = 0xaaaaaaaa;
1104 /* Configure PGx pins speed to 50 MHz */
1105 GPIOG->OSPEEDR = 0xaaaaaaaa;
1106 /* Configure PGx pins Output type to push-pull */
1107 GPIOG->OTYPER = 0x00000000;
1108 /* No pull-up, pull-down for PGx pins */
1109 GPIOG->PUPDR = 0x00000000;
1110
1111 /* Connect PHx pins to FMC Alternate function */
1112 GPIOH->AFR[0] = 0x00C0CC00;
1113 GPIOH->AFR[1] = 0xCCCCCCCC;
1114 /* Configure PHx pins in Alternate function mode */
1115 GPIOH->MODER = 0xAAAA08A0;
1116 /* Configure PHx pins speed to 50 MHz */
1117 GPIOH->OSPEEDR = 0xAAAA08A0;
1118 /* Configure PHx pins Output type to push-pull */
1119 GPIOH->OTYPER = 0x00000000;
1120 /* No pull-up, pull-down for PHx pins */
1121 GPIOH->PUPDR = 0x00000000;
1122
1123 /* Connect PIx pins to FMC Alternate function */
1124 GPIOI->AFR[0] = 0xCCCCCCCC;
1125 GPIOI->AFR[1] = 0x00000CC0;
1126 /* Configure PIx pins in Alternate function mode */
1127 GPIOI->MODER = 0x0028AAAA;
1128 /* Configure PIx pins speed to 50 MHz */
1129 GPIOI->OSPEEDR = 0x0028AAAA;
1130 /* Configure PIx pins Output type to push-pull */
1131 GPIOI->OTYPER = 0x00000000;
1132 /* No pull-up, pull-down for PIx pins */
1133 GPIOI->PUPDR = 0x00000000;
1134
1135 /*-- FMC Configuration ------------------------------------------------------*/
1136 /* Enable the FMC interface clock */
1137 RCC->AHB3ENR |= 0x00000001;
1138
1139 /* Configure and enable SDRAM bank1 */
1140 FMC_Bank5_6->SDCR[0] = 0x000039D0;
1141 FMC_Bank5_6->SDTR[0] = 0x01115351;
1142
1143 /* SDRAM initialization sequence */
1144 /* Clock enable command */
1145 FMC_Bank5_6->SDCMR = 0x00000011;
1146 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
1147 while((tmpreg != 0) & (timeout-- > 0))
1148 {
1149 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
1150 }
1151
1152 /* Delay */
1153 for (index = 0; index<1000; index++);
1154
1155 /* PALL command */
1156 FMC_Bank5_6->SDCMR = 0x00000012;
1157 timeout = 0xFFFF;
1158 while((tmpreg != 0) & (timeout-- > 0))
1159 {
1160 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
1161 }
1162
1163 /* Auto refresh command */
1164 FMC_Bank5_6->SDCMR = 0x00000073;
1165 timeout = 0xFFFF;
1166 while((tmpreg != 0) & (timeout-- > 0))
1167 {
1168 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
1169 }
1170
1171 /* MRD register program */
1172 FMC_Bank5_6->SDCMR = 0x00046014;
1173 timeout = 0xFFFF;
1174 while((tmpreg != 0) & (timeout-- > 0))
1175 {
1176 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
1177 }
1178
1179 /* Set refresh count */
1180 tmpreg = FMC_Bank5_6->SDRTR;
1181 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
1182
1183 /* Disable write protection */
1184 tmpreg = FMC_Bank5_6->SDCR[0];
1185 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
1186
1187 /*
1188 Bank1_SDRAM is configured as follow:
1189
1190 FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2;
1191 FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 6;
1192 FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4;
1193 FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 6;
1194 FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2;
1195 FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2;
1196 FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2;
1197
1198 FMC_SDRAMInitStructure.FMC_Bank = SDRAM_BANK;
1199 FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
1200 FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_11b;
1201 FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b;
1202 FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;
1203 FMC_SDRAMInitStructure.FMC_CASLatency = FMC_CAS_Latency_3;
1204 FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;
1205 FMC_SDRAMInitStructure.FMC_SDClockPeriod = FMC_SDClock_Period_2;
1206 FMC_SDRAMInitStructure.FMC_ReadBurst = FMC_Read_Burst_disable;
1207 FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1;
1208 FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;
1209 */
1210
1211 }
1212 #endif /* DATA_IN_ExtSDRAM */
1213
1214
1215 /**
1216 * @}
1217 */
1218
1219 /**
1220 * @}
1221 */
1222
1223 /**
1224 * @}
1225 */
1226 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1227