1 /** 2 ****************************************************************************** 3 * @file stm32f7xx_hal_cec.h 4 * @author MCD Application Team 5 * @version V1.0.1 6 * @date 25-June-2015 7 * @brief Header file of CEC HAL module. 8 ****************************************************************************** 9 * @attention 10 * 11 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 12 * 13 * Redistribution and use in source and binary forms, with or without modification, 14 * are permitted provided that the following conditions are met: 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright notice, 18 * this list of conditions and the following disclaimer in the documentation 19 * and/or other materials provided with the distribution. 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 ****************************************************************************** 36 */ 37 38 /* Define to prevent recursive inclusion -------------------------------------*/ 39 #ifndef __STM32F7xx_HAL_CEC_H 40 #define __STM32F7xx_HAL_CEC_H 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 /* Includes ------------------------------------------------------------------*/ 47 #include "stm32f7xx_hal_def.h" 48 49 /** @addtogroup STM32F7xx_HAL_Driver 50 * @{ 51 */ 52 53 /** @addtogroup CEC 54 * @{ 55 */ 56 57 /* Exported types ------------------------------------------------------------*/ 58 /** @defgroup CEC_Exported_Types CEC Exported Types 59 * @{ 60 */ 61 62 /** 63 * @brief CEC Init Structure definition 64 */ 65 typedef struct { 66 uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time. 67 It can be one of @ref CEC_Signal_Free_Time 68 and belongs to the set {0,...,7} where 69 0x0 is the default configuration 70 else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */ 71 72 uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms, 73 it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE 74 or CEC_EXTENDED_TOLERANCE */ 75 76 uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception. 77 CEC_NO_RX_STOP_ON_BRE: reception is not stopped. 78 CEC_RX_STOP_ON_BRE: reception is stopped. */ 79 80 uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the 81 CEC line upon Bit Rising Error detection. 82 CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation. 83 CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */ 84 85 uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the 86 CEC line upon Long Bit Period Error detection. 87 CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation. 88 CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */ 89 90 uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line 91 upon an error detected on a broadcast message. 92 93 It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values: 94 95 1) CEC_BROADCASTERROR_ERRORBIT_GENERATION. 96 a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE 97 and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION. 98 b) LBPE detection: error-bit generation on the CEC line 99 if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION. 100 101 2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION. 102 no error-bit generation in case neither a) nor b) are satisfied. Additionally, 103 there is no error-bit generation in case of Short Bit Period Error detection in 104 a broadcast message while LSTN bit is set. */ 105 106 uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts. 107 CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software. 108 CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */ 109 110 uint32_t OwnAddress; /*!< Set OAR field, specifies CEC device address within a 15-bit long field */ 111 112 uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values: 113 114 CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its 115 own address (OAR). Messages addressed to different destination are ignored. 116 Broadcast messages are always received. 117 118 CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own 119 address (OAR) with positive acknowledge. Messages addressed to different destination 120 are received, but without interfering with the CEC bus: no acknowledge sent. */ 121 122 uint8_t InitiatorAddress; /* Initiator address (source logical address, sent in each header) */ 123 124 } CEC_InitTypeDef; 125 126 /** 127 * @brief HAL CEC State structures definition 128 */ 129 typedef enum { 130 HAL_CEC_STATE_RESET = 0x00, /*!< Peripheral Reset state */ 131 HAL_CEC_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ 132 HAL_CEC_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ 133 HAL_CEC_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */ 134 HAL_CEC_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */ 135 HAL_CEC_STATE_STANDBY_RX = 0x05, /*!< IP ready to receive, doesn't prevent IP to transmit */ 136 HAL_CEC_STATE_TIMEOUT = 0x06, /*!< Timeout state */ 137 HAL_CEC_STATE_ERROR = 0x07 /*!< State Error */ 138 } HAL_CEC_StateTypeDef; 139 140 /** 141 * @brief CEC handle Structure definition 142 */ 143 typedef struct { 144 CEC_TypeDef *Instance; /* CEC registers base address */ 145 146 CEC_InitTypeDef Init; /* CEC communication parameters */ 147 148 uint8_t *pTxBuffPtr; /* Pointer to CEC Tx transfer Buffer */ 149 150 uint16_t TxXferCount; /* CEC Tx Transfer Counter */ 151 152 uint8_t *pRxBuffPtr; /* Pointer to CEC Rx transfer Buffer */ 153 154 uint16_t RxXferSize; /* CEC Rx Transfer size, 0: header received only */ 155 156 uint32_t ErrorCode; /* For errors handling purposes, copy of ISR register 157 in case error is reported */ 158 159 HAL_LockTypeDef Lock; /* Locking object */ 160 161 HAL_CEC_StateTypeDef State; /* CEC communication state */ 162 163 } CEC_HandleTypeDef; 164 /** 165 * @} 166 */ 167 168 /* Exported constants --------------------------------------------------------*/ 169 /** @defgroup CEC_Exported_Constants CEC Exported Constants 170 * @{ 171 */ 172 173 /** @defgroup CEC_Error_Code CEC Error Code 174 * @{ 175 */ 176 #define HAL_CEC_ERROR_NONE (uint32_t) 0x0 /*!< no error */ 177 #define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */ 178 #define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */ 179 #define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */ 180 #define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */ 181 #define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */ 182 #define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */ 183 #define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */ 184 #define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */ 185 #define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */ 186 /** 187 * @} 188 */ 189 190 /** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter 191 * @{ 192 */ 193 #define CEC_DEFAULT_SFT ((uint32_t)0x00000000) 194 #define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001) 195 #define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002) 196 #define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003) 197 #define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004) 198 #define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005) 199 #define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006) 200 #define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007) 201 /** 202 * @} 203 */ 204 205 /** @defgroup CEC_Tolerance CEC Receiver Tolerance 206 * @{ 207 */ 208 #define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000) 209 #define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL) 210 /** 211 * @} 212 */ 213 214 /** @defgroup CEC_BRERxStop CEC Reception Stop on Error 215 * @{ 216 */ 217 #define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000) 218 #define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP) 219 /** 220 * @} 221 */ 222 223 /** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported 224 * @{ 225 */ 226 #define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000) 227 #define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN) 228 /** 229 * @} 230 */ 231 232 /** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported 233 * @{ 234 */ 235 #define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000) 236 #define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN) 237 /** 238 * @} 239 */ 240 241 /** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message 242 * @{ 243 */ 244 #define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000) 245 #define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN) 246 /** 247 * @} 248 */ 249 250 /** @defgroup CEC_SFT_Option CEC Signal Free Time start option 251 * @{ 252 */ 253 #define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000) 254 #define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT) 255 /** 256 * @} 257 */ 258 259 /** @defgroup CEC_Listening_Mode CEC Listening mode option 260 * @{ 261 */ 262 #define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000) 263 #define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN) 264 /** 265 * @} 266 */ 267 268 /** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register 269 * @{ 270 */ 271 #define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16) 272 /** 273 * @} 274 */ 275 276 /** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header 277 * @{ 278 */ 279 #define CEC_INITIATOR_LSB_POS ((uint32_t) 4) 280 /** 281 * @} 282 */ 283 284 /** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition 285 * @{ 286 */ 287 #define CEC_IT_TXACKE CEC_IER_TXACKEIE 288 #define CEC_IT_TXERR CEC_IER_TXERRIE 289 #define CEC_IT_TXUDR CEC_IER_TXUDRIE 290 #define CEC_IT_TXEND CEC_IER_TXENDIE 291 #define CEC_IT_TXBR CEC_IER_TXBRIE 292 #define CEC_IT_ARBLST CEC_IER_ARBLSTIE 293 #define CEC_IT_RXACKE CEC_IER_RXACKEIE 294 #define CEC_IT_LBPE CEC_IER_LBPEIE 295 #define CEC_IT_SBPE CEC_IER_SBPEIE 296 #define CEC_IT_BRE CEC_IER_BREIE 297 #define CEC_IT_RXOVR CEC_IER_RXOVRIE 298 #define CEC_IT_RXEND CEC_IER_RXENDIE 299 #define CEC_IT_RXBR CEC_IER_RXBRIE 300 /** 301 * @} 302 */ 303 304 /** @defgroup CEC_Flags_Definitions CEC Flags definition 305 * @{ 306 */ 307 #define CEC_FLAG_TXACKE CEC_ISR_TXACKE 308 #define CEC_FLAG_TXERR CEC_ISR_TXERR 309 #define CEC_FLAG_TXUDR CEC_ISR_TXUDR 310 #define CEC_FLAG_TXEND CEC_ISR_TXEND 311 #define CEC_FLAG_TXBR CEC_ISR_TXBR 312 #define CEC_FLAG_ARBLST CEC_ISR_ARBLST 313 #define CEC_FLAG_RXACKE CEC_ISR_RXACKE 314 #define CEC_FLAG_LBPE CEC_ISR_LBPE 315 #define CEC_FLAG_SBPE CEC_ISR_SBPE 316 #define CEC_FLAG_BRE CEC_ISR_BRE 317 #define CEC_FLAG_RXOVR CEC_ISR_RXOVR 318 #define CEC_FLAG_RXEND CEC_ISR_RXEND 319 #define CEC_FLAG_RXBR CEC_ISR_RXBR 320 /** 321 * @} 322 */ 323 324 /** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags 325 * @{ 326 */ 327 #define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\ 328 CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE) 329 /** 330 * @} 331 */ 332 333 /** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag 334 * @{ 335 */ 336 #define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE) 337 /** 338 * @} 339 */ 340 341 /** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag 342 * @{ 343 */ 344 #define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE) 345 /** 346 * @} 347 */ 348 349 /** 350 * @} 351 */ 352 353 /* Exported macros -----------------------------------------------------------*/ 354 /** @defgroup CEC_Exported_Macros CEC Exported Macros 355 * @{ 356 */ 357 358 /** @brief Reset CEC handle state 359 * @param __HANDLE__: CEC handle. 360 * @retval None 361 */ 362 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CEC_STATE_RESET) 363 364 /** @brief Checks whether or not the specified CEC interrupt flag is set. 365 * @param __HANDLE__: specifies the CEC Handle. 366 * @param __FLAG__: specifies the flag to check. 367 * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error 368 * @arg CEC_FLAG_TXERR: Tx Error. 369 * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. 370 * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte). 371 * @arg CEC_FLAG_TXBR: Tx-Byte Request. 372 * @arg CEC_FLAG_ARBLST: Arbitration Lost 373 * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge 374 * @arg CEC_FLAG_LBPE: Rx Long period Error 375 * @arg CEC_FLAG_SBPE: Rx Short period Error 376 * @arg CEC_FLAG_BRE: Rx Bit Rising Error 377 * @arg CEC_FLAG_RXOVR: Rx Overrun. 378 * @arg CEC_FLAG_RXEND: End Of Reception. 379 * @arg CEC_FLAG_RXBR: Rx-Byte Received. 380 * @retval ITStatus 381 */ 382 #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) 383 384 /** @brief Clears the interrupt or status flag when raised (write at 1) 385 * @param __HANDLE__: specifies the CEC Handle. 386 * @param __FLAG__: specifies the interrupt/status flag to clear. 387 * This parameter can be one of the following values: 388 * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error 389 * @arg CEC_FLAG_TXERR: Tx Error. 390 * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. 391 * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte). 392 * @arg CEC_FLAG_TXBR: Tx-Byte Request. 393 * @arg CEC_FLAG_ARBLST: Arbitration Lost 394 * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge 395 * @arg CEC_FLAG_LBPE: Rx Long period Error 396 * @arg CEC_FLAG_SBPE: Rx Short period Error 397 * @arg CEC_FLAG_BRE: Rx Bit Rising Error 398 * @arg CEC_FLAG_RXOVR: Rx Overrun. 399 * @arg CEC_FLAG_RXEND: End Of Reception. 400 * @arg CEC_FLAG_RXBR: Rx-Byte Received. 401 * @retval none 402 */ 403 #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__)) 404 405 /** @brief Enables the specified CEC interrupt. 406 * @param __HANDLE__: specifies the CEC Handle. 407 * @param __INTERRUPT__: specifies the CEC interrupt to enable. 408 * This parameter can be one of the following values: 409 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable 410 * @arg CEC_IT_TXERR: Tx Error IT Enable 411 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable 412 * @arg CEC_IT_TXEND: End of transmission IT Enable 413 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable 414 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable 415 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable 416 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable 417 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable 418 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable 419 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable 420 * @arg CEC_IT_RXEND: End Of Reception IT Enable 421 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable 422 * @retval none 423 */ 424 #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 425 426 /** @brief Disables the specified CEC interrupt. 427 * @param __HANDLE__: specifies the CEC Handle. 428 * @param __INTERRUPT__: specifies the CEC interrupt to disable. 429 * This parameter can be one of the following values: 430 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable 431 * @arg CEC_IT_TXERR: Tx Error IT Enable 432 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable 433 * @arg CEC_IT_TXEND: End of transmission IT Enable 434 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable 435 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable 436 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable 437 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable 438 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable 439 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable 440 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable 441 * @arg CEC_IT_RXEND: End Of Reception IT Enable 442 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable 443 * @retval none 444 */ 445 #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) 446 447 /** @brief Checks whether or not the specified CEC interrupt is enabled. 448 * @param __HANDLE__: specifies the CEC Handle. 449 * @param __INTERRUPT__: specifies the CEC interrupt to check. 450 * This parameter can be one of the following values: 451 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable 452 * @arg CEC_IT_TXERR: Tx Error IT Enable 453 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable 454 * @arg CEC_IT_TXEND: End of transmission IT Enable 455 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable 456 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable 457 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable 458 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable 459 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable 460 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable 461 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable 462 * @arg CEC_IT_RXEND: End Of Reception IT Enable 463 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable 464 * @retval FlagStatus 465 */ 466 #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) 467 468 /** @brief Enables the CEC device 469 * @param __HANDLE__: specifies the CEC Handle. 470 * @retval none 471 */ 472 #define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN) 473 474 /** @brief Disables the CEC device 475 * @param __HANDLE__: specifies the CEC Handle. 476 * @retval none 477 */ 478 #define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN) 479 480 /** @brief Set Transmission Start flag 481 * @param __HANDLE__: specifies the CEC Handle. 482 * @retval none 483 */ 484 #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM) 485 486 /** @brief Set Transmission End flag 487 * @param __HANDLE__: specifies the CEC Handle. 488 * @retval none 489 * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. 490 */ 491 #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM) 492 493 /** @brief Get Transmission Start flag 494 * @param __HANDLE__: specifies the CEC Handle. 495 * @retval FlagStatus 496 */ 497 #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM) 498 499 /** @brief Get Transmission End flag 500 * @param __HANDLE__: specifies the CEC Handle. 501 * @retval FlagStatus 502 */ 503 #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM) 504 505 /** @brief Clear OAR register 506 * @param __HANDLE__: specifies the CEC Handle. 507 * @retval none 508 */ 509 #define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR) 510 511 /** @brief Set OAR register (without resetting previously set address in case of multi-address mode) 512 * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand 513 * @param __HANDLE__: specifies the CEC Handle. 514 * @param __ADDRESS__: Own Address value (CEC logical address is identified by bit position) 515 * @retval none 516 */ 517 #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS) 518 519 /** 520 * @} 521 */ 522 523 /* Exported functions --------------------------------------------------------*/ 524 /** @addtogroup CEC_Exported_Functions 525 * @{ 526 */ 527 528 /** @addtogroup CEC_Exported_Functions_Group1 529 * @{ 530 */ 531 /* Initialization and de-initialization functions ****************************/ 532 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec); 533 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec); 534 void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec); 535 void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec); 536 /** 537 * @} 538 */ 539 540 /** @addtogroup CEC_Exported_Functions_Group2 541 * @{ 542 */ 543 /* I/O operation functions ***************************************************/ 544 HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout); 545 HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout); 546 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size); 547 HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData); 548 uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec); 549 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec); 550 void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec); 551 void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec); 552 void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec); 553 /** 554 * @} 555 */ 556 557 /** @addtogroup CEC_Exported_Functions_Group3 558 * @{ 559 */ 560 /* Peripheral State functions ************************************************/ 561 HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec); 562 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); 563 /** 564 * @} 565 */ 566 567 /** 568 * @} 569 */ 570 571 /* Private types -------------------------------------------------------------*/ 572 /** @defgroup CEC_Private_Types CEC Private Types 573 * @{ 574 */ 575 576 /** 577 * @} 578 */ 579 580 /* Private variables ---------------------------------------------------------*/ 581 /** @defgroup CEC_Private_Variables CEC Private Variables 582 * @{ 583 */ 584 585 /** 586 * @} 587 */ 588 589 /* Private constants ---------------------------------------------------------*/ 590 /** @defgroup CEC_Private_Constants CEC Private Constants 591 * @{ 592 */ 593 594 /** 595 * @} 596 */ 597 598 /* Private macros ------------------------------------------------------------*/ 599 /** @defgroup CEC_Private_Macros CEC Private Macros 600 * @{ 601 */ 602 603 #define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT) 604 605 #define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \ 606 ((__RXTOL__) == CEC_EXTENDED_TOLERANCE)) 607 608 #define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \ 609 ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE)) 610 611 #define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \ 612 ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION)) 613 614 #define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \ 615 ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION)) 616 617 #define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \ 618 ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION)) 619 620 #define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \ 621 ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END)) 622 623 #define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \ 624 ((__MODE__) == CEC_FULL_LISTENING_MODE)) 625 626 /** @brief Check CEC device Own Address Register (OAR) setting. 627 * OAR address is written in a 15-bit field within CEC_CFGR register. 628 * @param __ADDRESS__: CEC own address. 629 * @retval Test result (TRUE or FALSE). 630 */ 631 #define IS_CEC_OAR_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x07FFF) 632 633 /** @brief Check CEC initiator or destination logical address setting. 634 * Initiator and destination addresses are coded over 4 bits. 635 * @param __ADDRESS__: CEC initiator or logical address. 636 * @retval Test result (TRUE or FALSE). 637 */ 638 #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF) 639 640 /** @brief Check CEC message size. 641 * The message size is the payload size: without counting the header, 642 * it varies from 0 byte (ping operation, one header only, no payload) to 643 * 15 bytes (1 opcode and up to 14 operands following the header). 644 * @param __SIZE__: CEC message size. 645 * @retval Test result (TRUE or FALSE). 646 */ 647 #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF) 648 649 /** 650 * @} 651 */ 652 653 /* Private functions ---------------------------------------------------------*/ 654 /** @defgroup CEC_Private_Functions CEC Private Functions 655 * @{ 656 */ 657 658 /** 659 * @} 660 */ 661 662 /** 663 * @} 664 */ 665 666 /** 667 * @} 668 */ 669 670 #ifdef __cplusplus 671 } 672 #endif 673 674 #endif /* __STM32F7xx_HAL_CEC_H */ 675 676 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 677