1 /** 2 ****************************************************************************** 3 * @file stm32f7xx_hal_eth.h 4 * @author MCD Application Team 5 * @version V1.0.1 6 * @date 25-June-2015 7 * @brief Header file of ETH HAL module. 8 ****************************************************************************** 9 * @attention 10 * 11 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 12 * 13 * Redistribution and use in source and binary forms, with or without modification, 14 * are permitted provided that the following conditions are met: 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright notice, 18 * this list of conditions and the following disclaimer in the documentation 19 * and/or other materials provided with the distribution. 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 ****************************************************************************** 36 */ 37 38 /* Define to prevent recursive inclusion -------------------------------------*/ 39 #ifndef __STM32F7xx_HAL_ETH_H 40 #define __STM32F7xx_HAL_ETH_H 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 /* Includes ------------------------------------------------------------------*/ 47 #include "stm32f7xx_hal_def.h" 48 49 /** @addtogroup STM32F7xx_HAL_Driver 50 * @{ 51 */ 52 53 /** @addtogroup ETH 54 * @{ 55 */ 56 57 /** @addtogroup ETH_Private_Macros 58 * @{ 59 */ 60 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20) 61 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \ 62 ((CMD) == ETH_AUTONEGOTIATION_DISABLE)) 63 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \ 64 ((SPEED) == ETH_SPEED_100M)) 65 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \ 66 ((MODE) == ETH_MODE_HALFDUPLEX)) 67 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \ 68 ((MODE) == ETH_RXINTERRUPT_MODE)) 69 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \ 70 ((MODE) == ETH_RXINTERRUPT_MODE)) 71 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \ 72 ((MODE) == ETH_RXINTERRUPT_MODE)) 73 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \ 74 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE)) 75 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \ 76 ((MODE) == ETH_MEDIA_INTERFACE_RMII)) 77 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \ 78 ((CMD) == ETH_WATCHDOG_DISABLE)) 79 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \ 80 ((CMD) == ETH_JABBER_DISABLE)) 81 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \ 82 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \ 83 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \ 84 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \ 85 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \ 86 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \ 87 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \ 88 ((GAP) == ETH_INTERFRAMEGAP_40BIT)) 89 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \ 90 ((CMD) == ETH_CARRIERSENCE_DISABLE)) 91 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \ 92 ((CMD) == ETH_RECEIVEOWN_DISABLE)) 93 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \ 94 ((CMD) == ETH_LOOPBACKMODE_DISABLE)) 95 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \ 96 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE)) 97 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \ 98 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE)) 99 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \ 100 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE)) 101 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \ 102 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \ 103 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \ 104 ((LIMIT) == ETH_BACKOFFLIMIT_1)) 105 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \ 106 ((CMD) == ETH_DEFFERRALCHECK_DISABLE)) 107 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \ 108 ((CMD) == ETH_RECEIVEAll_DISABLE)) 109 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \ 110 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \ 111 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE)) 112 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \ 113 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \ 114 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER)) 115 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \ 116 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE)) 117 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \ 118 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE)) 119 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \ 120 ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE)) 121 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \ 122 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \ 123 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \ 124 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE)) 125 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \ 126 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \ 127 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT)) 128 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF) 129 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \ 130 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE)) 131 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \ 132 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \ 133 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \ 134 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256)) 135 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \ 136 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE)) 137 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \ 138 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE)) 139 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \ 140 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE)) 141 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \ 142 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT)) 143 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF) 144 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \ 145 ((ADDRESS) == ETH_MAC_ADDRESS1) || \ 146 ((ADDRESS) == ETH_MAC_ADDRESS2) || \ 147 ((ADDRESS) == ETH_MAC_ADDRESS3)) 148 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \ 149 ((ADDRESS) == ETH_MAC_ADDRESS2) || \ 150 ((ADDRESS) == ETH_MAC_ADDRESS3)) 151 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \ 152 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA)) 153 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \ 154 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \ 155 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \ 156 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \ 157 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \ 158 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1)) 159 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \ 160 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE)) 161 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \ 162 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE)) 163 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \ 164 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE)) 165 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \ 166 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE)) 167 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \ 168 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \ 169 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \ 170 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \ 171 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \ 172 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \ 173 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \ 174 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES)) 175 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \ 176 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE)) 177 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \ 178 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE)) 179 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \ 180 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \ 181 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \ 182 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES)) 183 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \ 184 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE)) 185 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \ 186 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE)) 187 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \ 188 ((CMD) == ETH_FIXEDBURST_DISABLE)) 189 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \ 190 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \ 191 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \ 192 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \ 193 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \ 194 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \ 195 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \ 196 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \ 197 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \ 198 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \ 199 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \ 200 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT)) 201 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \ 202 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \ 203 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \ 204 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \ 205 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \ 206 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \ 207 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \ 208 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \ 209 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \ 210 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \ 211 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \ 212 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT)) 213 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F) 214 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \ 215 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \ 216 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \ 217 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \ 218 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX)) 219 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \ 220 ((FLAG) == ETH_DMATXDESC_IC) || \ 221 ((FLAG) == ETH_DMATXDESC_LS) || \ 222 ((FLAG) == ETH_DMATXDESC_FS) || \ 223 ((FLAG) == ETH_DMATXDESC_DC) || \ 224 ((FLAG) == ETH_DMATXDESC_DP) || \ 225 ((FLAG) == ETH_DMATXDESC_TTSE) || \ 226 ((FLAG) == ETH_DMATXDESC_TER) || \ 227 ((FLAG) == ETH_DMATXDESC_TCH) || \ 228 ((FLAG) == ETH_DMATXDESC_TTSS) || \ 229 ((FLAG) == ETH_DMATXDESC_IHE) || \ 230 ((FLAG) == ETH_DMATXDESC_ES) || \ 231 ((FLAG) == ETH_DMATXDESC_JT) || \ 232 ((FLAG) == ETH_DMATXDESC_FF) || \ 233 ((FLAG) == ETH_DMATXDESC_PCE) || \ 234 ((FLAG) == ETH_DMATXDESC_LCA) || \ 235 ((FLAG) == ETH_DMATXDESC_NC) || \ 236 ((FLAG) == ETH_DMATXDESC_LCO) || \ 237 ((FLAG) == ETH_DMATXDESC_EC) || \ 238 ((FLAG) == ETH_DMATXDESC_VF) || \ 239 ((FLAG) == ETH_DMATXDESC_CC) || \ 240 ((FLAG) == ETH_DMATXDESC_ED) || \ 241 ((FLAG) == ETH_DMATXDESC_UF) || \ 242 ((FLAG) == ETH_DMATXDESC_DB)) 243 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \ 244 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT)) 245 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \ 246 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \ 247 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \ 248 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL)) 249 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF) 250 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \ 251 ((FLAG) == ETH_DMARXDESC_AFM) || \ 252 ((FLAG) == ETH_DMARXDESC_ES) || \ 253 ((FLAG) == ETH_DMARXDESC_DE) || \ 254 ((FLAG) == ETH_DMARXDESC_SAF) || \ 255 ((FLAG) == ETH_DMARXDESC_LE) || \ 256 ((FLAG) == ETH_DMARXDESC_OE) || \ 257 ((FLAG) == ETH_DMARXDESC_VLAN) || \ 258 ((FLAG) == ETH_DMARXDESC_FS) || \ 259 ((FLAG) == ETH_DMARXDESC_LS) || \ 260 ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \ 261 ((FLAG) == ETH_DMARXDESC_LC) || \ 262 ((FLAG) == ETH_DMARXDESC_FT) || \ 263 ((FLAG) == ETH_DMARXDESC_RWT) || \ 264 ((FLAG) == ETH_DMARXDESC_RE) || \ 265 ((FLAG) == ETH_DMARXDESC_DBE) || \ 266 ((FLAG) == ETH_DMARXDESC_CE) || \ 267 ((FLAG) == ETH_DMARXDESC_MAMPCE)) 268 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \ 269 ((BUFFER) == ETH_DMARXDESC_BUFFER2)) 270 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ 271 ((FLAG) == ETH_PMT_FLAG_MPR)) 272 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00)) 273 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ 274 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \ 275 ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \ 276 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ 277 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ 278 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ 279 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ 280 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ 281 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ 282 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ 283 ((FLAG) == ETH_DMA_FLAG_T)) 284 #define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00)) 285 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ 286 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ 287 ((IT) == ETH_MAC_IT_PMT)) 288 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ 289 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ 290 ((FLAG) == ETH_MAC_FLAG_PMT)) 291 #define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00)) 292 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ 293 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ 294 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ 295 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ 296 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ 297 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ 298 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ 299 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ 300 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) 301 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \ 302 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER)) 303 #define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \ 304 ((IT) != 0x00)) 305 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ 306 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ 307 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) 308 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \ 309 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE)) 310 311 312 /** 313 * @} 314 */ 315 316 /** @addtogroup ETH_Private_Defines 317 * @{ 318 */ 319 /* Delay to wait when writing to some Ethernet registers */ 320 #define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001) 321 322 /* ETHERNET Errors */ 323 #define ETH_SUCCESS ((uint32_t)0) 324 #define ETH_ERROR ((uint32_t)1) 325 326 /* ETHERNET DMA Tx descriptors Collision Count Shift */ 327 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3) 328 329 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ 330 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16) 331 332 /* ETHERNET DMA Rx descriptors Frame Length Shift */ 333 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16) 334 335 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ 336 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16) 337 338 /* ETHERNET DMA Rx descriptors Frame length Shift */ 339 #define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16) 340 341 /* ETHERNET MAC address offsets */ 342 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */ 343 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */ 344 345 /* ETHERNET MACMIIAR register Mask */ 346 #define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3) 347 348 /* ETHERNET MACCR register Mask */ 349 #define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F) 350 351 /* ETHERNET MACFCR register Mask */ 352 #define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41) 353 354 /* ETHERNET DMAOMR register Mask */ 355 #define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23) 356 357 /* ETHERNET Remote Wake-up frame register length */ 358 #define ETH_WAKEUP_REGISTER_LENGTH 8 359 360 /* ETHERNET Missed frames counter Shift */ 361 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17 362 /** 363 * @} 364 */ 365 366 /* Exported types ------------------------------------------------------------*/ 367 /** @defgroup ETH_Exported_Types ETH Exported Types 368 * @{ 369 */ 370 371 /** 372 * @brief HAL State structures definition 373 */ 374 typedef enum { 375 HAL_ETH_STATE_RESET = 0x00, /*!< Peripheral not yet Initialized or disabled */ 376 HAL_ETH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ 377 HAL_ETH_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ 378 HAL_ETH_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ 379 HAL_ETH_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ 380 HAL_ETH_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ 381 HAL_ETH_STATE_BUSY_WR = 0x42, /*!< Write process is ongoing */ 382 HAL_ETH_STATE_BUSY_RD = 0x82, /*!< Read process is ongoing */ 383 HAL_ETH_STATE_TIMEOUT = 0x03, /*!< Timeout state */ 384 HAL_ETH_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ 385 } HAL_ETH_StateTypeDef; 386 387 /** 388 * @brief ETH Init Structure definition 389 */ 390 391 typedef struct { 392 uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY 393 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) 394 and the mode (half/full-duplex). 395 This parameter can be a value of @ref ETH_AutoNegotiation */ 396 397 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps. 398 This parameter can be a value of @ref ETH_Speed */ 399 400 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode 401 This parameter can be a value of @ref ETH_Duplex_Mode */ 402 403 uint16_t PhyAddress; /*!< Ethernet PHY address. 404 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ 405 406 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ 407 408 uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode. 409 This parameter can be a value of @ref ETH_Rx_Mode */ 410 411 uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software. 412 This parameter can be a value of @ref ETH_Checksum_Mode */ 413 414 uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface. 415 This parameter can be a value of @ref ETH_Media_Interface */ 416 417 } ETH_InitTypeDef; 418 419 420 /** 421 * @brief ETH MAC Configuration Structure definition 422 */ 423 424 typedef struct { 425 uint32_t Watchdog; /*!< Selects or not the Watchdog timer 426 When enabled, the MAC allows no more then 2048 bytes to be received. 427 When disabled, the MAC can receive up to 16384 bytes. 428 This parameter can be a value of @ref ETH_Watchdog */ 429 430 uint32_t Jabber; /*!< Selects or not Jabber timer 431 When enabled, the MAC allows no more then 2048 bytes to be sent. 432 When disabled, the MAC can send up to 16384 bytes. 433 This parameter can be a value of @ref ETH_Jabber */ 434 435 uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission. 436 This parameter can be a value of @ref ETH_Inter_Frame_Gap */ 437 438 uint32_t CarrierSense; /*!< Selects or not the Carrier Sense. 439 This parameter can be a value of @ref ETH_Carrier_Sense */ 440 441 uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn, 442 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted 443 in Half-Duplex mode. 444 This parameter can be a value of @ref ETH_Receive_Own */ 445 446 uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode. 447 This parameter can be a value of @ref ETH_Loop_Back_Mode */ 448 449 uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. 450 This parameter can be a value of @ref ETH_Checksum_Offload */ 451 452 uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, 453 when a collision occurs (Half-Duplex mode). 454 This parameter can be a value of @ref ETH_Retry_Transmission */ 455 456 uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping. 457 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ 458 459 uint32_t BackOffLimit; /*!< Selects the BackOff limit value. 460 This parameter can be a value of @ref ETH_Back_Off_Limit */ 461 462 uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode). 463 This parameter can be a value of @ref ETH_Deferral_Check */ 464 465 uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering). 466 This parameter can be a value of @ref ETH_Receive_All */ 467 468 uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode. 469 This parameter can be a value of @ref ETH_Source_Addr_Filter */ 470 471 uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) 472 This parameter can be a value of @ref ETH_Pass_Control_Frames */ 473 474 uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames. 475 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ 476 477 uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames. 478 This parameter can be a value of @ref ETH_Destination_Addr_Filter */ 479 480 uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode 481 This parameter can be a value of @ref ETH_Promiscuous_Mode */ 482 483 uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter. 484 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ 485 486 uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter. 487 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ 488 489 uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. 490 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ 491 492 uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table. 493 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ 494 495 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. 496 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ 497 498 uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames. 499 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ 500 501 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for 502 automatic retransmission of PAUSE Frame. 503 This parameter can be a value of @ref ETH_Pause_Low_Threshold */ 504 505 uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 506 unicast address and unique multicast address). 507 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ 508 509 uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and 510 disable its transmitter for a specified time (Pause Time) 511 This parameter can be a value of @ref ETH_Receive_Flow_Control */ 512 513 uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) 514 or the MAC back-pressure operation (Half-Duplex mode) 515 This parameter can be a value of @ref ETH_Transmit_Flow_Control */ 516 517 uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for 518 comparison and filtering. 519 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ 520 521 uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */ 522 523 } ETH_MACInitTypeDef; 524 525 526 /** 527 * @brief ETH DMA Configuration Structure definition 528 */ 529 530 typedef struct { 531 uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames. 532 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ 533 534 uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode. 535 This parameter can be a value of @ref ETH_Receive_Store_Forward */ 536 537 uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames. 538 This parameter can be a value of @ref ETH_Flush_Received_Frame */ 539 540 uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode. 541 This parameter can be a value of @ref ETH_Transmit_Store_Forward */ 542 543 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control. 544 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ 545 546 uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames. 547 This parameter can be a value of @ref ETH_Forward_Error_Frames */ 548 549 uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error 550 and length less than 64 bytes) including pad-bytes and CRC) 551 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ 552 553 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO. 554 This parameter can be a value of @ref ETH_Receive_Threshold_Control */ 555 556 uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second 557 frame of Transmit data even before obtaining the status for the first frame. 558 This parameter can be a value of @ref ETH_Second_Frame_Operate */ 559 560 uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats. 561 This parameter can be a value of @ref ETH_Address_Aligned_Beats */ 562 563 uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers. 564 This parameter can be a value of @ref ETH_Fixed_Burst */ 565 566 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. 567 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ 568 569 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction. 570 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ 571 572 uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format. 573 This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */ 574 575 uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) 576 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ 577 578 uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration. 579 This parameter can be a value of @ref ETH_DMA_Arbitration */ 580 } ETH_DMAInitTypeDef; 581 582 583 /** 584 * @brief ETH DMA Descriptors data structure definition 585 */ 586 587 typedef struct { 588 __IO uint32_t Status; /*!< Status */ 589 590 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ 591 592 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ 593 594 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ 595 596 /*!< Enhanced ETHERNET DMA PTP Descriptors */ 597 uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */ 598 599 uint32_t Reserved1; /*!< Reserved */ 600 601 uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */ 602 603 uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */ 604 605 } ETH_DMADescTypeDef; 606 607 608 /** 609 * @brief Received Frame Informations structure definition 610 */ 611 typedef struct { 612 ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */ 613 614 ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */ 615 616 uint32_t SegCount; /*!< Segment count */ 617 618 uint32_t length; /*!< Frame length */ 619 620 uint32_t buffer; /*!< Frame buffer */ 621 622 } ETH_DMARxFrameInfos; 623 624 625 /** 626 * @brief ETH Handle Structure definition 627 */ 628 629 typedef struct { 630 ETH_TypeDef *Instance; /*!< Register base address */ 631 632 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */ 633 634 uint32_t LinkStatus; /*!< Ethernet link status */ 635 636 ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */ 637 638 ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */ 639 640 ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */ 641 642 __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */ 643 644 HAL_LockTypeDef Lock; /*!< ETH Lock */ 645 646 } ETH_HandleTypeDef; 647 648 /** 649 * @} 650 */ 651 652 /* Exported constants --------------------------------------------------------*/ 653 /** @defgroup ETH_Exported_Constants ETH Exported Constants 654 * @{ 655 */ 656 657 /** @defgroup ETH_Buffers_setting ETH Buffers setting 658 * @{ 659 */ 660 #define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ 661 #define ETH_HEADER ((uint32_t)14) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ 662 #define ETH_CRC ((uint32_t)4) /*!< Ethernet CRC */ 663 #define ETH_EXTRA ((uint32_t)2) /*!< Extra bytes in some cases */ 664 #define ETH_VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */ 665 #define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */ 666 #define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */ 667 #define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */ 668 669 /* Ethernet driver receive buffers are organized in a chained linked-list, when 670 an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO 671 to the driver receive buffers memory. 672 673 Depending on the size of the received ethernet packet and the size of 674 each ethernet driver receive buffer, the received packet can take one or more 675 ethernet driver receive buffer. 676 677 In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE 678 and the total count of the driver receive buffers ETH_RXBUFNB. 679 680 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as 681 example, they can be reconfigured in the application layer to fit the application 682 needs */ 683 684 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet 685 packet */ 686 #ifndef ETH_RX_BUF_SIZE 687 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE 688 #endif 689 690 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ 691 #ifndef ETH_RXBUFNB 692 #define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ 693 #endif 694 695 696 /* Ethernet driver transmit buffers are organized in a chained linked-list, when 697 an ethernet packet is transmitted, Tx-DMA will transfer the packet from the 698 driver transmit buffers memory to the TxFIFO. 699 700 Depending on the size of the Ethernet packet to be transmitted and the size of 701 each ethernet driver transmit buffer, the packet to be transmitted can take 702 one or more ethernet driver transmit buffer. 703 704 In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE 705 and the total count of the driver transmit buffers ETH_TXBUFNB. 706 707 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as 708 example, they can be reconfigured in the application layer to fit the application 709 needs */ 710 711 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet 712 packet */ 713 #ifndef ETH_TX_BUF_SIZE 714 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE 715 #endif 716 717 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/ 718 #ifndef ETH_TXBUFNB 719 #define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ 720 #endif 721 722 /** 723 * @} 724 */ 725 726 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor 727 * @{ 728 */ 729 730 /* 731 DMA Tx Descriptor 732 ----------------------------------------------------------------------------------------------- 733 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | 734 ----------------------------------------------------------------------------------------------- 735 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | 736 ----------------------------------------------------------------------------------------------- 737 TDES2 | Buffer1 Address [31:0] | 738 ----------------------------------------------------------------------------------------------- 739 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | 740 ----------------------------------------------------------------------------------------------- 741 */ 742 743 /** 744 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register 745 */ 746 #define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ 747 #define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */ 748 #define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /*!< Last Segment */ 749 #define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /*!< First Segment */ 750 #define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /*!< Disable CRC */ 751 #define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /*!< Disable Padding */ 752 #define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */ 753 #define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */ 754 #define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */ 755 #define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */ 756 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ 757 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ 758 #define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */ 759 #define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */ 760 #define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */ 761 #define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /*!< IP Header Error */ 762 #define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ 763 #define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */ 764 #define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ 765 #define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */ 766 #define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */ 767 #define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */ 768 #define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */ 769 #define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */ 770 #define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /*!< VLAN Frame */ 771 #define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /*!< Collision Count */ 772 #define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */ 773 #define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */ 774 #define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /*!< Deferred Bit */ 775 776 /** 777 * @brief Bit definition of TDES1 register 778 */ 779 #define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */ 780 #define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */ 781 782 /** 783 * @brief Bit definition of TDES2 register 784 */ 785 #define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ 786 787 /** 788 * @brief Bit definition of TDES3 register 789 */ 790 #define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ 791 792 /*--------------------------------------------------------------------------------------------- 793 TDES6 | Transmit Time Stamp Low [31:0] | 794 ----------------------------------------------------------------------------------------------- 795 TDES7 | Transmit Time Stamp High [31:0] | 796 ----------------------------------------------------------------------------------------------*/ 797 798 /* Bit definition of TDES6 register */ 799 #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */ 800 801 /* Bit definition of TDES7 register */ 802 #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */ 803 804 /** 805 * @} 806 */ 807 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor 808 * @{ 809 */ 810 811 /* 812 DMA Rx Descriptor 813 -------------------------------------------------------------------------------------------------------------------- 814 RDES0 | OWN(31) | Status [30:0] | 815 --------------------------------------------------------------------------------------------------------------------- 816 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | 817 --------------------------------------------------------------------------------------------------------------------- 818 RDES2 | Buffer1 Address [31:0] | 819 --------------------------------------------------------------------------------------------------------------------- 820 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | 821 --------------------------------------------------------------------------------------------------------------------- 822 */ 823 824 /** 825 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register 826 */ 827 #define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ 828 #define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */ 829 #define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */ 830 #define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ 831 #define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */ 832 #define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */ 833 #define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */ 834 #define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */ 835 #define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */ 836 #define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */ 837 #define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */ 838 #define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ 839 #define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */ 840 #define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */ 841 #define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ 842 #define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */ 843 #define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */ 844 #define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /*!< CRC error */ 845 #define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ 846 847 /** 848 * @brief Bit definition of RDES1 register 849 */ 850 #define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */ 851 #define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */ 852 #define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */ 853 #define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */ 854 #define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */ 855 856 /** 857 * @brief Bit definition of RDES2 register 858 */ 859 #define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ 860 861 /** 862 * @brief Bit definition of RDES3 register 863 */ 864 #define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ 865 866 /*--------------------------------------------------------------------------------------------------------------------- 867 RDES4 | Reserved[31:15] | Extended Status [14:0] | 868 --------------------------------------------------------------------------------------------------------------------- 869 RDES5 | Reserved[31:0] | 870 --------------------------------------------------------------------------------------------------------------------- 871 RDES6 | Receive Time Stamp Low [31:0] | 872 --------------------------------------------------------------------------------------------------------------------- 873 RDES7 | Receive Time Stamp High [31:0] | 874 --------------------------------------------------------------------------------------------------------------------*/ 875 876 /* Bit definition of RDES4 register */ 877 #define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */ 878 #define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */ 879 #define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */ 880 #define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */ 881 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */ 882 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */ 883 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */ 884 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ 885 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ 886 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ 887 #define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */ 888 #define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */ 889 #define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */ 890 #define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */ 891 #define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */ 892 #define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */ 893 #define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */ 894 #define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */ 895 #define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */ 896 897 /* Bit definition of RDES6 register */ 898 #define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */ 899 900 /* Bit definition of RDES7 register */ 901 #define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */ 902 /** 903 * @} 904 */ 905 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation 906 * @{ 907 */ 908 #define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001) 909 #define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000) 910 911 /** 912 * @} 913 */ 914 /** @defgroup ETH_Speed ETH Speed 915 * @{ 916 */ 917 #define ETH_SPEED_10M ((uint32_t)0x00000000) 918 #define ETH_SPEED_100M ((uint32_t)0x00004000) 919 920 /** 921 * @} 922 */ 923 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode 924 * @{ 925 */ 926 #define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800) 927 #define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000) 928 /** 929 * @} 930 */ 931 /** @defgroup ETH_Rx_Mode ETH Rx Mode 932 * @{ 933 */ 934 #define ETH_RXPOLLING_MODE ((uint32_t)0x00000000) 935 #define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001) 936 /** 937 * @} 938 */ 939 940 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode 941 * @{ 942 */ 943 #define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000) 944 #define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001) 945 /** 946 * @} 947 */ 948 949 /** @defgroup ETH_Media_Interface ETH Media Interface 950 * @{ 951 */ 952 #define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000) 953 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL) 954 /** 955 * @} 956 */ 957 958 /** @defgroup ETH_Watchdog ETH Watchdog 959 * @{ 960 */ 961 #define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000) 962 #define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000) 963 /** 964 * @} 965 */ 966 967 /** @defgroup ETH_Jabber ETH Jabber 968 * @{ 969 */ 970 #define ETH_JABBER_ENABLE ((uint32_t)0x00000000) 971 #define ETH_JABBER_DISABLE ((uint32_t)0x00400000) 972 /** 973 * @} 974 */ 975 976 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap 977 * @{ 978 */ 979 #define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */ 980 #define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */ 981 #define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */ 982 #define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */ 983 #define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */ 984 #define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */ 985 #define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */ 986 #define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */ 987 /** 988 * @} 989 */ 990 991 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense 992 * @{ 993 */ 994 #define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000) 995 #define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000) 996 /** 997 * @} 998 */ 999 1000 /** @defgroup ETH_Receive_Own ETH Receive Own 1001 * @{ 1002 */ 1003 #define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000) 1004 #define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000) 1005 /** 1006 * @} 1007 */ 1008 1009 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode 1010 * @{ 1011 */ 1012 #define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000) 1013 #define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000) 1014 /** 1015 * @} 1016 */ 1017 1018 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload 1019 * @{ 1020 */ 1021 #define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400) 1022 #define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000) 1023 /** 1024 * @} 1025 */ 1026 1027 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission 1028 * @{ 1029 */ 1030 #define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000) 1031 #define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200) 1032 /** 1033 * @} 1034 */ 1035 1036 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip 1037 * @{ 1038 */ 1039 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080) 1040 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000) 1041 /** 1042 * @} 1043 */ 1044 1045 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit 1046 * @{ 1047 */ 1048 #define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000) 1049 #define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020) 1050 #define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040) 1051 #define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060) 1052 /** 1053 * @} 1054 */ 1055 1056 /** @defgroup ETH_Deferral_Check ETH Deferral Check 1057 * @{ 1058 */ 1059 #define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010) 1060 #define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000) 1061 /** 1062 * @} 1063 */ 1064 1065 /** @defgroup ETH_Receive_All ETH Receive All 1066 * @{ 1067 */ 1068 #define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000) 1069 #define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000) 1070 /** 1071 * @} 1072 */ 1073 1074 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter 1075 * @{ 1076 */ 1077 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200) 1078 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300) 1079 #define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000) 1080 /** 1081 * @} 1082 */ 1083 1084 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames 1085 * @{ 1086 */ 1087 #define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */ 1088 #define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */ 1089 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */ 1090 /** 1091 * @} 1092 */ 1093 1094 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception 1095 * @{ 1096 */ 1097 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000) 1098 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020) 1099 /** 1100 * @} 1101 */ 1102 1103 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter 1104 * @{ 1105 */ 1106 #define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000) 1107 #define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008) 1108 /** 1109 * @} 1110 */ 1111 1112 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode 1113 * @{ 1114 */ 1115 #define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001) 1116 #define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000) 1117 /** 1118 * @} 1119 */ 1120 1121 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter 1122 * @{ 1123 */ 1124 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404) 1125 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004) 1126 #define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000) 1127 #define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010) 1128 /** 1129 * @} 1130 */ 1131 1132 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter 1133 * @{ 1134 */ 1135 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402) 1136 #define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002) 1137 #define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000) 1138 /** 1139 * @} 1140 */ 1141 1142 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause 1143 * @{ 1144 */ 1145 #define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000) 1146 #define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080) 1147 /** 1148 * @} 1149 */ 1150 1151 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold 1152 * @{ 1153 */ 1154 #define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */ 1155 #define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */ 1156 #define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */ 1157 #define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */ 1158 /** 1159 * @} 1160 */ 1161 1162 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect 1163 * @{ 1164 */ 1165 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008) 1166 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000) 1167 /** 1168 * @} 1169 */ 1170 1171 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control 1172 * @{ 1173 */ 1174 #define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004) 1175 #define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000) 1176 /** 1177 * @} 1178 */ 1179 1180 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control 1181 * @{ 1182 */ 1183 #define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002) 1184 #define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000) 1185 /** 1186 * @} 1187 */ 1188 1189 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison 1190 * @{ 1191 */ 1192 #define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000) 1193 #define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000) 1194 /** 1195 * @} 1196 */ 1197 1198 /** @defgroup ETH_MAC_addresses ETH MAC addresses 1199 * @{ 1200 */ 1201 #define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000) 1202 #define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008) 1203 #define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010) 1204 #define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018) 1205 /** 1206 * @} 1207 */ 1208 1209 /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA 1210 * @{ 1211 */ 1212 #define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000) 1213 #define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008) 1214 /** 1215 * @} 1216 */ 1217 1218 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes 1219 * @{ 1220 */ 1221 #define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */ 1222 #define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */ 1223 #define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */ 1224 #define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */ 1225 #define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */ 1226 #define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */ 1227 /** 1228 * @} 1229 */ 1230 1231 /** @defgroup ETH_MAC_Debug_flags ETH MAC Debug flags 1232 * @{ 1233 */ 1234 #define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */ 1235 #define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */ 1236 #define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */ 1237 #define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */ 1238 #define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ 1239 #define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ 1240 #define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ 1241 #define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */ 1242 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */ 1243 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ 1244 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ 1245 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */ 1246 #define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */ 1247 #define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */ 1248 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ 1249 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */ 1250 #define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */ 1251 #define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */ 1252 #define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */ 1253 #define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */ 1254 #define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */ 1255 #define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */ 1256 #define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */ 1257 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */ 1258 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */ 1259 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */ 1260 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */ 1261 /** 1262 * @} 1263 */ 1264 1265 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame 1266 * @{ 1267 */ 1268 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000) 1269 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000) 1270 /** 1271 * @} 1272 */ 1273 1274 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward 1275 * @{ 1276 */ 1277 #define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000) 1278 #define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000) 1279 /** 1280 * @} 1281 */ 1282 1283 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame 1284 * @{ 1285 */ 1286 #define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000) 1287 #define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000) 1288 /** 1289 * @} 1290 */ 1291 1292 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward 1293 * @{ 1294 */ 1295 #define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000) 1296 #define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000) 1297 /** 1298 * @} 1299 */ 1300 1301 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control 1302 * @{ 1303 */ 1304 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ 1305 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ 1306 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ 1307 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ 1308 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ 1309 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ 1310 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ 1311 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ 1312 /** 1313 * @} 1314 */ 1315 1316 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames 1317 * @{ 1318 */ 1319 #define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080) 1320 #define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000) 1321 /** 1322 * @} 1323 */ 1324 1325 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames 1326 * @{ 1327 */ 1328 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040) 1329 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000) 1330 /** 1331 * @} 1332 */ 1333 1334 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control 1335 * @{ 1336 */ 1337 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ 1338 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ 1339 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ 1340 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ 1341 /** 1342 * @} 1343 */ 1344 1345 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate 1346 * @{ 1347 */ 1348 #define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004) 1349 #define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000) 1350 /** 1351 * @} 1352 */ 1353 1354 /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats 1355 * @{ 1356 */ 1357 #define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000) 1358 #define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000) 1359 /** 1360 * @} 1361 */ 1362 1363 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst 1364 * @{ 1365 */ 1366 #define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000) 1367 #define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000) 1368 /** 1369 * @} 1370 */ 1371 1372 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length 1373 * @{ 1374 */ 1375 #define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ 1376 #define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ 1377 #define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ 1378 #define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ 1379 #define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ 1380 #define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ 1381 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ 1382 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ 1383 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ 1384 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ 1385 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ 1386 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ 1387 /** 1388 * @} 1389 */ 1390 1391 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length 1392 * @{ 1393 */ 1394 #define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ 1395 #define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ 1396 #define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 1397 #define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 1398 #define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 1399 #define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 1400 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 1401 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 1402 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 1403 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 1404 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ 1405 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ 1406 /** 1407 * @} 1408 */ 1409 1410 /** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format 1411 * @{ 1412 */ 1413 #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080) 1414 #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000) 1415 /** 1416 * @} 1417 */ 1418 1419 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration 1420 * @{ 1421 */ 1422 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000) 1423 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000) 1424 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000) 1425 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000) 1426 #define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002) 1427 /** 1428 * @} 1429 */ 1430 1431 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment 1432 * @{ 1433 */ 1434 #define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /*!< Last Segment */ 1435 #define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /*!< First Segment */ 1436 /** 1437 * @} 1438 */ 1439 1440 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control 1441 * @{ 1442 */ 1443 #define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /*!< Checksum engine bypass */ 1444 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */ 1445 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ 1446 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ 1447 /** 1448 * @} 1449 */ 1450 1451 /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers 1452 * @{ 1453 */ 1454 #define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */ 1455 #define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */ 1456 /** 1457 * @} 1458 */ 1459 1460 /** @defgroup ETH_PMT_Flags ETH PMT Flags 1461 * @{ 1462 */ 1463 #define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */ 1464 #define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */ 1465 #define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */ 1466 /** 1467 * @} 1468 */ 1469 1470 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts 1471 * @{ 1472 */ 1473 #define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */ 1474 #define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */ 1475 #define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */ 1476 /** 1477 * @} 1478 */ 1479 1480 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts 1481 * @{ 1482 */ 1483 #define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */ 1484 #define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */ 1485 #define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */ 1486 /** 1487 * @} 1488 */ 1489 1490 /** @defgroup ETH_MAC_Flags ETH MAC Flags 1491 * @{ 1492 */ 1493 #define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */ 1494 #define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */ 1495 #define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */ 1496 #define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */ 1497 #define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */ 1498 /** 1499 * @} 1500 */ 1501 1502 /** @defgroup ETH_DMA_Flags ETH DMA Flags 1503 * @{ 1504 */ 1505 #define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ 1506 #define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ 1507 #define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ 1508 #define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */ 1509 #define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write transfer, 1-read transfer */ 1510 #define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */ 1511 #define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */ 1512 #define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */ 1513 #define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */ 1514 #define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */ 1515 #define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */ 1516 #define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */ 1517 #define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */ 1518 #define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */ 1519 #define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */ 1520 #define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */ 1521 #define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */ 1522 #define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */ 1523 #define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */ 1524 #define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */ 1525 #define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */ 1526 /** 1527 * @} 1528 */ 1529 1530 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts 1531 * @{ 1532 */ 1533 #define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */ 1534 #define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */ 1535 #define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */ 1536 #define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */ 1537 #define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */ 1538 /** 1539 * @} 1540 */ 1541 1542 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts 1543 * @{ 1544 */ 1545 #define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ 1546 #define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ 1547 #define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ 1548 #define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */ 1549 #define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */ 1550 #define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */ 1551 #define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */ 1552 #define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */ 1553 #define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */ 1554 #define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */ 1555 #define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */ 1556 #define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */ 1557 #define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */ 1558 #define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */ 1559 #define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */ 1560 #define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */ 1561 #define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */ 1562 #define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */ 1563 /** 1564 * @} 1565 */ 1566 1567 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state 1568 * @{ 1569 */ 1570 #define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */ 1571 #define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */ 1572 #define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /*!< Running - waiting for status */ 1573 #define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */ 1574 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /*!< Suspended - Tx Descriptor unavailable */ 1575 #define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */ 1576 1577 /** 1578 * @} 1579 */ 1580 1581 1582 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state 1583 * @{ 1584 */ 1585 #define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */ 1586 #define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */ 1587 #define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /*!< Running - waiting for packet */ 1588 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /*!< Suspended - Rx Descriptor unavailable */ 1589 #define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /*!< Running - closing descriptor */ 1590 #define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /*!< Running - queuing the receive frame into host memory */ 1591 1592 /** 1593 * @} 1594 */ 1595 1596 /** @defgroup ETH_DMA_overflow ETH DMA overflow 1597 * @{ 1598 */ 1599 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */ 1600 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */ 1601 /** 1602 * @} 1603 */ 1604 1605 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP 1606 * @{ 1607 */ 1608 #define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the ETH EXTI Line */ 1609 1610 /** 1611 * @} 1612 */ 1613 1614 /** 1615 * @} 1616 */ 1617 1618 /* Exported macro ------------------------------------------------------------*/ 1619 /** @defgroup ETH_Exported_Macros ETH Exported Macros 1620 * @brief macros to handle interrupts and specific clock configurations 1621 * @{ 1622 */ 1623 1624 /** @brief Reset ETH handle state 1625 * @param __HANDLE__: specifies the ETH handle. 1626 * @retval None 1627 */ 1628 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET) 1629 1630 /** 1631 * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. 1632 * @param __HANDLE__: ETH Handle 1633 * @param __FLAG__: specifies the flag of TDES0 to check. 1634 * @retval the ETH_DMATxDescFlag (SET or RESET). 1635 */ 1636 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__)) 1637 1638 /** 1639 * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not. 1640 * @param __HANDLE__: ETH Handle 1641 * @param __FLAG__: specifies the flag of RDES0 to check. 1642 * @retval the ETH_DMATxDescFlag (SET or RESET). 1643 */ 1644 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__)) 1645 1646 /** 1647 * @brief Enables the specified DMA Rx Desc receive interrupt. 1648 * @param __HANDLE__: ETH Handle 1649 * @retval None 1650 */ 1651 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC)) 1652 1653 /** 1654 * @brief Disables the specified DMA Rx Desc receive interrupt. 1655 * @param __HANDLE__: ETH Handle 1656 * @retval None 1657 */ 1658 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC) 1659 1660 /** 1661 * @brief Set the specified DMA Rx Desc Own bit. 1662 * @param __HANDLE__: ETH Handle 1663 * @retval None 1664 */ 1665 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN) 1666 1667 /** 1668 * @brief Returns the specified ETHERNET DMA Tx Desc collision count. 1669 * @param __HANDLE__: ETH Handle 1670 * @retval The Transmit descriptor collision counter value. 1671 */ 1672 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT) 1673 1674 /** 1675 * @brief Set the specified DMA Tx Desc Own bit. 1676 * @param __HANDLE__: ETH Handle 1677 * @retval None 1678 */ 1679 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN) 1680 1681 /** 1682 * @brief Enables the specified DMA Tx Desc Transmit interrupt. 1683 * @param __HANDLE__: ETH Handle 1684 * @retval None 1685 */ 1686 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC) 1687 1688 /** 1689 * @brief Disables the specified DMA Tx Desc Transmit interrupt. 1690 * @param __HANDLE__: ETH Handle 1691 * @retval None 1692 */ 1693 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC) 1694 1695 /** 1696 * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. 1697 * @param __HANDLE__: ETH Handle 1698 * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion. 1699 * This parameter can be one of the following values: 1700 * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass 1701 * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum 1702 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present 1703 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header 1704 * @retval None 1705 */ 1706 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__)) 1707 1708 /** 1709 * @brief Enables the DMA Tx Desc CRC. 1710 * @param __HANDLE__: ETH Handle 1711 * @retval None 1712 */ 1713 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC) 1714 1715 /** 1716 * @brief Disables the DMA Tx Desc CRC. 1717 * @param __HANDLE__: ETH Handle 1718 * @retval None 1719 */ 1720 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC) 1721 1722 /** 1723 * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes. 1724 * @param __HANDLE__: ETH Handle 1725 * @retval None 1726 */ 1727 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP) 1728 1729 /** 1730 * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes. 1731 * @param __HANDLE__: ETH Handle 1732 * @retval None 1733 */ 1734 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP) 1735 1736 /** 1737 * @brief Enables the specified ETHERNET MAC interrupts. 1738 * @param __HANDLE__ : ETH Handle 1739 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be 1740 * enabled or disabled. 1741 * This parameter can be any combination of the following values: 1742 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt 1743 * @arg ETH_MAC_IT_PMT : PMT interrupt 1744 * @retval None 1745 */ 1746 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__)) 1747 1748 /** 1749 * @brief Disables the specified ETHERNET MAC interrupts. 1750 * @param __HANDLE__ : ETH Handle 1751 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be 1752 * enabled or disabled. 1753 * This parameter can be any combination of the following values: 1754 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt 1755 * @arg ETH_MAC_IT_PMT : PMT interrupt 1756 * @retval None 1757 */ 1758 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__)) 1759 1760 /** 1761 * @brief Initiate a Pause Control Frame (Full-duplex only). 1762 * @param __HANDLE__: ETH Handle 1763 * @retval None 1764 */ 1765 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) 1766 1767 /** 1768 * @brief Checks whether the ETHERNET flow control busy bit is set or not. 1769 * @param __HANDLE__: ETH Handle 1770 * @retval The new state of flow control busy status bit (SET or RESET). 1771 */ 1772 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA) 1773 1774 /** 1775 * @brief Enables the MAC Back Pressure operation activation (Half-duplex only). 1776 * @param __HANDLE__: ETH Handle 1777 * @retval None 1778 */ 1779 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) 1780 1781 /** 1782 * @brief Disables the MAC BackPressure operation activation (Half-duplex only). 1783 * @param __HANDLE__: ETH Handle 1784 * @retval None 1785 */ 1786 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA) 1787 1788 /** 1789 * @brief Checks whether the specified ETHERNET MAC flag is set or not. 1790 * @param __HANDLE__: ETH Handle 1791 * @param __FLAG__: specifies the flag to check. 1792 * This parameter can be one of the following values: 1793 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag 1794 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag 1795 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag 1796 * @arg ETH_MAC_FLAG_MMC : MMC flag 1797 * @arg ETH_MAC_FLAG_PMT : PMT flag 1798 * @retval The state of ETHERNET MAC flag. 1799 */ 1800 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__)) 1801 1802 /** 1803 * @brief Enables the specified ETHERNET DMA interrupts. 1804 * @param __HANDLE__ : ETH Handle 1805 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be 1806 * enabled @ref ETH_DMA_Interrupts 1807 * @retval None 1808 */ 1809 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__)) 1810 1811 /** 1812 * @brief Disables the specified ETHERNET DMA interrupts. 1813 * @param __HANDLE__ : ETH Handle 1814 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be 1815 * disabled. @ref ETH_DMA_Interrupts 1816 * @retval None 1817 */ 1818 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__)) 1819 1820 /** 1821 * @brief Clears the ETHERNET DMA IT pending bit. 1822 * @param __HANDLE__ : ETH Handle 1823 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts 1824 * @retval None 1825 */ 1826 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__)) 1827 1828 /** 1829 * @brief Checks whether the specified ETHERNET DMA flag is set or not. 1830 * @param __HANDLE__: ETH Handle 1831 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags 1832 * @retval The new state of ETH_DMA_FLAG (SET or RESET). 1833 */ 1834 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__)) 1835 1836 /** 1837 * @brief Checks whether the specified ETHERNET DMA flag is set or not. 1838 * @param __HANDLE__: ETH Handle 1839 * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags 1840 * @retval The new state of ETH_DMA_FLAG (SET or RESET). 1841 */ 1842 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__)) 1843 1844 /** 1845 * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. 1846 * @param __HANDLE__: ETH Handle 1847 * @param __OVERFLOW__: specifies the DMA overflow flag to check. 1848 * This parameter can be one of the following values: 1849 * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter 1850 * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter 1851 * @retval The state of ETHERNET DMA overflow Flag (SET or RESET). 1852 */ 1853 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__)) 1854 1855 /** 1856 * @brief Set the DMA Receive status watchdog timer register value 1857 * @param __HANDLE__: ETH Handle 1858 * @param __VALUE__: DMA Receive status watchdog timer register value 1859 * @retval None 1860 */ 1861 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__)) 1862 1863 /** 1864 * @brief Enables any unicast packet filtered by the MAC address 1865 * recognition to be a wake-up frame. 1866 * @param __HANDLE__: ETH Handle. 1867 * @retval None 1868 */ 1869 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU) 1870 1871 /** 1872 * @brief Disables any unicast packet filtered by the MAC address 1873 * recognition to be a wake-up frame. 1874 * @param __HANDLE__: ETH Handle. 1875 * @retval None 1876 */ 1877 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU) 1878 1879 /** 1880 * @brief Enables the MAC Wake-Up Frame Detection. 1881 * @param __HANDLE__: ETH Handle. 1882 * @retval None 1883 */ 1884 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE) 1885 1886 /** 1887 * @brief Disables the MAC Wake-Up Frame Detection. 1888 * @param __HANDLE__: ETH Handle. 1889 * @retval None 1890 */ 1891 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) 1892 1893 /** 1894 * @brief Enables the MAC Magic Packet Detection. 1895 * @param __HANDLE__: ETH Handle. 1896 * @retval None 1897 */ 1898 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE) 1899 1900 /** 1901 * @brief Disables the MAC Magic Packet Detection. 1902 * @param __HANDLE__: ETH Handle. 1903 * @retval None 1904 */ 1905 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) 1906 1907 /** 1908 * @brief Enables the MAC Power Down. 1909 * @param __HANDLE__: ETH Handle 1910 * @retval None 1911 */ 1912 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD) 1913 1914 /** 1915 * @brief Disables the MAC Power Down. 1916 * @param __HANDLE__: ETH Handle 1917 * @retval None 1918 */ 1919 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD) 1920 1921 /** 1922 * @brief Checks whether the specified ETHERNET PMT flag is set or not. 1923 * @param __HANDLE__: ETH Handle. 1924 * @param __FLAG__: specifies the flag to check. 1925 * This parameter can be one of the following values: 1926 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset 1927 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received 1928 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received 1929 * @retval The new state of ETHERNET PMT Flag (SET or RESET). 1930 */ 1931 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__)) 1932 1933 /** 1934 * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) 1935 * @param __HANDLE__: ETH Handle. 1936 * @retval None 1937 */ 1938 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP)) 1939 1940 /** 1941 * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16) 1942 * @param __HANDLE__: ETH Handle. 1943 * @retval None 1944 */ 1945 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\ 1946 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0) 1947 1948 /** 1949 * @brief Enables the MMC Counter Freeze. 1950 * @param __HANDLE__: ETH Handle. 1951 * @retval None 1952 */ 1953 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF) 1954 1955 /** 1956 * @brief Disables the MMC Counter Freeze. 1957 * @param __HANDLE__: ETH Handle. 1958 * @retval None 1959 */ 1960 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF) 1961 1962 /** 1963 * @brief Enables the MMC Reset On Read. 1964 * @param __HANDLE__: ETH Handle. 1965 * @retval None 1966 */ 1967 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR) 1968 1969 /** 1970 * @brief Disables the MMC Reset On Read. 1971 * @param __HANDLE__: ETH Handle. 1972 * @retval None 1973 */ 1974 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR) 1975 1976 /** 1977 * @brief Enables the MMC Counter Stop Rollover. 1978 * @param __HANDLE__: ETH Handle. 1979 * @retval None 1980 */ 1981 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR) 1982 1983 /** 1984 * @brief Disables the MMC Counter Stop Rollover. 1985 * @param __HANDLE__: ETH Handle. 1986 * @retval None 1987 */ 1988 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR) 1989 1990 /** 1991 * @brief Resets the MMC Counters. 1992 * @param __HANDLE__: ETH Handle. 1993 * @retval None 1994 */ 1995 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR) 1996 1997 /** 1998 * @brief Enables the specified ETHERNET MMC Rx interrupts. 1999 * @param __HANDLE__: ETH Handle. 2000 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 2001 * This parameter can be one of the following values: 2002 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value 2003 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value 2004 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value 2005 * @retval None 2006 */ 2007 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF) 2008 /** 2009 * @brief Disables the specified ETHERNET MMC Rx interrupts. 2010 * @param __HANDLE__: ETH Handle. 2011 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 2012 * This parameter can be one of the following values: 2013 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value 2014 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value 2015 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value 2016 * @retval None 2017 */ 2018 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF) 2019 /** 2020 * @brief Enables the specified ETHERNET MMC Tx interrupts. 2021 * @param __HANDLE__: ETH Handle. 2022 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 2023 * This parameter can be one of the following values: 2024 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value 2025 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value 2026 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value 2027 * @retval None 2028 */ 2029 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__)) 2030 2031 /** 2032 * @brief Disables the specified ETHERNET MMC Tx interrupts. 2033 * @param __HANDLE__: ETH Handle. 2034 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 2035 * This parameter can be one of the following values: 2036 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value 2037 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value 2038 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value 2039 * @retval None 2040 */ 2041 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__)) 2042 2043 /** 2044 * @brief Enables the ETH External interrupt line. 2045 * @retval None 2046 */ 2047 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP) 2048 2049 /** 2050 * @brief Disables the ETH External interrupt line. 2051 * @retval None 2052 */ 2053 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP) 2054 2055 /** 2056 * @brief Enable event on ETH External event line. 2057 * @retval None. 2058 */ 2059 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP) 2060 2061 /** 2062 * @brief Disable event on ETH External event line 2063 * @retval None. 2064 */ 2065 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP) 2066 2067 /** 2068 * @brief Get flag of the ETH External interrupt line. 2069 * @retval None 2070 */ 2071 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP) 2072 2073 /** 2074 * @brief Clear flag of the ETH External interrupt line. 2075 * @retval None 2076 */ 2077 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP) 2078 2079 /** 2080 * @brief Enables rising edge trigger to the ETH External interrupt line. 2081 * @retval None 2082 */ 2083 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP 2084 2085 /** 2086 * @brief Disables the rising edge trigger to the ETH External interrupt line. 2087 * @retval None 2088 */ 2089 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) 2090 2091 /** 2092 * @brief Enables falling edge trigger to the ETH External interrupt line. 2093 * @retval None 2094 */ 2095 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP) 2096 2097 /** 2098 * @brief Disables falling edge trigger to the ETH External interrupt line. 2099 * @retval None 2100 */ 2101 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) 2102 2103 /** 2104 * @brief Enables rising/falling edge trigger to the ETH External interrupt line. 2105 * @retval None 2106 */ 2107 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\ 2108 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP 2109 2110 /** 2111 * @brief Disables rising/falling edge trigger to the ETH External interrupt line. 2112 * @retval None 2113 */ 2114 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ 2115 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) 2116 2117 /** 2118 * @brief Generate a Software interrupt on selected EXTI line. 2119 * @retval None. 2120 */ 2121 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP 2122 2123 /** 2124 * @} 2125 */ 2126 /* Exported functions --------------------------------------------------------*/ 2127 2128 /** @addtogroup ETH_Exported_Functions 2129 * @{ 2130 */ 2131 2132 /* Initialization and de-initialization functions ****************************/ 2133 2134 /** @addtogroup ETH_Exported_Functions_Group1 2135 * @{ 2136 */ 2137 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); 2138 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); 2139 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); 2140 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); 2141 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount); 2142 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); 2143 2144 /** 2145 * @} 2146 */ 2147 /* IO operation functions ****************************************************/ 2148 2149 /** @addtogroup ETH_Exported_Functions_Group2 2150 * @{ 2151 */ 2152 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength); 2153 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth); 2154 /* Communication with PHY functions*/ 2155 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue); 2156 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue); 2157 /* Non-Blocking mode: Interrupt */ 2158 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth); 2159 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); 2160 /* Callback in non blocking modes (Interrupt) */ 2161 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); 2162 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); 2163 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); 2164 /** 2165 * @} 2166 */ 2167 2168 /* Peripheral Control functions **********************************************/ 2169 2170 /** @addtogroup ETH_Exported_Functions_Group3 2171 * @{ 2172 */ 2173 2174 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); 2175 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); 2176 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf); 2177 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf); 2178 /** 2179 * @} 2180 */ 2181 2182 /* Peripheral State functions ************************************************/ 2183 2184 /** @addtogroup ETH_Exported_Functions_Group4 2185 * @{ 2186 */ 2187 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); 2188 /** 2189 * @} 2190 */ 2191 2192 /** 2193 * @} 2194 */ 2195 2196 /** 2197 * @} 2198 */ 2199 2200 /** 2201 * @} 2202 */ 2203 #ifdef __cplusplus 2204 } 2205 #endif 2206 2207 #endif /* __STM32F7xx_HAL_ETH_H */ 2208 2209 2210 2211 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 2212