1 /*
2 * Copyright (c) 2014 Chris Anderson
3 *
4 * Use of this source code is governed by a MIT-style
5 * license that can be found in the LICENSE file or at
6 * https://opensource.org/licenses/MIT
7 */
8 #include <stdio.h>
9 #include <dev/gpio.h>
10 #include <target/gpioconfig.h>
11 #include <lib/pktbuf.h>
12 #include <kernel/vm.h>
13 #include <platform/zynq.h>
14 #include <platform/gem.h>
15 #include <target.h>
16
17 zynq_pll_cfg_tree_t zynq_pll_cfg = {
18 .arm = {
19 .lock_cnt = 250,
20 .cp = 2,
21 .res = 2,
22 .fdiv = 40,
23 },
24 .ddr = {
25 .lock_cnt = 300,
26 .cp = 2,
27 .res = 2,
28 .fdiv = 32,
29 },
30 .io = {
31 .lock_cnt = 325,
32 .cp = 2,
33 .res = 12,
34 .fdiv = 30,
35 }
36 };
37
38 const unsigned long zynq_ddr_cfg[] = {
39 0XF8006000, 0x00000080U, 0XF8006004, 0x00001081U, 0XF8006008, 0x03C0780FU,
40 0XF800600C, 0x02001001U, 0XF8006010, 0x00014001U, 0XF8006014, 0x0004281AU,
41 0XF8006018, 0x44E458D2U, 0XF800601C, 0x720238E5U, 0XF8006020, 0x270872D0U,
42 0XF8006024, 0x00000000U, 0XF8006028, 0x00002007U, 0XF800602C, 0x00000008U,
43 0XF8006030, 0x00040930U, 0XF8006034, 0x00011054U, 0XF8006038, 0x00000000U,
44 0XF800603C, 0x00000777U, 0XF8006040, 0xFFF00000U, 0XF8006044, 0x0F666666U,
45 0XF8006048, 0x0003C000U, 0XF8006050, 0x77010800U, 0XF8006058, 0x00000000U,
46 0XF800605C, 0x00005003U, 0XF8006060, 0x0000003EU, 0XF8006064, 0x00020000U,
47 0XF8006068, 0x00284141U, 0XF800606C, 0x00001610U, 0XF8006078, 0x00466111U,
48 0XF800607C, 0x00032222U, 0XF80060A4, 0x10200802U, 0XF80060A8, 0x0690CB73U,
49 0XF80060AC, 0x000001FEU, 0XF80060B0, 0x1CFFFFFFU, 0XF80060B4, 0x00000200U,
50 0XF80060B8, 0x00200066U, 0XF80060C4, 0x00000003U, 0XF80060C4, 0x00000000U,
51 0XF80060C8, 0x00000000U, 0XF80060DC, 0x00000000U, 0XF80060F0, 0x00000000U,
52 0XF80060F4, 0x00000008U, 0XF8006114, 0x00000000U, 0XF8006118, 0x40000001U,
53 0XF800611C, 0x40000001U, 0XF8006120, 0x40000001U, 0XF8006124, 0x40000001U,
54 0XF800612C, 0x0002C000U, 0XF8006130, 0x0002C400U, 0XF8006134, 0x0002F003U,
55 0XF8006138, 0x0002EC03U, 0XF8006140, 0x00000035U, 0XF8006144, 0x00000035U,
56 0XF8006148, 0x00000035U, 0XF800614C, 0x00000035U, 0XF8006154, 0x00000077U,
57 0XF8006158, 0x00000077U, 0XF800615C, 0x00000083U, 0XF8006160, 0x00000083U,
58 0XF8006168, 0x00000105U, 0XF800616C, 0x00000106U, 0XF8006170, 0x00000111U,
59 0XF8006174, 0x00000110U, 0XF800617C, 0x000000B7U, 0XF8006180, 0x000000B7U,
60 0XF8006184, 0x000000C3U, 0XF8006188, 0x000000C3U, 0XF8006190, 0x00040080U,
61 0XF8006194, 0x0001FC82U, 0XF8006204, 0x00000000U, 0XF8006208, 0x000003FFU,
62 0XF800620C, 0x000003FFU, 0XF8006210, 0x000003FFU, 0XF8006214, 0x000003FFU,
63 0XF8006218, 0x000003FFU, 0XF800621C, 0x000003FFU, 0XF8006220, 0x000003FFU,
64 0XF8006224, 0x000003FFU, 0XF80062A8, 0x00000000U, 0XF80062AC, 0x00000000U,
65 0XF80062B0, 0x00005125U, 0XF80062B4, 0x000012A8U,
66 };
67
68 const unsigned long zynq_ddr_cfg_cnt = countof(zynq_ddr_cfg);
69
70 const zynq_ddriob_cfg_t zynq_ddriob_cfg = {
71 .addr0 = DDRIOB_OUTPUT_EN(0x3),
72 .addr1 = DDRIOB_OUTPUT_EN(0x3),
73 .data0 = DDRIOB_INP_TYPE(1) | DDRIOB_TERM_EN | DDRIOB_DCI_TYPE(0x3) | DDRIOB_OUTPUT_EN(0x3),
74 .data1 = DDRIOB_INP_TYPE(1) | DDRIOB_TERM_EN | DDRIOB_DCI_TYPE(0x3) | DDRIOB_OUTPUT_EN(0x3),
75 .diff0 = DDRIOB_INP_TYPE(2) | DDRIOB_TERM_EN | DDRIOB_DCI_TYPE(0x3) | DDRIOB_OUTPUT_EN(0x3),
76 .diff1 = DDRIOB_INP_TYPE(2) | DDRIOB_TERM_EN | DDRIOB_DCI_TYPE(0x3) | DDRIOB_OUTPUT_EN(0x3),
77 .ibuf_disable = false,
78 .term_disable = false,
79 };
80
81 const uint32_t zynq_mio_cfg[ZYNQ_MIO_CNT] = {
82 [0] = MIO_IO_TYPE_LVCMOS33,
83 [1] = MIO_L0_SEL | MIO_IO_TYPE_LVCMOS33,
84 [2] = MIO_L0_SEL | MIO_IO_TYPE_LVCMOS33,
85 [3] = MIO_L0_SEL | MIO_IO_TYPE_LVCMOS33,
86 [4] = MIO_L0_SEL | MIO_IO_TYPE_LVCMOS33,
87 [5] = MIO_L0_SEL | MIO_IO_TYPE_LVCMOS33,
88 [6] = MIO_L0_SEL | MIO_IO_TYPE_LVCMOS33,
89 [7] = MIO_IO_TYPE_LVCMOS33,
90 [8] = MIO_L0_SEL | MIO_IO_TYPE_LVCMOS33,
91 [9] = MIO_IO_TYPE_LVCMOS33,
92 [10] = MIO_IO_TYPE_LVCMOS33,
93 [11] = MIO_IO_TYPE_LVCMOS33,
94 [12] = MIO_IO_TYPE_LVCMOS33,
95 [13] = MIO_IO_TYPE_LVCMOS33,
96 [14] = MIO_IO_TYPE_LVCMOS33,
97 [15] = MIO_IO_TYPE_LVCMOS33,
98 // 16-21 gem0
99 [16] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_PULLUP | MIO_DISABLE_RCVR,
100 [17] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_PULLUP | MIO_DISABLE_RCVR,
101 [18] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_PULLUP | MIO_DISABLE_RCVR,
102 [19] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_PULLUP | MIO_DISABLE_RCVR,
103 [20] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_PULLUP | MIO_DISABLE_RCVR,
104 [21] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_PULLUP | MIO_DISABLE_RCVR,
105 // 22-27 gem0
106 [22] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_PULLUP,
107 [23] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_PULLUP,
108 [24] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_PULLUP,
109 [25] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_PULLUP,
110 [26] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_PULLUP,
111 [27] = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_HSTL | MIO_PULLUP,
112 [28] = MIO_L1_SEL | MIO_IO_TYPE_LVCMOS18,
113 [29] = MIO_TRI_ENABLE | MIO_L1_SEL | MIO_IO_TYPE_LVCMOS18,
114 [30] = MIO_L1_SEL | MIO_IO_TYPE_LVCMOS18,
115 [31] = MIO_TRI_ENABLE | MIO_L1_SEL | MIO_IO_TYPE_LVCMOS18,
116 [32] = MIO_L1_SEL | MIO_IO_TYPE_LVCMOS18,
117 [33] = MIO_L1_SEL | MIO_IO_TYPE_LVCMOS18,
118 [34] = MIO_L1_SEL | MIO_IO_TYPE_LVCMOS18,
119 [35] = MIO_L1_SEL | MIO_IO_TYPE_LVCMOS18,
120 [36] = MIO_TRI_ENABLE | MIO_L1_SEL | MIO_IO_TYPE_LVCMOS18,
121 [37] = MIO_L1_SEL | MIO_IO_TYPE_LVCMOS18,
122 [38] = MIO_L1_SEL | MIO_IO_TYPE_LVCMOS18,
123 [39] = MIO_L1_SEL | MIO_IO_TYPE_LVCMOS18,
124 [40] = MIO_L3_SEL(0x4) | MIO_IO_TYPE_LVCMOS18,
125 [41] = MIO_L3_SEL(0x4) | MIO_IO_TYPE_LVCMOS18,
126 [42] = MIO_L3_SEL(0x4) | MIO_IO_TYPE_LVCMOS18,
127 [43] = MIO_L3_SEL(0x4) | MIO_IO_TYPE_LVCMOS18,
128 [44] = MIO_L3_SEL(0x4) | MIO_IO_TYPE_LVCMOS18,
129 [45] = MIO_L3_SEL(0x4) | MIO_IO_TYPE_LVCMOS18,
130 [46] = MIO_TRI_ENABLE | MIO_IO_TYPE_LVCMOS18,
131 [47] = MIO_IO_TYPE_LVCMOS18,
132 [48] = MIO_L3_SEL(0x7) | MIO_IO_TYPE_LVCMOS18,
133 [49] = MIO_TRI_ENABLE | MIO_L3_SEL(0x7) | MIO_IO_TYPE_LVCMOS18,
134 [50] = MIO_TRI_ENABLE | MIO_IO_TYPE_LVCMOS18,
135 [51] = MIO_IO_TYPE_LVCMOS18,
136 // 52-53 gem0
137 [52] = MIO_L3_SEL(0x4) | MIO_IO_TYPE_LVCMOS18 | MIO_PULLUP,
138 [53] = MIO_L3_SEL(0x4) | MIO_IO_TYPE_LVCMOS18 | MIO_PULLUP,
139 };
140
141 const zynq_clk_cfg_t zynq_clk_cfg = {
142 .arm_clk = ARM_CLK_CTRL_DIVISOR(2) | ARM_CLK_CTRL_CPU_6OR4XCLKACT |
143 ARM_CLK_CTRL_CPU_3OR2XCLKACT | ARM_CLK_CTRL_CPU_2XCLKACT |
144 ARM_CLK_CTRL_CPU_1XCLKACT | ARM_CLK_CTRL_PERI_CLKACT,
145 .ddr_clk = DDR_CLK_CTRL_DDR_3XCLKACT | DDR_CLK_CTRL_DDR_2XCLKACT |
146 DDR_CLK_CTRL_DDR_3XCLK_DIV(2) | DDR_CLK_CTRL_DDR_2XCLK_DIV(3),
147 .dci_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(35) | CLK_CTRL_DIVISOR1(3),
148 .gem0_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(8) | CLK_CTRL_DIVISOR1(1),
149 .gem0_rclk = CLK_CTRL_CLKACT,
150 .lqspi_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(5),
151 .sdio_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(20),
152 .uart_clk = CLK_CTRL_CLKACT1 | CLK_CTRL_DIVISOR0(20),
153 .pcap_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(5),
154 .fpga0_clk = CLK_CTRL_DIVISOR0(10) | CLK_CTRL_DIVISOR1(1),
155 .fpga1_clk = CLK_CTRL_DIVISOR0(10) | CLK_CTRL_DIVISOR1(1),
156 .fpga2_clk = CLK_CTRL_DIVISOR0(30) | CLK_CTRL_DIVISOR1(1),
157 .fpga3_clk = CLK_CTRL_DIVISOR0(20) | CLK_CTRL_DIVISOR1(1),
158 .aper_clk = DMA_CPU_CLK_EN | USB0_CPU_CLK_EN | USB1_CPU_CLK_EN | GEM0_CPU_CLK_EN |
159 SDI0_CPU_CLK_EN | I2C0_CPU_CLK_EN | I2C1_CPU_CLK_EN | UART1_CPU_CLK_EN |
160 GPIO_CPU_CLK_EN | LQSPI_CPU_CLK_EN | SMC_CPU_CLK_EN,
161 .clk_621_true = CLK_621_ENABLE,
162 };
163
target_early_init(void)164 void target_early_init(void) {
165 gpio_config(GPIO_LEDR, GPIO_OUTPUT);
166 gpio_set(GPIO_LEDR, 0);
167 }
168
target_init(void)169 void target_init(void) {
170 gem_init(GEM0_BASE);
171 }
172
target_set_debug_led(unsigned int led,bool on)173 void target_set_debug_led(unsigned int led, bool on) {
174 if (led == 0)
175 gpio_set(GPIO_LEDR, on);
176 }
177
178