1 /* 2 * Copyright 2014, General Dynamics C4 Systems 3 * 4 * SPDX-License-Identifier: GPL-2.0-only 5 */ 6 7 #pragma once 8 9 #include <stdint.h> 10 11 /* 12 * Samsung Exynos multi-core timer implementation 13 * Samsung has a habit of ripping out ARM IP and 14 * replacing it with their own. 15 */ 16 17 #define GCNTWSTAT_CNTH (1U << 1) 18 #define GCNTWSTAT_CNTL (1U << 0) 19 20 #define GTCON_EN (1U << 8) 21 #define GTCON_COMP3_AUTOINC (1U << 7) 22 #define GTCON_COMP3_EN (1U << 6) 23 #define GTCON_COMP2_AUTOINC (1U << 5) 24 #define GTCON_COMP2_EN (1U << 4) 25 #define GTCON_COMP1_AUTOINC (1U << 3) 26 #define GTCON_COMP1_EN (1U << 2) 27 #define GTCON_COMP0_AUTOINC (1U << 1) 28 #define GTCON_COMP0_EN (1U << 0) 29 30 #define GINT_COMP3_IRQ (1U << 3) 31 #define GINT_COMP2_IRQ (1U << 2) 32 #define GINT_COMP1_IRQ (1U << 1) 33 #define GINT_COMP0_IRQ (1U << 0) 34 35 #define GWSTAT_TCON (1U << 16) 36 #define GWSTAT_COMP3_ADD_INC (1U << 14) 37 #define GWSTAT_COMP3H (1U << 13) 38 #define GWSTAT_COMP3L (1U << 12) 39 #define GWSTAT_COMP2_ADD_INC (1U << 10) 40 #define GWSTAT_COMP2H (1U << 9) 41 #define GWSTAT_COMP2L (1U << 8) 42 #define GWSTAT_COMP1_ADD_INC (1U << 6) 43 #define GWSTAT_COMP1H (1U << 5) 44 #define GWSTAT_COMP1L (1U << 4) 45 #define GWSTAT_COMP0_ADD_INC (1U << 2) 46 #define GWSTAT_COMP0H (1U << 1) 47 #define GWSTAT_COMP0L (1U << 0) 48 49 #define LTCON_XXX0 (1U << 3) 50 #define LTCON_INTERVAL_MODE (1U << 2) 51 #define LTCON_IEN (1U << 1) 52 #define LTCON_EN (1U << 0) 53 54 #define LTWSTAT_TCON (1U << 3) 55 #define LTWSTAT_TCOMP (1U << 1) 56 #define LTWSTAT_TCNT (1U << 0) 57 58 59 60 struct mct_global_map { 61 uint32_t reserved0[64]; 62 uint32_t cntl; /* 0x100 Low word of count */ 63 uint32_t cnth; /* 0x104 High word of count */ 64 uint32_t reserved1[1]; 65 uint32_t cnt_wstat; /* 0x110 Write status for cnt */ 66 uint32_t reserved2[60]; 67 68 uint32_t comp0l; /* 0x200 Low word of Compare value */ 69 uint32_t comp0h; /* 0x204 High word of Compare value*/ 70 uint32_t comp0_add_inc; /* 0x208 Low word of Automatic increment amount */ 71 uint32_t comp0_res; 72 73 uint32_t comp1l; /* 0x210 Low word of Compare value */ 74 uint32_t comp1h; /* 0x214 High word of Compare value*/ 75 uint32_t comp1_add_inc; /* 0x218 Low word of Automatic increment amount */ 76 uint32_t comp1_res; 77 78 uint32_t comp2l; /* 0x220 Low word of Compare value */ 79 uint32_t comp2h; /* 0x224 High word of Compare value*/ 80 uint32_t comp2_add_inc; /* 0x228 Low word of Automatic increment amount */ 81 uint32_t comp2_res; 82 83 uint32_t comp3l; /* 0x230 Low word of Compare value */ 84 uint32_t comp3h; /* 0x234 High word of Compare value*/ 85 uint32_t comp3_add_inc; /* 0x238 Low word of Automatic increment amount */ 86 uint32_t comp3_res; 87 88 uint32_t tcon; /* 0x240 Timer control */ 89 uint32_t int_stat; /* 0x244 Interrupt pending status */ 90 uint32_t int_en; /* 0x248 Interrupt enable */ 91 uint32_t wstat; /* 0x24C write status */ 92 uint32_t reserved3[44]; 93 }; 94 95 struct mct_local_map { 96 uint32_t tcompl; /* 0x00 */ 97 uint32_t tcntl; /* 0x04 */ 98 uint32_t tcomph; /* 0x08 */ 99 uint32_t tcnth; /* 0x0C */ 100 uint32_t reserved0[4]; 101 uint32_t tcon; /* 0x20 Timer control */ 102 uint32_t int_stat; /* 0x30 Interrupt status */ 103 uint32_t int_en; /* 0x34 Interrupt enable */ 104 uint32_t reserved1[2]; 105 uint32_t wstat; /* 0x40 Write status */ 106 uint32_t reserved2[50]; 107 }; 108 109 struct mct_map { 110 struct mct_global_map global; 111 struct mct_local_map local[4]; 112 }; 113 typedef volatile struct mct_map timer_t; 114 extern timer_t *mct; 115 mct_reset(void)116static inline void mct_reset(void) 117 { 118 mct->global.int_stat = mct->global.int_stat; 119 } 120 mct_clear_write_status(void)121static inline void mct_clear_write_status(void) 122 { 123 /* Clear write status */ 124 mct->global.wstat = mct->global.wstat; 125 mct->global.cnt_wstat = mct->global.cnt_wstat; 126 } 127 128 129