1#
2# Copyright 2020, Data61, CSIRO (ABN 41 687 119 230)
3#
4# SPDX-License-Identifier: GPL-2.0-only
5#
6
7cmake_minimum_required(VERSION 3.7.2)
8
9if(KernelArchARM)
10    set_property(TARGET kernel_config_target APPEND PROPERTY TOPLEVELTYPES pde_C)
11endif()
12
13set(KernelArmPASizeBits40 OFF)
14set(KernelArmPASizeBits44 OFF)
15if(KernelArmCortexA35)
16    set(KernelArmICacheVIPT ON)
17    set(KernelArmPASizeBits40 ON)
18    math(EXPR KernelPaddrUserTop "(1 << 40)")
19elseif(KernelArmCortexA53)
20    set(KernelArmICacheVIPT ON)
21    set(KernelArmPASizeBits40 ON)
22    math(EXPR KernelPaddrUserTop "(1 << 40)")
23elseif(KernelArmCortexA55)
24    set(KernelArmICacheVIPT ON)
25    set(KernelArmPASizeBits40 ON)
26    math(EXPR KernelPaddrUserTop "(1 << 40)")
27elseif(KernelArmCortexA57)
28    set(KernelArmPASizeBits44 ON)
29    math(EXPR KernelPaddrUserTop "(1 << 44)")
30elseif(KernelArmCortexA72)
31    # For Cortex-A72 in AArch64 state, the physical address range is 44 bits
32    # (https://developer.arm.com/documentation/100095/0001/memory-management-unit/about-the-mmu)
33    set(KernelArmPASizeBits44 ON)
34    math(EXPR KernelPaddrUserTop "(1 << 44)")
35endif()
36config_set(KernelArmPASizeBits40 ARM_PA_SIZE_BITS_40 "${KernelArmPASizeBits40}")
37config_set(KernelArmPASizeBits44 ARM_PA_SIZE_BITS_44 "${KernelArmPASizeBits44}")
38config_set(KernelArmICacheVIPT ARM_ICACHE_VIPT "${KernelArmICacheVIPT}")
39
40if(KernelSel4ArchAarch32)
41    # 64-bit targets may be building in 32-bit mode,
42    # so make sure maximum paddr is 32-bit.
43    math(EXPR KernelPaddrUserTop "(1 << 32) - 1")
44endif()
45
46include(src/arch/arm/armv/armv7-a/config.cmake)
47include(src/arch/arm/armv/armv8-a/config.cmake)
48
49config_option(
50    KernelDebugDisableL2Cache DEBUG_DISABLE_L2_CACHE
51    "Do not enable the L2 cache on startup for debugging purposes."
52    DEFAULT OFF
53    DEPENDS "KernelArchARM"
54)
55config_option(
56    KernelDebugDisableL1ICache DEBUG_DISABLE_L1_ICACHE
57    "Do not enable the L1 instruction cache on startup for debugging purposes."
58    DEFAULT OFF
59    DEPENDS "KernelArchARM;KernelDebugDisableL2Cache"
60)
61config_option(
62    KernelDebugDisableL1DCache DEBUG_DISABLE_L1_DCACHE
63    "Do not enable the L1 data cache on startup for debugging purposes."
64    DEFAULT OFF
65    DEPENDS "KernelArchARM;KernelDebugDisableL2Cache"
66)
67config_option(
68    KernelDebugDisableBranchPrediction DEBUG_DISABLE_BRANCH_PREDICTION
69    "Do not enable branch prediction (also called program flow control) on startup. \
70    This makes execution time more deterministic at the expense of dramatically decreasing \
71    performance. Primary use is for debugging."
72    DEFAULT OFF
73    DEPENDS "KernelArchARM"
74)
75
76if(NOT DEFINED KernelSel4ArchArmHyp)
77    # the current CMake scripts ensure that KernelSel4ArchArmHyp is always set
78    # to either ON or OFF. If it is not set, something is either broken or the
79    # CMake files are used wrongly. Or support for KernelSel4ArchArmHyp has
80    # finally been removed - and then this check here should be removed and the
81    # KernelArmHypervisorSupport below can be OFF by default.
82    message(FATAL_ERROR "KernelSel4ArchArmHyp must be ON or OFF")
83endif()
84config_option(
85    KernelArmHypervisorSupport ARM_HYPERVISOR_SUPPORT
86    "Build as Hypervisor. Utilise ARM virtualisation extensions to build the kernel as a hypervisor"
87    DEFAULT ${KernelSel4ArchArmHyp}
88    DEPENDS
89        "KernelArmCortexA15 OR KernelArmCortexA35 OR KernelArmCortexA57 OR KernelArmCortexA53 OR KernelArmCortexA55 OR KernelArmCortexA72"
90)
91
92config_option(KernelArmGicV3 ARM_GIC_V3_SUPPORT "Build support for GICv3" DEFAULT OFF)
93
94if(KernelArmPASizeBits40 AND ARM_HYPERVISOR_SUPPORT)
95    config_set(KernelAarch64VspaceS2StartL1 AARCH64_VSPACE_S2_START_L1 "ON")
96else()
97    config_set(KernelAarch64VspaceS2StartL1 AARCH64_VSPACE_S2_START_L1 "OFF")
98endif()
99
100config_option(
101    KernelArmHypEnableVCPUCP14SaveAndRestore ARM_HYP_ENABLE_VCPU_CP14_SAVE_AND_RESTORE
102    "Trap, but don't save/restore VCPUs' CP14 accesses \
103    This allows us to turn off the save and restore of VCPU threads' CP14 \
104    context for performance (or other) reasons, we can just turn them off \
105    and trap them instead, and have the VCPUs' accesses to CP14 \
106    intercepted and delivered to the VM Monitor as fault messages"
107    DEFAULT ON
108    DEPENDS "KernelSel4ArchArmHyp;NOT KernelVerificationBuild"
109    DEFAULT_DISABLED OFF
110)
111
112config_option(
113    KernelArmErrata430973 ARM_ERRATA_430973
114    "Enable workaround for 430973 Cortex-A8 (r1p0..r1p2) erratum \
115    Enables a workaround for the 430973 Cortex-A8 (r1p0..r1p2) erratum. Error occurs \
116    if code containing ARM/Thumb interworking branch is replaced by different code \
117    at the same virtual address."
118    DEFAULT OFF
119    DEPENDS "KernelArchARM;KernelArmCortexA8"
120)
121
122config_option(
123    KernelArmErrata773022 ARM_ERRATA_773022
124    "Enable workaround for 773022 Cortex-A15 (r0p0..r0p4) erratum \
125    Enables a workaround for the 773022 Cortex-A15 (r0p0..r0p4) erratum. Error occurs \
126    on rare sequences of instructions and results in the loop buffer delivering \
127    incorrect instructions. The work around is to disable the loop buffer"
128    DEFAULT ON
129    DEPENDS "KernelArchARM;KernelArmCortexA15"
130    DEFAULT_DISABLED OFF
131)
132
133config_option(KernelArmSMMU ARM_SMMU "Enable SystemMMU" DEFAULT OFF DEPENDS "KernelPlatformTx2")
134
135config_option(
136    KernelTk1SMMU TK1_SMMU "Enable SystemMMU for the Tegra TK1 SoC"
137    DEFAULT OFF
138    DEPENDS "KernelPlatformTK1"
139)
140
141config_option(KernelArmEnableA9Prefetcher ENABLE_A9_PREFETCHER "Enable Cortex-A9 prefetcher \
142    Cortex-A9 has an L1 and L2 prefetcher. By default \
143    they are disabled. This config options allows \
144    them to be turned on. Enabling the prefetchers \
145    requires that the kernel be in secure mode. ARM \
146    documents indicate that as of r4p1 version of \
147    Cortex-A9 the bits used to enable the prefetchers \
148    no longer exist, it is not clear if this is just \
149    a document error or not." DEFAULT OFF DEPENDS "KernelArmCortexA9")
150
151config_option(
152    KernelArmExportPMUUser EXPORT_PMU_USER "PL0 access to PMU. \
153    Grant user access to Performance Monitoring Unit. \
154    WARNING: While useful for evaluating performance, \
155    this option opens timing and covert channels."
156    DEFAULT OFF
157    DEPENDS "KernelArchArmV7a OR KernelArchArmV8a;NOT KernelArmCortexA8"
158)
159
160config_option(
161    KernelArmDisableWFIWFETraps DISABLE_WFI_WFE_TRAPS "Disable the trapping of WFI \
162    and WFE instructions when configuring the \
163    Hyp Configuration Registor (HCR) of a VCPU"
164    DEFAULT OFF
165    DEPENDS "KernelArchArmV7a OR KernelArchArmV8a;KernelArmHypervisorSupport"
166)
167config_option(KernelTk1SMMUInterruptEnable SMMU_INTERRUPT_ENABLE "Enable SMMU interrupts. \
168    SMMU interrupts currently only serve a debug purpose as \
169    they are not forwarded to user level. Enabling this will \
170    cause some fault types to print out a message in the kernel. \
171    WARNING: Printing fault information is slow and rapid faults \
172    can result in all time spent in the kernel printing fault \
173    messages" DEFAULT "${KernelDebugBuild}" DEPENDS "KernelTk1SMMU" DEFAULT_DISABLED OFF)
174
175config_option(
176    KernelAArch32FPUEnableContextSwitch AARCH32_FPU_ENABLE_CONTEXT_SWITCH
177    "Enable hardware VFP and SIMD context switch \
178        This enables the VFP and SIMD context switch on platforms with \
179        hardware support, allowing the user to execute hardware VFP and SIMD \
180        operations in a multithreading environment, instead of relying on \
181        software emulation of FPU/VFP from the C library (e.g. mfloat-abi=soft)."
182    DEFAULT ON
183    DEPENDS "KernelSel4ArchAarch32;NOT KernelVerificationBuild"
184    DEFAULT_DISABLED OFF
185)
186
187config_option(
188    KernelAArch64SErrorIgnore AARCH64_SERROR_IGNORE
189    "By default any SError interrupt will halt the kernel. SErrors may \
190    be caused by e.g. writes to read-only device registers or ECC errors. \
191    When this option is enabled SErrors will be ignored."
192    DEFAULT OFF
193    DEPENDS "KernelSel4ArchAarch64;NOT KernelVerificationBuild"
194)
195mark_as_advanced(KernelAArch64SErrorIgnore)
196
197if(KernelAArch32FPUEnableContextSwitch OR KernelSel4ArchAarch64)
198    set(KernelHaveFPU ON)
199endif()
200
201if(KernelSel4ArchAarch64)
202    set(KernelHardwareDebugAPIUnsupported ON CACHE INTERNAL "")
203endif()
204
205if(
206    KernelArmCortexA7
207    OR KernelArmCortexA8
208    OR KernelArmCortexA15
209    OR KernelArmCortexA35
210    OR KernelArmCortexA53
211    OR KernelArmCortexA55
212    OR KernelArmCortexA57
213    OR KernelArmCortexA72
214)
215    # According to https://developer.arm.com/documentation/100095/0001/functional-description/about-the-cortex-a72-processor-functions/components-of-the-processor
216    # the L1 instruction on the Cortex-A72 cache has a 64-byte cache line.
217    # Thus, 6 bits are needed.
218    config_set(KernelArmCacheLineSizeBits L1_CACHE_LINE_SIZE_BITS "6")
219elseif(KernelArmCortexA9)
220    config_set(KernelArmCacheLineSizeBits L1_CACHE_LINE_SIZE_BITS "5")
221endif()
222
223add_sources(
224    DEP "KernelArchARM"
225    PREFIX src/arch/arm
226    CFILES
227        c_traps.c
228        api/faults.c
229        benchmark/benchmark.c
230        kernel/boot.c
231        kernel/thread.c
232        machine/cache.c
233        machine/errata.c
234        machine/debug.c
235        machine/hardware.c
236        machine/io.c
237        object/interrupt.c
238        object/tcb.c
239        object/iospace.c
240        object/vcpu.c
241        object/smmu.c
242        smp/ipi.c
243)
244
245add_bf_source_old("KernelArchARM" "structures.bf" "include/arch/arm" "arch/object")
246
247include(src/arch/arm/${KernelWordSize}/config.cmake)
248