1/* 2 * Copyright Linux Kernel Team 3 * Copyright 2020, HENSOLDT Cyber GmbH 4 * 5 * SPDX-License-Identifier: GPL-2.0-only 6 * 7 * This file is derived from an intermediate build stage of the 8 * Linux kernel. The licenses of all input files to this process 9 * are compatible with GPL-2.0-only. 10 */ 11 12/dts-v1/; 13 14/ { 15 #address-cells = < 0x01 >; 16 #size-cells = < 0x01 >; 17 model = "Boundary Devices i.MX6 SoloX Nitrogen6sx Board"; 18 compatible = "boundary,imx6sx-nitrogen6sx\0fsl,imx6sx"; 19 20 chosen { 21 stdout-path = "/soc/aips-bus@2000000/spba-bus@2000000/serial@2020000"; 22 }; 23 24 memory@80000000 { 25 device_type = "memory"; 26 reg = < 0x80000000 0x40000000 >; 27 }; 28 29 regulators { 30 compatible = "simple-bus"; 31 #address-cells = < 0x01 >; 32 #size-cells = < 0x00 >; 33 34 regulator@1 { 35 compatible = "regulator-fixed"; 36 regulator-name = "3P3V"; 37 regulator-min-microvolt = < 0x325aa0 >; 38 regulator-max-microvolt = < 0x325aa0 >; 39 regulator-always-on; 40 phandle = < 0x35 >; 41 }; 42 }; 43 44 aliases { 45 gpio0 = "/soc/aips-bus@2000000/gpio@209c000"; 46 gpio1 = "/soc/aips-bus@2000000/gpio@20a0000"; 47 gpio2 = "/soc/aips-bus@2000000/gpio@20a4000"; 48 gpio3 = "/soc/aips-bus@2000000/gpio@20a8000"; 49 gpio4 = "/soc/aips-bus@2000000/gpio@20ac000"; 50 gpio5 = "/soc/aips-bus@2000000/gpio@20b0000"; 51 gpio6 = "/soc/aips-bus@2000000/gpio@20b4000"; 52 i2c0 = "/soc/aips-bus@2100000/i2c@21a0000"; 53 i2c1 = "/soc/aips-bus@2100000/i2c@21a4000"; 54 i2c2 = "/soc/aips-bus@2100000/i2c@21a8000"; 55 serial0 = "/soc/aips-bus@2000000/spba-bus@2000000/serial@2020000"; 56 serial1 = "/soc/aips-bus@2100000/serial@21e8000"; 57 serial2 = "/soc/aips-bus@2100000/serial@21ec000"; 58 serial3 = "/soc/aips-bus@2100000/serial@21f0000"; 59 serial4 = "/soc/aips-bus@2100000/serial@21f4000"; 60 serial5 = "/soc/aips-bus@2100000/serial@22a0000"; 61 ethernet0 = "/soc/aips-bus@2100000/ethernet@2188000"; 62 ethernet1 = "/soc/aips-bus@2100000/ethernet@21b4000"; 63 }; 64 65 cpus { 66 #address-cells = < 0x01 >; 67 #size-cells = < 0x00 >; 68 69 cpu@0 { 70 compatible = "arm,cortex-a9"; 71 device_type = "cpu"; 72 reg = < 0x00 >; 73 next-level-cache = < 0x67 >; 74 operating-points = < 0xf32a0 0x1312d0 0xc15c0 0x11edd8 0x60ae0 0x106738 0x30570 0xee098 >; 75 fsl,soc-operating-points = < 0xf32a0 0x11edd8 0xc15c0 0x11edd8 0x60ae0 0x11edd8 0x30570 0x11edd8 >; 76 clock-latency = < 0xee6c >; 77 #cooling-cells = < 0x02 >; 78 clocks = < 0x04 0x81 0x04 0x14 0x04 0x23 0x04 0x24 0x04 0x04 >; /* TODO: &clks */ 79 clock-names = "arm\0pll2_pfd2_396m\0step\0pll1_sw\0pll1_sys"; /* TODO */ 80 arm-supply = < 0x68 >; 81 soc-supply = < 0x69 >; 82 nvmem-cells = < 0xd1 >; 83 nvmem-cell-names = "speed_grade"; 84 }; 85 }; 86 87 clocks { 88 89 ckil { 90 compatible = "fixed-clock"; 91 #clock-cells = < 0x00 >; 92 clock-frequency = < 0x8000 >; 93 clock-output-names = "ckil"; 94 phandle = < 0xd2 >; 95 }; 96 97 osc { 98 compatible = "fixed-clock"; 99 #clock-cells = < 0 >; 100 clock-frequency = < 0x16e3600 >; 101 clock-output-names = "osc"; 102 phandle = < 0xd3 >; 103 }; 104 105 ipp_di0 { 106 compatible = "fixed-clock"; 107 #clock-cells = < 0x00 >; 108 clock-frequency = < 0x00 >; 109 clock-output-names = "ipp_di0"; 110 phandle = < 0xd4 >; 111 }; 112 113 ipp_di1 { 114 compatible = "fixed-clock"; 115 #clock-cells = < 0x00 >; 116 clock-frequency = < 0x00 >; 117 clock-output-names = "ipp_di1"; 118 phandle = < 0xd5 >; 119 }; 120 121 anaclk1 { 122 compatible = "fixed-clock"; 123 #clock-cells = < 0x00 >; 124 clock-frequency = < 0x00 >; 125 clock-output-names = "anaclk1"; 126 phandle = < 0xd6 >; 127 }; 128 129 anaclk2 { 130 compatible = "fixed-clock"; 131 #clock-cells = < 0x00 >; 132 clock-frequency = < 0x00 >; 133 clock-output-names = "anaclk2"; 134 phandle = < 0xd7 >; 135 }; 136 }; 137 138 soc { 139 #address-cells = < 0x01 >; 140 #size-cells = < 0x01 >; 141 compatible = "simple-bus"; 142 interrupt-parent = < 0x01 >; 143 ranges; 144 145 /* taken from seL4 sabre.dts */ 146 timer@a00600 { 147 compatible = "arm,cortex-a9-twd-timer"; 148 reg = < 0xa00600 0x20 >; 149 interrupts = < 0x01 0x0d 0xf01 >; 150 interrupt-parent = < 0x16 >; 151 clocks = < 0x04 0x1e >; 152 }; 153 154 interrupt-controller@a01000 { 155 compatible = "arm,cortex-a9-gic"; 156 #interrupt-cells = < 0x03 >; 157 interrupt-controller; 158 reg = < 0xa01000 0x1000 0xa00100 0x100 >; 159 interrupt-parent = < 0x16 >; 160 phandle = < 0x16 >; 161 }; 162 163 l2-cache@a02000 { 164 compatible = "arm,pl310-cache"; 165 reg = < 0x00a02000 0x1000 >; 166 interrupts = < 0x00 0x5c 0x04 >; 167 cache-unified; 168 cache-level = < 0x02 >; 169 arm,tag-latency = < 0x04 0x02 0x03 >; 170 arm,data-latency = < 0x04 0x02 0x03 >; 171 phandle = < 0x67 >; 172 }; 173 174 aips-bus@2000000 { 175 compatible = "fsl,aips-bus\0simple-bus"; 176 #address-cells = < 0x01 >; 177 #size-cells = < 0x01 >; 178 reg = < 0x2000000 0x100000 >; 179 ranges; 180 181 spba-bus@2000000 { 182 compatible = "fsl,spba-bus\0simple-bus"; 183 #address-cells = < 0x01 >; 184 #size-cells = < 0x01 >; 185 reg = < 0x2000000 0x40000 >; 186 ranges; 187 188 serial@2020000 { 189 compatible = "fsl,imx6sx-uart\0fsl,imx6q-uart\0fsl,imx21-uart"; 190 reg = < 0x2020000 0x4000 >; 191 interrupts = < 0x00 0x1a 0x04 >; 192 clocks = < 0x04 0xcc 0x04 0xcd >; 193 clock-names = "ipg\0per"; 194 dmas = < 0x17 0x19 0x04 0x00 0x17 0x1a 0x04 0x00 >; 195 dma-names = "rx\0tx"; 196 pinctrl-names = "default"; 197 pinctrl-0 = < 0x1a >; 198 status = "okay"; 199 }; 200 }; 201 202 gpt@2098000 { 203 compatible = "fsl,imx6sx-gpt\0fsl,imx6dl-gpt\0fsl,imx31-gpt"; 204 reg = < 0x2098000 0x4000 >; 205 interrupts = < 0x00 0x37 0x04 >; 206 clocks = < 0x04 0x9a 0x04 0xe3 >; 207 clock-names = "ipg\0per"; 208 }; 209 210 gpio@209c000 { 211 compatible = "fsl,imx6sx-gpio\0fsl,imx35-gpio"; 212 reg = < 0x209c000 0x4000 >; 213 interrupts = < 0x00 0x42 0x04 0x00 0x43 0x04 >; 214 gpio-controller; 215 #gpio-cells = < 0x02 >; 216 interrupt-controller; 217 #interrupt-cells = < 0x02 >; 218 gpio-ranges = < 0x22 0 5 26 >; 219 phandle = < 0x43 >; 220 }; 221 222 gpio@20a0000 { 223 compatible = "fsl,imx6sx-gpio\0fsl,imx35-gpio"; 224 reg = < 0x20a0000 0x4000 >; 225 interrupts = < 0x00 0x44 0x04 0x00 0x45 0x04 >; 226 gpio-controller; 227 #gpio-cells = < 0x02 >; 228 interrupt-controller; 229 #interrupt-cells = < 0x02 >; 230 gpio-ranges = < 0x22 0 31 20 >; 231 phandle = < 0x37 >; 232 }; 233 234 gpio@20a4000 { 235 compatible = "fsl,imx6sx-gpio\0fsl,imx35-gpio"; 236 reg = < 0x20a4000 0x4000 >; 237 interrupts = < 0x00 0x46 0x04 0x00 0x47 0x04 >; 238 gpio-controller; 239 #gpio-cells = < 0x02 >; 240 interrupt-controller; 241 #interrupt-cells = < 0x02 >; 242 gpio-ranges = < 0x22 0 51 29 >; 243 phandle = < 0x18 >; 244 }; 245 246 gpio@20a8000 { 247 compatible = "fsl,imx6sx-gpio\0fsl,imx35-gpio"; 248 reg = < 0x20a8000 0x4000 >; 249 interrupts = < 0x00 0x48 0x04 0x00 0x49 0x04 >; 250 gpio-controller; 251 #gpio-cells = < 0x02 >; 252 interrupt-controller; 253 #interrupt-cells = < 0x02 >; 254 gpio-ranges = < 0x22 0 80 32 >; 255 phandle = < 0x76 >; 256 }; 257 258 gpio@20ac000 { 259 compatible = "fsl,imx6sx-gpio\0fsl,imx35-gpio"; 260 reg = < 0x20ac000 0x4000 >; 261 interrupts = < 0x00 0x4a 0x04 0x00 0x4b 0x04 >; 262 gpio-controller; 263 #gpio-cells = < 0x02 >; 264 interrupt-controller; 265 #interrupt-cells = < 0x02 >; 266 gpio-ranges = < 0x22 0 112 24 >; 267 }; 268 269 gpio@20b0000 { 270 compatible = "fsl,imx6sx-gpio\0fsl,imx35-gpio"; 271 reg = < 0x20b0000 0x4000 >; 272 interrupts = < 0x00 0x4c 0x04 0x00 0x4d 0x04 >; 273 gpio-controller; 274 #gpio-cells = < 0x02 >; 275 interrupt-controller; 276 #interrupt-cells = < 0x02 >; 277 gpio-ranges = < 0x22 0 136 12 0x22 12 158 11 >; 278 phandle = < 0x40 >; 279 }; 280 281 gpio@20b4000 { 282 compatible = "fsl,imx6sx-gpio\0fsl,imx35-gpio"; 283 reg = < 0x20b4000 0x4000 >; 284 interrupts = < 0x00 0x4e 0x04 0x00 0x4f 0x04 >; 285 gpio-controller; 286 #gpio-cells = < 0x02 >; 287 interrupt-controller; 288 #interrupt-cells = < 0x02 >; 289 gpio-ranges = < 0x22 0 148 10 0x22 10 169 2 >; 290 phandle = < 0x34 >; 291 }; 292 293 ccm@20c4000 { 294 compatible = "fsl,imx6sx-ccm"; 295 reg = < 0x20c4000 0x4000 >; 296 interrupts = < 0x00 0x57 0x04 0x00 0x58 0x04 >; 297 #clock-cells = < 0x01 >; 298 clocks = < 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 >; 299 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2"; 300 phandle = < 0x04 >; 301 }; 302 303 src@20d8000 { 304 compatible = "fsl,imx6sx-src\0fsl,imx51-src"; 305 reg = < 0x20d8000 0x4000 >; 306 interrupts = < 0x00 0x5b 0x04 0x00 0x60 0x04 >; 307 #reset-cells = < 0x01 >; 308 phandle = < 0x1b >; /* TODO */ 309 }; 310 311 epit@20d0000 { 312 reg = < 0x20d0000 0x4000 >; 313 interrupts = < 0x00 0x38 0x04 >; 314 }; 315 316 epit@20d4000 { 317 reg = < 0x20d4000 0x4000 >; 318 interrupts = < 0x00 0x39 0x04 >; 319 }; 320 321 anatop@20c8000 { 322 compatible = "fsl,imx6sx-anatop\0fsl,imx6q-anatop\0syscon\0simple-mfd"; 323 reg = < 0x20c8000 0x1000 >; 324 interrupts = < 0x00 0x31 0x04 0x00 0x36 0x04 0x00 0x7f 0x04 >; 325 phandle = < 0x02 >; /* TODO */ 326 327 regulator-vddcore { 328 compatible = "fsl,anatop-regulator"; 329 regulator-name = "vddarm"; 330 regulator-min-microvolt = < 0xb1008 >; 331 regulator-max-microvolt = < 0x162010 >; 332 regulator-always-on; 333 anatop-reg-offset = < 0x140 >; 334 anatop-vol-bit-shift = < 0x00 >; 335 anatop-vol-bit-width = < 0x05 >; 336 anatop-delay-reg-offset = < 0x170 >; 337 anatop-delay-bit-shift = < 0x18 >; 338 anatop-delay-bit-width = < 0x02 >; 339 anatop-min-bit-val = < 0x01 >; 340 anatop-min-voltage = < 0xb1008 >; 341 anatop-max-voltage = < 0x162010 >; 342 phandle = < 0x68 >; 343 }; 344 345 regulator-vddsoc { 346 compatible = "fsl,anatop-regulator"; 347 regulator-name = "vddsoc"; 348 regulator-min-microvolt = < 0xb1008 >; 349 regulator-max-microvolt = < 0x162010 >; 350 regulator-always-on; 351 anatop-reg-offset = < 0x140 >; 352 anatop-vol-bit-shift = < 0x12 >; 353 anatop-vol-bit-width = < 0x05 >; 354 anatop-delay-reg-offset = < 0x170 >; 355 anatop-delay-bit-shift = < 0x1c >; 356 anatop-delay-bit-width = < 0x02 >; 357 anatop-min-bit-val = < 0x01 >; 358 anatop-min-voltage = < 0xb1008 >; 359 anatop-max-voltage = < 0x162010 >; 360 phandle = < 0x69 >; 361 }; 362 }; 363 364 gpc@20dc000 { 365 compatible = "fsl,imx6sx-gpc\0fsl,imx6q-gpc"; 366 reg = < 0x20dc000 0x4000 >; 367 interrupt-controller; 368 #interrupt-cells = < 0x03 >; 369 interrupts = < 0x00 0x59 0x04 >; 370 interrupt-parent = < 0x16 >; 371 clocks = < 0x04 0x52 >; 372 clock-names = "ipg"; 373 phandle = < 0x01 >; 374 375 pgc { 376 #address-cells = < 0x01 >; 377 #size-cells = < 0x00 >; 378 379 power-domain@0 { 380 reg = < 0x00 >; 381 #power-domain-cells = < 0x00 >; 382 }; 383 384 power-domain@1 { 385 reg = < 0x01 >; 386 #power-domain-cells = < 0x00 >; 387 power-supply = < 0x69 >; 388 clocks = < 0x04 0x9c >; 389 phandle = < 0x15 >; 390 }; 391 392 power-domain@2 { 393 reg = < 0x02 >; 394 #power-domain-cells = < 0x00 >; 395 clocks = < 0x04 0xaa 0x04 0xad 0x04 0xaf 0x04 0xa9 0x04 0xae 0x04 0x9f 0x04 0xd7 >; 396 }; 397 398 power-domain@3 { 399 reg = < 0x03 >; 400 #power-domain-cells = < 0x00 >; 401 power-supply = < 0x24 >; 402 }; 403 }; 404 }; 405 406 iomuxc@20e0000 { 407 compatible = "fsl,imx6sx-iomuxc"; 408 reg = <0x020e0000 0x4000>; 409 pinctrl-names = "default"; 410 pinctrl-0 = < 0x2b >; 411 phandle = < 0x22 >; 412 413 imx6sx-nitrogen6 { 414 415 hoggrp { 416 fsl,pins = < 0x0144 0x048C 0x0000 0x5 0x0 0x1b0b0 417 0x014C 0x0494 0x0000 0x5 0x0 0x1b0b0 418 0x0170 0x04B8 0x0000 0x5 0x0 0x1b0b0 419 0x0178 0x04C0 0x0000 0x5 0x0 0x1b0b0 420 0x017C 0x04C4 0x0000 0x5 0x0 0x1b0b0 421 0x0174 0x04BC 0x0000 0x5 0x0 0x1b0b0 422 0x0180 0x04C8 0x0000 0x5 0x0 0x1b0b0 423 0x0184 0x04CC 0x0000 0x5 0x0 0x1b0b0 424 0x0188 0x04D0 0x0000 0x5 0x0 0x1b0b0 425 0x018C 0x04D4 0x0000 0x5 0x0 0x1b0b0 426 0x0224 0x056C 0x0000 0x7 0x0 0x000b0 427 0x026C 0x05B4 0x0000 0x5 0x0 0x1b0b0 428 0x0160 0x04A8 0x0000 0x5 0x0 0x1b0b0 429 0x01A4 0x04EC 0x0000 0x5 0x0 0x1b0b0 430 >; 431 phandle = < 0x2b >; 432 }; 433 434 uart1grp { 435 fsl,pins = < 0x0024 0x036C 0x0000 0x0 0x0 0x1b0b1 0x0028 0x0370 0x0830 0x0 0x1 0x1b0b1 >; 436 phandle = < 0x1a >; 437 }; 438 439 i2c1grp { 440 fsl,pins = < 0x0014 0x035C 0x07A8 0x0 0x1 0x4001b8b1 0x0018 0x0360 0x07AC 0x0 0x1 0x4001b8b1 >; 441 phandle = < 0x38 >; 442 }; 443 444 i2c2grp { 445 fsl,pins = < 0x001C 0x0364 0x07B0 0x0 0x1 0x4001b8b1 0x0020 0x0368 0x07B4 0x0 0x1 0x4001b8b1 >; 446 phandle = < 0x3a >; 447 }; 448 449 i2c3grp { 450 fsl,pins = < 0x00B4 0x03FC 0x07B8 0x2 0x2 0x4001b8b1 0x00C8 0x0410 0x07BC 0x2 0x2 0x4001b8b1 >; 451 phandle = < 0x45 >; 452 }; 453 enetgrp { 454 fsl,pins = < 0x0088 0x03D0 0x0764 0x0 0x1 0x1b0b0 0x0084 0x03CC 0x0000 0x0 0x0 0x1b0b0 0x01D8 0x0520 0x0000 0x0 0x0 0x30b1 0x01DC 0x0524 0x0000 0x0 0x0 0x30b1 0x01E0 0x0528 0x0000 0x0 0x0 0x30b1 0x01E4 0x052C 0x0000 0x0 0x0 0x30b1 0x01EC 0x0534 0x0000 0x0 0x0 0x30b1 0x01E8 0x0530 0x0000 0x0 0x0 0x30b1 0x01C0 0x0508 0x0000 0x0 0x0 0x3081 0x01C4 0x050C 0x0000 0x0 0x0 0x3081 0x01D0 0x0518 0x0000 0x0 0x0 0x3081 0x01C8 0x0510 0x0000 0x0 0x0 0x3081 0x01CC 0x0514 0x0000 0x0 0x0 0x3081 0x01D4 0x051C 0x0768 0x0 0x1 0x3081 0x0098 0x03E0 0x0000 0x5 0x0 0xb0b0 0x008C 0x03D4 0x0000 0x5 0x0 0xb0b0 0x0090 0x03D8 0x0000 0x5 0x0 0xb0b0 >; 455 phandle = < 0x32 >; 456 }; 457 enetgrp2 { 458 fsl,pins = < 0x0208 0x0550 0x0000 0x0 0x0 0x30b1 0x020C 0x0554 0x0000 0x0 0x0 0x30b1 0x0210 0x0558 0x0000 0x0 0x0 0x30b1 0x0214 0x055C 0x0000 0x0 0x0 0x30b1 0x021C 0x0564 0x0000 0x0 0x0 0x30b1 0x0218 0x0560 0x0000 0x0 0x0 0x30b1 0x01F0 0x0538 0x0000 0x0 0x0 0x3081 0x01F4 0x053C 0x0000 0x0 0x0 0x3081 0x0200 0x0548 0x0000 0x0 0x0 0x3081 0x01F8 0x0540 0x0000 0x0 0x0 0x3081 0x01FC 0x0544 0x0000 0x0 0x0 0x3081 0x0204 0x054C 0x0774 0x0 0x1 0x3081 0x0094 0x03DC 0x0000 0x5 0x0 0xb0b0 0x009C 0x03E4 0x0000 0x5 0x0 0xb0b0 0x00A0 0x03E8 0x0000 0x5 0x0 0xb0b0 >; 459 phandle = < 0x33 >; 460 }; 461 }; 462 }; 463 464 iomuxc-gpr@20e4000 { 465 compatible = "fsl,imx6sx-iomuxc-gpr\0fsl,imx6q-iomuxc-gpr\0syscon"; 466 reg = <0x020e4000 0x4000>; 467 phandle = < 0x05 >; 468 }; 469 470 sdma@20ec000 { 471 compatible = "fsl,imx6sx-sdma\0fsl,imx6q-sdma"; 472 reg = < 0x20ec000 0x4000 >; 473 interrupts = < 0x00 0x02 0x04 >; 474 clocks = < 0x04 0x52 0x04 0xc3 >; 475 clock-names = "ipg\0ahb"; 476 #dma-cells = < 0x03 >; 477 /* imx6sx reuses imx6q sdma firmware */ 478 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 479 phandle = < 0x17 >; 480 }; 481 }; 482 483 aips-bus@2100000 { 484 compatible = "fsl,aips-bus\0simple-bus"; 485 #address-cells = < 0x01 >; 486 #size-cells = < 0x01 >; 487 reg = < 0x2100000 0x100000 >; 488 ranges; 489 490 ocotp@21bc000 { 491 #address-cells = < 0x01 >; 492 #size-cells = < 0x01 >; 493 compatible = "fsl,imx6sx-ocotp\0syscon"; 494 reg = < 0x21bc000 0x4000 >; 495 clocks = < 0x04 0xa3 >; 496 497 cpu_speed_grade { 498 reg = < 0x10 4 >; 499 phandle = < 0xd1 >; 500 }; 501 }; 502 503 i2c@21a0000 { 504 #address-cells = < 0x01 >; 505 #size-cells = < 0x00 >; 506 compatible = "fsl,imx6sx-i2c\0fsl,imx21-i2c"; 507 reg = < 0x21a0000 0x4000 >; 508 interrupts = < 0x00 0x24 0x04 >; 509 clocks = < 0x04 0xa0 >; 510 clock-frequency = < 0x186a0 >; 511 pinctrl-names = "default"; 512 pinctrl-0 = < 0x38 >; 513 status = "okay"; 514 515 /* ignored codec: sgtl5000@a */ 516 }; 517 518 i2c@21a4000 { 519 #address-cells = < 0x01 >; 520 #size-cells = < 0x00 >; 521 compatible = "fsl,imx6sx-i2c\0fsl,imx21-i2c"; 522 reg = < 0x21a4000 0x4000 >; 523 interrupts = < 0x00 0x25 0x04 >; 524 clocks = < 0x04 0xa1 >; 525 clock-frequency = < 0x186a0 >; 526 pinctrl-names = "default"; 527 pinctrl-0 = < 0x3a >; 528 phandle = < 0x10 >; 529 status = "okay"; 530 }; 531 532 i2c@21a8000 { 533 #address-cells = < 0x01 >; 534 #size-cells = < 0x00 >; 535 compatible = "fsl,imx6sx-i2c\0fsl,imx21-i2c"; 536 reg = < 0x21a8000 0x4000 >; 537 interrupts = < 0x00 0x26 0x04 >; 538 clocks = < 0x04 0xa2 >; 539 clock-frequency = < 0x186a0 >; 540 pinctrl-names = "default"; 541 pinctrl-0 = < 0x45 >; 542 status = "okay"; 543 }; 544 545 serial@21e8000 { 546 compatible = "fsl,imx6q-uart\0fsl,imx21-uart"; 547 reg = < 0x21e8000 0x4000 >; 548 interrupts = < 0x00 0x1b 0x04 >; 549 clocks = < 0x04 0xa0 0x04 0xa1 >; 550 clock-names = "ipg\0per"; 551 dmas = < 0x17 0x1b 0x04 0x00 0x17 0x1c 0x04 0x00 >; 552 dma-names = "rx\0tx"; 553 status = "okay"; 554 pinctrl-names = "default"; 555 pinctrl-0 = < 0x50 >; 556 }; 557 558 serial@21ec000 { 559 compatible = "fsl,imx6q-uart\0fsl,imx21-uart"; 560 reg = < 0x21ec000 0x4000 >; 561 interrupts = < 0x00 0x1c 0x04 >; 562 clocks = < 0x04 0xa0 0x04 0xa1 >; 563 clock-names = "ipg\0per"; 564 dmas = < 0x17 0x1d 0x04 0x00 0x17 0x1e 0x04 0x00 >; 565 dma-names = "rx\0tx"; 566 status = "disabled"; 567 }; 568 569 serial@21f0000 { 570 compatible = "fsl,imx6q-uart\0fsl,imx21-uart"; 571 reg = < 0x21f0000 0x4000 >; 572 interrupts = < 0x00 0x1d 0x04 >; 573 clocks = < 0x04 0xa0 0x04 0xa1 >; 574 clock-names = "ipg\0per"; 575 dmas = < 0x17 0x1f 0x04 0x00 0x17 0x20 0x04 0x00 >; 576 dma-names = "rx\0tx"; 577 status = "disabled"; 578 }; 579 580 serial@21f4000 { 581 compatible = "fsl,imx6q-uart\0fsl,imx21-uart"; 582 reg = < 0x21f4000 0x4000 >; 583 interrupts = < 0x00 0x1e 0x04 >; 584 clocks = < 0x04 0xa0 0x04 0xa1 >; 585 clock-names = "ipg\0per"; 586 dmas = < 0x17 0x21 0x04 0x00 0x17 0x22 0x04 0x00 >; 587 dma-names = "rx\0tx"; 588 status = "disabled"; 589 }; 590 591 serial@22a0000 { 592 compatible = "fsl,imx6q-uart\0fsl,imx21-uart"; 593 reg = < 0x21f4000 0x4000 >; 594 interrupts = < 0x00 0x1e 0x04 >; 595 clocks = < 0x04 0xa0 0x04 0xa1 >; 596 clock-names = "ipg\0per"; 597 dmas = < 0x17 0x21 0x04 0x00 0x17 0x22 0x04 0x00 >; 598 dma-names = "rx\0tx"; 599 status = "disabled"; 600 }; 601 602 ethernet@2188000 { 603 compatible = "fsl,imx6sx-fec\0fsl,imx6q-fec"; 604 reg = < 0x2188000 0x4000 >; 605 interrupt-names = "int0\0pps"; 606 interrupts = < 0x00 0x76 0x04 0x00 0x77 0x04 >; 607 clocks = < 0x04 0xac 0x04 0xe1 0x04 0xe4 0x04 0x11 0x04 0xe4 >; 608 clock-names = "ipg\0ahb\0ptp\0enet_clk_ref\0enet_out"; 609 fsl,num-tx-queues = < 0x03 >; 610 fsl,num-rx-queues = < 0x03 >; 611 fsl,stop-mode = <0x05 0x10 0x03>; 612 pinctrl-names = "default"; 613 pinctrl-0 = < 0x32 >; 614 phy-mode = "rgmii"; 615 phy-handle = < ðphy1 >; 616 phy-supply = < 0x35 >; 617 fsl,magic-packet; 618 status = "okay"; 619 620 mdio { 621 #address-cells = <1>; 622 #size-cells = <0>; 623 624 ethphy1: ethernet-phy@4 { 625 reg = <4>; 626 }; 627 628 ethphy2: ethernet-phy@5 { 629 reg = <5>; 630 }; 631 }; 632 }; 633 634 ethernet@21b4000 { 635 compatible = "fsl,imx6sx-fec\0fsl,imx6q-fec"; 636 reg = < 0x021b4000 0x4000 >; 637 interrupt-names = "int0\0pps"; 638 interrupts = < 0x00 0x66 0x04 0x00 0x67 0x04 >; 639 clocks = < 0x04 0xac 0x04 0xe1 0x04 0xe4 0x04 0xe7 0x04 0xe4 >; 640 clock-names = "ipg\0ahb\0ptp\0enet_clk_ref\0enet_out"; 641 fsl,stop-mode = < 0x05 0x10 0x04>; 642 pinctrl-names = "default"; 643 pinctrl-0 = < 0x33 >; 644 phy-mode = "rgmii"; 645 phy-handle = < ðphy2 >; 646 phy-supply = < 0x35 >; 647 fsl,magic-packet; 648 status = "okay"; 649 }; 650 }; 651 }; 652}; 653