1 /* 2 * SPDX-License-Identifier: BSD-3-Clause 3 * SPDX-FileCopyrightText: Copyright TF-RMM Contributors. 4 */ 5 6 #ifndef ARCH_FEATURES_H 7 #define ARCH_FEATURES_H 8 9 #include <arch_helpers.h> 10 #include <stdbool.h> 11 is_armv8_4_ttst_present(void)12static inline bool is_armv8_4_ttst_present(void) 13 { 14 return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_ST_SHIFT) & 15 ID_AA64MMFR2_EL1_ST_MASK) == 1U; 16 } 17 18 /* 19 * Check if SVE is enabled 20 * ID_AA64PFR0_EL1.SVE, bits [35:32]: 21 * 0b0000 SVE architectural state and programmers' model are not implemented. 22 * 0b0001 SVE architectural state and programmers' model are implemented. 23 */ is_feat_sve_present(void)24static inline bool is_feat_sve_present(void) 25 { 26 return ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL1_SVE_SHIFT) & 27 ID_AA64PFR0_EL1_SVE_MASK) != 0UL; 28 } 29 30 /* 31 * Check if RNDR is available 32 */ is_feat_rng_present(void)33static inline bool is_feat_rng_present(void) 34 { 35 return ((read_ID_AA64ISAR0_EL1() >> ID_AA64ISAR0_RNDR_SHIFT) & 36 ID_AA64ISAR0_RNDR_MASK) != 0UL; 37 } 38 39 /* 40 * Check if FEAT_VMID16 is implemented 41 * ID_AA64MMFR1_EL1.VMIDBits, bits [7:4]: 42 * 0b0000 8 bits. 43 * 0b0010 16 bits. 44 * All other values are reserved. 45 */ is_feat_vmid16_present(void)46static inline bool is_feat_vmid16_present(void) 47 { 48 return (((read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_VMIDBits_SHIFT) & 49 ID_AA64MMFR1_EL1_VMIDBits_MASK) == 50 ID_AA64MMFR1_EL1_VMIDBits_16); 51 } 52 53 /* 54 * Check if FEAT_LPA2 is implemented. 55 * 4KB granule at stage 2 supports 52-bit input and output addresses: 56 * ID_AA64MMFR0_EL1.TGran4_2 bits [43:40]: 0b0011 57 */ is_feat_lpa2_4k_present(void)58static inline bool is_feat_lpa2_4k_present(void) 59 { 60 u_register_t aa64mmfr0 = read_id_aa64mmfr0_el1(); 61 62 return ((((aa64mmfr0 >> ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT) & 63 ID_AA64MMFR0_EL1_TGRAN4_2_MASK) == 64 ID_AA64MMFR0_EL1_TGRAN4_2_LPA2)); 65 } 66 67 unsigned int arch_feat_get_pa_width(void); 68 69 #endif /* ARCH_FEATURES_H */ 70