1 /* 2 * SPDX-License-Identifier: BSD-3-Clause 3 * SPDX-FileCopyrightText: Copyright TF-RMM Contributors. 4 * SPDX-FileCopyrightText: Copyright Arm Limited and Contributors. 5 */ 6 7 /* This file is derived from xlat_table_v2 library in TF-A project */ 8 9 #ifndef XLAT_DEFS_H 10 #define XLAT_DEFS_H 11 12 #include <arch.h> 13 #include <utils_def.h> 14 15 #define PAGE_SIZE_4KB (1UL << 12) 16 #define PAGE_SIZE_16KB (1UL << 14) 17 #define PAGE_SIZE_64KB (1UL << 16) 18 19 /* 20 * The ARMv8-A architecture allows translation granule sizes of 4KB, 16KB or 64KB. 21 * 22 * Only 4K granularities are allowed on this library. 23 */ 24 #define PAGE_SIZE (UL(1) << XLAT_GRANULARITY_SIZE_SHIFT) 25 #define PAGE_SIZE_MASK (PAGE_SIZE - UL(1)) 26 #define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == U(0)) 27 28 #define XLAT_ENTRY_SIZE_SHIFT UL(3) /* Each MMU table entry is 8 bytes */ 29 #define XLAT_ENTRY_SIZE (UL(1) << XLAT_ENTRY_SIZE_SHIFT) 30 31 /* Size of one complete table */ 32 #define XLAT_TABLE_SIZE_SHIFT XLAT_GRANULARITY_SIZE_SHIFT 33 #define XLAT_TABLE_SIZE (UL(1) << XLAT_TABLE_SIZE_SHIFT) 34 35 #define XLAT_TABLE_LEVEL_MAX UL(3) 36 37 /* Values for number of entries in each MMU translation table */ 38 #define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT) 39 #define XLAT_TABLE_ENTRIES (UL(1) << XLAT_TABLE_ENTRIES_SHIFT) 40 #define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - UL(1)) 41 42 /* Values to convert a memory address to an index into a translation table */ 43 #define L3_XLAT_ADDRESS_SHIFT XLAT_GRANULARITY_SIZE_SHIFT 44 #define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) 45 #define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) 46 #define L0_XLAT_ADDRESS_SHIFT (L1_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) 47 #define XLAT_ADDR_SHIFT(level) (XLAT_GRANULARITY_SIZE_SHIFT + \ 48 ((XLAT_TABLE_LEVEL_MAX - (level)) * XLAT_TABLE_ENTRIES_SHIFT)) 49 50 #define XLAT_BLOCK_SIZE(level) (UL(1) << XLAT_ADDR_SHIFT(level)) 51 /* Mask to get the bits used to index inside a block of a certain level */ 52 #define XLAT_BLOCK_MASK(level) (XLAT_BLOCK_SIZE(level) - UL(1)) 53 /* Mask to get the address bits common to a block of a certain table level*/ 54 #define XLAT_ADDR_MASK(level) (~XLAT_BLOCK_MASK(level)) 55 /* 56 * Extract from the given virtual address the index into the given lookup level. 57 * This macro assumes the system is using the 4KB translation granule. 58 */ 59 #define XLAT_TABLE_IDX(virtual_addr, level) \ 60 (((virtual_addr) >> XLAT_ADDR_SHIFT(level)) & ULL(0x1FF)) 61 62 /* Mask to get the PA given a L3 descriptor entry (4KB granularity) */ 63 #define XLAT_TTE_L3_PA_MASK ULL(0x0000FFFFFFFFF000) 64 65 /* 66 * In AArch64 state, the MMU may support 4KB, 16KB and 64KB page 67 * granularity. For 4KB granularity, a level 0 table descriptor doesn't support 68 * block translation. For 16KB, the same thing happens to levels 0 and 1. For 69 * 64KB, same for level 1. See section D4.3.1 of the ARMv8-A Architecture 70 * Reference Manual (DDI 0487A.k) for more information. 71 * 72 * The define below specifies the first table level that allows block 73 * descriptors. 74 */ 75 #if PAGE_SIZE == PAGE_SIZE_4KB 76 # define MIN_LVL_BLOCK_DESC U(1) 77 #elif (PAGE_SIZE == PAGE_SIZE_16KB) || (PAGE_SIZE == PAGE_SIZE_64KB) 78 # define MIN_LVL_BLOCK_DESC U(2) 79 #endif 80 81 #define XLAT_TABLE_LEVEL_MIN U(0) 82 83 /* Mask used to know if an address belongs to a high va region. */ 84 #define HIGH_REGION_MASK (ULL(0xFFF) << 52) 85 86 /* 87 * Define the architectural limits of the virtual address space in AArch64 88 * state. 89 * 90 * TCR.TxSZ is calculated as 64 minus the width of said address space. 91 * The value of TCR.TxSZ must be in the range 16 to 39 [1] or 48 [2], 92 * depending on Small Translation Table Support which means that 93 * the virtual address space width must be in the range 48 to 25 or 16 bits. 94 * 95 * [1] See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more 96 * information: 97 * Page 1730: 'Input address size', 'For all translation stages'. 98 * [2] See section 12.2.55 in the ARMv8-A Architecture Reference Manual 99 * (DDI 0487D.a) 100 */ 101 /* Maximum value of TCR_ELx.T(0,1)SZ is 39 */ 102 #define MIN_VIRT_ADDR_SPACE_SIZE (UL(1) << (UL(64) - TCR_TxSZ_MAX)) 103 104 /* Maximum value of TCR_ELx.T(0,1)SZ is 48 */ 105 #define MIN_VIRT_ADDR_SPACE_SIZE_TTST \ 106 (UL(1) << (UL(64) - TCR_TxSZ_MAX_TTST)) 107 #define MAX_VIRT_ADDR_SPACE_SIZE (UL(1) << (UL(64) - TCR_TxSZ_MIN)) 108 109 /* 110 * Here we calculate the initial lookup level from the value of the given 111 * virtual address space size. For a 4 KB page size, 112 * - level 0 supports virtual address spaces of widths 48 to 40 bits; 113 * - level 1 from 39 to 31; 114 * - level 2 from 30 to 22. 115 * - level 3 from 21 to 16. 116 * 117 * Small Translation Table (Armv8.4-TTST) support allows the starting level 118 * of the translation table from 3 for 4KB granularity. See section 12.2.55 in 119 * the ARMv8-A Architecture Reference Manual (DDI 0487D.a). In Armv8.3 and below 120 * wider or narrower address spaces are not supported. As a result, level 3 121 * cannot be used as initial lookup level with 4 KB granularity. See section 122 * D4.2.5 in the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more 123 * information. 124 * 125 * For example, for a 35-bit address space (i.e. virt_addr_space_size == 126 * 1 << 35), TCR.TxSZ will be programmed to (64 - 35) = 29. According to Table 127 * D4-11 in the ARM ARM, the initial lookup level for an address space like that 128 * is 1. 129 * 130 * Note that this macro assumes that the given virtual address space size is 131 * valid. 132 */ 133 #define GET_XLAT_TABLE_LEVEL_BASE(_virt_addr_space_sz) \ 134 (((_virt_addr_space_sz) > (ULL(1) << L0_XLAT_ADDRESS_SHIFT)) \ 135 ? 0U \ 136 : (((_virt_addr_space_sz) > (ULL(1) << L1_XLAT_ADDRESS_SHIFT)) \ 137 ? 1U \ 138 : (((_virt_addr_space_sz) > (ULL(1) << L2_XLAT_ADDRESS_SHIFT)) \ 139 ? 2U : 3U))) 140 141 #endif /* XLAT_DEFS_H */ 142