1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
4 */
5
6 #include <config.h>
7 #include <common.h>
8 #include <cpu_func.h>
9 #include <asm/global_data.h>
10 #include <linux/bitops.h>
11 #include <linux/compiler.h>
12 #include <linux/kernel.h>
13 #include <linux/log2.h>
14 #include <lmb.h>
15 #include <asm/arcregs.h>
16 #include <asm/arc-bcr.h>
17 #include <asm/cache.h>
18
19 /*
20 * [ NOTE 1 ]:
21 * Data cache (L1 D$ or SL$) entire invalidate operation or data cache disable
22 * operation may result in unexpected behavior and data loss even if we flush
23 * data cache right before invalidation. That may happens if we store any context
24 * on stack (like we store BLINK register on stack before function call).
25 * BLINK register is the register where return address is automatically saved
26 * when we do function call with instructions like 'bl'.
27 *
28 * There is the real example:
29 * We may hang in the next code as we store any BLINK register on stack in
30 * invalidate_dcache_all() function.
31 *
32 * void flush_dcache_all() {
33 * __dc_entire_op(OP_FLUSH);
34 * // Other code //
35 * }
36 *
37 * void invalidate_dcache_all() {
38 * __dc_entire_op(OP_INV);
39 * // Other code //
40 * }
41 *
42 * void foo(void) {
43 * flush_dcache_all();
44 * invalidate_dcache_all();
45 * }
46 *
47 * Now let's see what really happens during that code execution:
48 *
49 * foo()
50 * |->> call flush_dcache_all
51 * [return address is saved to BLINK register]
52 * [push BLINK] (save to stack) ![point 1]
53 * |->> call __dc_entire_op(OP_FLUSH)
54 * [return address is saved to BLINK register]
55 * [flush L1 D$]
56 * return [jump to BLINK]
57 * <<------
58 * [other flush_dcache_all code]
59 * [pop BLINK] (get from stack)
60 * return [jump to BLINK]
61 * <<------
62 * |->> call invalidate_dcache_all
63 * [return address is saved to BLINK register]
64 * [push BLINK] (save to stack) ![point 2]
65 * |->> call __dc_entire_op(OP_FLUSH)
66 * [return address is saved to BLINK register]
67 * [invalidate L1 D$] ![point 3]
68 * // Oops!!!
69 * // We lose return address from invalidate_dcache_all function:
70 * // we save it to stack and invalidate L1 D$ after that!
71 * return [jump to BLINK]
72 * <<------
73 * [other invalidate_dcache_all code]
74 * [pop BLINK] (get from stack)
75 * // we don't have this data in L1 dcache as we invalidated it in [point 3]
76 * // so we get it from next memory level (for example DDR memory)
77 * // but in the memory we have value which we save in [point 1], which
78 * // is return address from flush_dcache_all function (instead of
79 * // address from current invalidate_dcache_all function which we
80 * // saved in [point 2] !)
81 * return [jump to BLINK]
82 * <<------
83 * // As BLINK points to invalidate_dcache_all, we call it again and
84 * // loop forever.
85 *
86 * Fortunately we may fix that by using flush & invalidation of D$ with a single
87 * one instruction (instead of flush and invalidation instructions pair) and
88 * enabling force function inline with '__attribute__((always_inline))' gcc
89 * attribute to avoid any function call (and BLINK store) between cache flush
90 * and disable.
91 *
92 *
93 * [ NOTE 2 ]:
94 * As of today we only support the following cache configurations on ARC.
95 * Other configurations may exist in HW but we don't support it in SW.
96 * Configuration 1:
97 * ______________________
98 * | |
99 * | ARC CPU |
100 * |______________________|
101 * ___|___ ___|___
102 * | | | |
103 * | L1 I$ | | L1 D$ |
104 * |_______| |_______|
105 * on/off on/off
106 * ___|______________|____
107 * | |
108 * | main memory |
109 * |______________________|
110 *
111 * Configuration 2:
112 * ______________________
113 * | |
114 * | ARC CPU |
115 * |______________________|
116 * ___|___ ___|___
117 * | | | |
118 * | L1 I$ | | L1 D$ |
119 * |_______| |_______|
120 * on/off on/off
121 * ___|______________|____
122 * | |
123 * | L2 (SL$) |
124 * |______________________|
125 * always on (ARCv2, HS < 3.0)
126 * on/off (ARCv2, HS >= 3.0)
127 * ___|______________|____
128 * | |
129 * | main memory |
130 * |______________________|
131 *
132 * Configuration 3:
133 * ______________________
134 * | |
135 * | ARC CPU |
136 * |______________________|
137 * ___|___ ___|___
138 * | | | |
139 * | L1 I$ | | L1 D$ |
140 * |_______| |_______|
141 * on/off must be on
142 * ___|______________|____ _______
143 * | | | |
144 * | L2 (SL$) |-----| IOC |
145 * |______________________| |_______|
146 * always must be on on/off
147 * ___|______________|____
148 * | |
149 * | main memory |
150 * |______________________|
151 */
152
153 DECLARE_GLOBAL_DATA_PTR;
154
155 /* Bit values in IC_CTRL */
156 #define IC_CTRL_CACHE_DISABLE BIT(0)
157
158 /* Bit values in DC_CTRL */
159 #define DC_CTRL_CACHE_DISABLE BIT(0)
160 #define DC_CTRL_INV_MODE_FLUSH BIT(6)
161 #define DC_CTRL_FLUSH_STATUS BIT(8)
162
163 #define OP_INV BIT(0)
164 #define OP_FLUSH BIT(1)
165 #define OP_FLUSH_N_INV (OP_FLUSH | OP_INV)
166
167 /* Bit val in SLC_CONTROL */
168 #define SLC_CTRL_DIS 0x001
169 #define SLC_CTRL_IM 0x040
170 #define SLC_CTRL_BUSY 0x100
171 #define SLC_CTRL_RGN_OP_INV 0x200
172
173 #define CACHE_LINE_MASK (~(gd->arch.l1_line_sz - 1))
174
175 /*
176 * We don't want to use '__always_inline' macro here as it can be redefined
177 * to simple 'inline' in some cases which breaks stuff. See [ NOTE 1 ] for more
178 * details about the reasons we need to use always_inline functions.
179 */
180 #define inlined_cachefunc inline __attribute__((always_inline))
181
182 static inlined_cachefunc void __ic_entire_invalidate(void);
183 static inlined_cachefunc void __dc_entire_op(const int cacheop);
184 static inlined_cachefunc void __slc_entire_op(const int op);
185 static inlined_cachefunc bool ioc_enabled(void);
186
pae_exists(void)187 static inline bool pae_exists(void)
188 {
189 /* TODO: should we compare mmu version from BCR and from CONFIG? */
190 #if (CONFIG_ARC_MMU_VER >= 4)
191 union bcr_mmu_4 mmu4;
192
193 mmu4.word = read_aux_reg(ARC_AUX_MMU_BCR);
194
195 if (mmu4.fields.pae)
196 return true;
197 #endif /* (CONFIG_ARC_MMU_VER >= 4) */
198
199 return false;
200 }
201
icache_exists(void)202 static inlined_cachefunc bool icache_exists(void)
203 {
204 union bcr_di_cache ibcr;
205
206 ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
207 return !!ibcr.fields.ver;
208 }
209
icache_enabled(void)210 static inlined_cachefunc bool icache_enabled(void)
211 {
212 if (!icache_exists())
213 return false;
214
215 return !(read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE);
216 }
217
dcache_exists(void)218 static inlined_cachefunc bool dcache_exists(void)
219 {
220 union bcr_di_cache dbcr;
221
222 dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
223 return !!dbcr.fields.ver;
224 }
225
dcache_enabled(void)226 static inlined_cachefunc bool dcache_enabled(void)
227 {
228 if (!dcache_exists())
229 return false;
230
231 return !(read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE);
232 }
233
slc_exists(void)234 static inlined_cachefunc bool slc_exists(void)
235 {
236 if (is_isa_arcv2()) {
237 union bcr_generic sbcr;
238
239 sbcr.word = read_aux_reg(ARC_BCR_SLC);
240 return !!sbcr.fields.ver;
241 }
242
243 return false;
244 }
245
246 enum slc_dis_status {
247 ST_SLC_MISSING = 0,
248 ST_SLC_NO_DISABLE_CTRL,
249 ST_SLC_DISABLE_CTRL
250 };
251
252 /*
253 * ARCv1 -> ST_SLC_MISSING
254 * ARCv2 && SLC absent -> ST_SLC_MISSING
255 * ARCv2 && SLC exists && SLC version <= 2 -> ST_SLC_NO_DISABLE_CTRL
256 * ARCv2 && SLC exists && SLC version > 2 -> ST_SLC_DISABLE_CTRL
257 */
slc_disable_supported(void)258 static inlined_cachefunc enum slc_dis_status slc_disable_supported(void)
259 {
260 if (is_isa_arcv2()) {
261 union bcr_generic sbcr;
262
263 sbcr.word = read_aux_reg(ARC_BCR_SLC);
264 if (sbcr.fields.ver == 0)
265 return ST_SLC_MISSING;
266 else if (sbcr.fields.ver <= 2)
267 return ST_SLC_NO_DISABLE_CTRL;
268 else
269 return ST_SLC_DISABLE_CTRL;
270 }
271
272 return ST_SLC_MISSING;
273 }
274
__slc_enabled(void)275 static inlined_cachefunc bool __slc_enabled(void)
276 {
277 return !(read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_DIS);
278 }
279
__slc_enable(void)280 static inlined_cachefunc void __slc_enable(void)
281 {
282 unsigned int ctrl;
283
284 ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
285 ctrl &= ~SLC_CTRL_DIS;
286 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
287 }
288
__slc_disable(void)289 static inlined_cachefunc void __slc_disable(void)
290 {
291 unsigned int ctrl;
292
293 ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
294 ctrl |= SLC_CTRL_DIS;
295 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
296 }
297
slc_enabled(void)298 static inlined_cachefunc bool slc_enabled(void)
299 {
300 enum slc_dis_status slc_status = slc_disable_supported();
301
302 if (slc_status == ST_SLC_MISSING)
303 return false;
304 else if (slc_status == ST_SLC_NO_DISABLE_CTRL)
305 return true;
306 else
307 return __slc_enabled();
308 }
309
slc_data_bypass(void)310 static inlined_cachefunc bool slc_data_bypass(void)
311 {
312 /*
313 * If L1 data cache is disabled SL$ is bypassed and all load/store
314 * requests are sent directly to main memory.
315 */
316 return !dcache_enabled();
317 }
318
slc_enable(void)319 void slc_enable(void)
320 {
321 if (slc_disable_supported() != ST_SLC_DISABLE_CTRL)
322 return;
323
324 if (__slc_enabled())
325 return;
326
327 __slc_enable();
328 }
329
330 /* TODO: warn if we are not able to disable SLC */
slc_disable(void)331 void slc_disable(void)
332 {
333 if (slc_disable_supported() != ST_SLC_DISABLE_CTRL)
334 return;
335
336 /* we don't support SLC disabling if we use IOC */
337 if (ioc_enabled())
338 return;
339
340 if (!__slc_enabled())
341 return;
342
343 /*
344 * We need to flush L1D$ to guarantee that we won't have any
345 * writeback operations during SLC disabling.
346 */
347 __dc_entire_op(OP_FLUSH);
348 __slc_entire_op(OP_FLUSH_N_INV);
349 __slc_disable();
350 }
351
ioc_exists(void)352 static inlined_cachefunc bool ioc_exists(void)
353 {
354 if (is_isa_arcv2()) {
355 union bcr_clust_cfg cbcr;
356
357 cbcr.word = read_aux_reg(ARC_BCR_CLUSTER);
358 return cbcr.fields.c;
359 }
360
361 return false;
362 }
363
ioc_enabled(void)364 static inlined_cachefunc bool ioc_enabled(void)
365 {
366 /*
367 * We check only CONFIG option instead of IOC HW state check as IOC
368 * must be disabled by default.
369 */
370 if (is_ioc_enabled())
371 return ioc_exists();
372
373 return false;
374 }
375
__slc_entire_op(const int op)376 static inlined_cachefunc void __slc_entire_op(const int op)
377 {
378 unsigned int ctrl;
379
380 if (!slc_enabled())
381 return;
382
383 ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
384
385 if (!(op & OP_FLUSH)) /* i.e. OP_INV */
386 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
387 else
388 ctrl |= SLC_CTRL_IM;
389
390 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
391
392 if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */
393 write_aux_reg(ARC_AUX_SLC_INVALIDATE, 0x1);
394 else
395 write_aux_reg(ARC_AUX_SLC_FLUSH, 0x1);
396
397 /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
398 read_aux_reg(ARC_AUX_SLC_CTRL);
399
400 /* Important to wait for flush to complete */
401 while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY);
402 }
403
slc_upper_region_init(void)404 static void slc_upper_region_init(void)
405 {
406 /*
407 * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist
408 * only if PAE exists in current HW. So we had to check pae_exist
409 * before using them.
410 */
411 if (!pae_exists())
412 return;
413
414 /*
415 * ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1 are always == 0
416 * as we don't use PAE40.
417 */
418 write_aux_reg(ARC_AUX_SLC_RGN_END1, 0);
419 write_aux_reg(ARC_AUX_SLC_RGN_START1, 0);
420 }
421
__slc_rgn_op(unsigned long paddr,unsigned long sz,const int op)422 static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op)
423 {
424 #ifdef CONFIG_ISA_ARCV2
425
426 unsigned int ctrl;
427 unsigned long end;
428
429 if (!slc_enabled())
430 return;
431
432 /*
433 * The Region Flush operation is specified by CTRL.RGN_OP[11..9]
434 * - b'000 (default) is Flush,
435 * - b'001 is Invalidate if CTRL.IM == 0
436 * - b'001 is Flush-n-Invalidate if CTRL.IM == 1
437 */
438 ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
439
440 /* Don't rely on default value of IM bit */
441 if (!(op & OP_FLUSH)) /* i.e. OP_INV */
442 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
443 else
444 ctrl |= SLC_CTRL_IM;
445
446 if (op & OP_INV)
447 ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */
448 else
449 ctrl &= ~SLC_CTRL_RGN_OP_INV;
450
451 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
452
453 /*
454 * Lower bits are ignored, no need to clip
455 * END needs to be setup before START (latter triggers the operation)
456 * END can't be same as START, so add (l2_line_sz - 1) to sz
457 */
458 end = paddr + sz + gd->arch.slc_line_sz - 1;
459
460 /*
461 * Upper addresses (ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1)
462 * are always == 0 as we don't use PAE40, so we only setup lower ones
463 * (ARC_AUX_SLC_RGN_END and ARC_AUX_SLC_RGN_START)
464 */
465 write_aux_reg(ARC_AUX_SLC_RGN_END, end);
466 write_aux_reg(ARC_AUX_SLC_RGN_START, paddr);
467
468 /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
469 read_aux_reg(ARC_AUX_SLC_CTRL);
470
471 while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY);
472
473 #endif /* CONFIG_ISA_ARCV2 */
474 }
475
arc_ioc_setup(void)476 static void arc_ioc_setup(void)
477 {
478 /* IOC Aperture start is equal to DDR start */
479 unsigned int ap_base = CONFIG_SYS_SDRAM_BASE;
480 /* IOC Aperture size is equal to DDR size */
481 long ap_size = CONFIG_SYS_SDRAM_SIZE;
482
483 /* Unsupported configuration. See [ NOTE 2 ] for more details. */
484 if (!slc_exists())
485 panic("Try to enable IOC but SLC is not present");
486
487 if (!slc_enabled())
488 panic("Try to enable IOC but SLC is disabled");
489
490 /* Unsupported configuration. See [ NOTE 2 ] for more details. */
491 if (!dcache_enabled())
492 panic("Try to enable IOC but L1 D$ is disabled");
493
494 if (!is_power_of_2(ap_size) || ap_size < 4096)
495 panic("IOC Aperture size must be power of 2 and bigger 4Kib");
496
497 /* IOC Aperture start must be aligned to the size of the aperture */
498 if (ap_base % ap_size != 0)
499 panic("IOC Aperture start must be aligned to the size of the aperture");
500
501 flush_n_invalidate_dcache_all();
502
503 /*
504 * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB,
505 * so setting 0x11 implies 512M, 0x12 implies 1G...
506 */
507 write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE,
508 order_base_2(ap_size / 1024) - 2);
509
510 write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12);
511 write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1);
512 write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1);
513 }
514
read_decode_cache_bcr_arcv2(void)515 static void read_decode_cache_bcr_arcv2(void)
516 {
517 #ifdef CONFIG_ISA_ARCV2
518
519 union bcr_slc_cfg slc_cfg;
520
521 if (slc_exists()) {
522 slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG);
523 gd->arch.slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64;
524
525 /*
526 * We don't support configuration where L1 I$ or L1 D$ is
527 * absent but SL$ exists. See [ NOTE 2 ] for more details.
528 */
529 if (!icache_exists() || !dcache_exists())
530 panic("Unsupported cache configuration: SLC exists but one of L1 caches is absent");
531 }
532
533 #endif /* CONFIG_ISA_ARCV2 */
534 }
535
read_decode_cache_bcr(void)536 void read_decode_cache_bcr(void)
537 {
538 int dc_line_sz = 0, ic_line_sz = 0;
539 union bcr_di_cache ibcr, dbcr;
540
541 /*
542 * We don't care much about I$ line length really as there're
543 * no per-line ops on I$ instead we only do full invalidation of it
544 * on occasion of relocation and right before jumping to the OS.
545 * Still we check insane config with zero-encoded line length in
546 * presense of version field in I$ BCR. Just in case.
547 */
548 ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
549 if (ibcr.fields.ver) {
550 ic_line_sz = 8 << ibcr.fields.line_len;
551 if (!ic_line_sz)
552 panic("Instruction exists but line length is 0\n");
553 }
554
555 dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
556 if (dbcr.fields.ver) {
557 gd->arch.l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len;
558 if (!dc_line_sz)
559 panic("Data cache exists but line length is 0\n");
560 }
561 }
562
cache_init(void)563 void cache_init(void)
564 {
565 read_decode_cache_bcr();
566
567 if (is_isa_arcv2())
568 read_decode_cache_bcr_arcv2();
569
570 if (is_isa_arcv2() && ioc_enabled())
571 arc_ioc_setup();
572
573 if (is_isa_arcv2() && slc_exists())
574 slc_upper_region_init();
575 }
576
icache_status(void)577 int icache_status(void)
578 {
579 return icache_enabled();
580 }
581
icache_enable(void)582 void icache_enable(void)
583 {
584 if (icache_exists())
585 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
586 ~IC_CTRL_CACHE_DISABLE);
587 }
588
icache_disable(void)589 void icache_disable(void)
590 {
591 if (!icache_exists())
592 return;
593
594 __ic_entire_invalidate();
595
596 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
597 IC_CTRL_CACHE_DISABLE);
598 }
599
600 /* IC supports only invalidation */
__ic_entire_invalidate(void)601 static inlined_cachefunc void __ic_entire_invalidate(void)
602 {
603 if (!icache_enabled())
604 return;
605
606 /* Any write to IC_IVIC register triggers invalidation of entire I$ */
607 write_aux_reg(ARC_AUX_IC_IVIC, 1);
608 /*
609 * As per ARC HS databook (see chapter 5.3.3.2)
610 * it is required to add 3 NOPs after each write to IC_IVIC.
611 */
612 __builtin_arc_nop();
613 __builtin_arc_nop();
614 __builtin_arc_nop();
615 read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */
616 }
617
invalidate_icache_all(void)618 void invalidate_icache_all(void)
619 {
620 __ic_entire_invalidate();
621
622 /*
623 * If SL$ is bypassed for data it is used only for instructions,
624 * so we need to invalidate it too.
625 */
626 if (is_isa_arcv2() && slc_data_bypass())
627 __slc_entire_op(OP_INV);
628 }
629
dcache_status(void)630 int dcache_status(void)
631 {
632 return dcache_enabled();
633 }
634
dcache_enable(void)635 void dcache_enable(void)
636 {
637 if (!dcache_exists())
638 return;
639
640 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
641 ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
642 }
643
dcache_disable(void)644 void dcache_disable(void)
645 {
646 if (!dcache_exists())
647 return;
648
649 __dc_entire_op(OP_FLUSH_N_INV);
650
651 /*
652 * As SLC will be bypassed for data after L1 D$ disable we need to
653 * flush it first before L1 D$ disable. Also we invalidate SLC to
654 * avoid any inconsistent data problems after enabling L1 D$ again with
655 * dcache_enable function.
656 */
657 if (is_isa_arcv2())
658 __slc_entire_op(OP_FLUSH_N_INV);
659
660 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
661 DC_CTRL_CACHE_DISABLE);
662 }
663
664 /* Common Helper for Line Operations on D-cache */
__dcache_line_loop(unsigned long paddr,unsigned long sz,const int cacheop)665 static inline void __dcache_line_loop(unsigned long paddr, unsigned long sz,
666 const int cacheop)
667 {
668 unsigned int aux_cmd;
669 int num_lines;
670
671 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
672 aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL;
673
674 sz += paddr & ~CACHE_LINE_MASK;
675 paddr &= CACHE_LINE_MASK;
676
677 num_lines = DIV_ROUND_UP(sz, gd->arch.l1_line_sz);
678
679 while (num_lines-- > 0) {
680 #if (CONFIG_ARC_MMU_VER == 3)
681 write_aux_reg(ARC_AUX_DC_PTAG, paddr);
682 #endif
683 write_aux_reg(aux_cmd, paddr);
684 paddr += gd->arch.l1_line_sz;
685 }
686 }
687
__before_dc_op(const int op)688 static inlined_cachefunc void __before_dc_op(const int op)
689 {
690 unsigned int ctrl;
691
692 ctrl = read_aux_reg(ARC_AUX_DC_CTRL);
693
694 /* IM bit implies flush-n-inv, instead of vanilla inv */
695 if (op == OP_INV)
696 ctrl &= ~DC_CTRL_INV_MODE_FLUSH;
697 else
698 ctrl |= DC_CTRL_INV_MODE_FLUSH;
699
700 write_aux_reg(ARC_AUX_DC_CTRL, ctrl);
701 }
702
__after_dc_op(const int op)703 static inlined_cachefunc void __after_dc_op(const int op)
704 {
705 if (op & OP_FLUSH) /* flush / flush-n-inv both wait */
706 while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
707 }
708
__dc_entire_op(const int cacheop)709 static inlined_cachefunc void __dc_entire_op(const int cacheop)
710 {
711 int aux;
712
713 if (!dcache_enabled())
714 return;
715
716 __before_dc_op(cacheop);
717
718 if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
719 aux = ARC_AUX_DC_IVDC;
720 else
721 aux = ARC_AUX_DC_FLSH;
722
723 write_aux_reg(aux, 0x1);
724
725 __after_dc_op(cacheop);
726 }
727
__dc_line_op(unsigned long paddr,unsigned long sz,const int cacheop)728 static inline void __dc_line_op(unsigned long paddr, unsigned long sz,
729 const int cacheop)
730 {
731 if (!dcache_enabled())
732 return;
733
734 __before_dc_op(cacheop);
735 __dcache_line_loop(paddr, sz, cacheop);
736 __after_dc_op(cacheop);
737 }
738
invalidate_dcache_range(unsigned long start,unsigned long end)739 void invalidate_dcache_range(unsigned long start, unsigned long end)
740 {
741 if (start >= end)
742 return;
743
744 /*
745 * ARCv1 -> call __dc_line_op
746 * ARCv2 && L1 D$ disabled -> nothing
747 * ARCv2 && L1 D$ enabled && IOC enabled -> nothing
748 * ARCv2 && L1 D$ enabled && no IOC -> call __dc_line_op; call __slc_rgn_op
749 */
750 if (!is_isa_arcv2() || !ioc_enabled())
751 __dc_line_op(start, end - start, OP_INV);
752
753 if (is_isa_arcv2() && !ioc_enabled() && !slc_data_bypass())
754 __slc_rgn_op(start, end - start, OP_INV);
755 }
756
flush_dcache_range(unsigned long start,unsigned long end)757 void flush_dcache_range(unsigned long start, unsigned long end)
758 {
759 if (start >= end)
760 return;
761
762 /*
763 * ARCv1 -> call __dc_line_op
764 * ARCv2 && L1 D$ disabled -> nothing
765 * ARCv2 && L1 D$ enabled && IOC enabled -> nothing
766 * ARCv2 && L1 D$ enabled && no IOC -> call __dc_line_op; call __slc_rgn_op
767 */
768 if (!is_isa_arcv2() || !ioc_enabled())
769 __dc_line_op(start, end - start, OP_FLUSH);
770
771 if (is_isa_arcv2() && !ioc_enabled() && !slc_data_bypass())
772 __slc_rgn_op(start, end - start, OP_FLUSH);
773 }
774
flush_cache(unsigned long start,unsigned long size)775 void flush_cache(unsigned long start, unsigned long size)
776 {
777 flush_dcache_range(start, start + size);
778 }
779
780 /*
781 * As invalidate_dcache_all() is not used in generic U-Boot code and as we
782 * don't need it in arch/arc code alone (invalidate without flush) we implement
783 * flush_n_invalidate_dcache_all (flush and invalidate in 1 operation) because
784 * it's much safer. See [ NOTE 1 ] for more details.
785 */
flush_n_invalidate_dcache_all(void)786 void flush_n_invalidate_dcache_all(void)
787 {
788 __dc_entire_op(OP_FLUSH_N_INV);
789
790 if (is_isa_arcv2() && !slc_data_bypass())
791 __slc_entire_op(OP_FLUSH_N_INV);
792 }
793
flush_dcache_all(void)794 void flush_dcache_all(void)
795 {
796 __dc_entire_op(OP_FLUSH);
797
798 if (is_isa_arcv2() && !slc_data_bypass())
799 __slc_entire_op(OP_FLUSH);
800 }
801
802 /*
803 * This is function to cleanup all caches (and therefore sync I/D caches) which
804 * can be used for cleanup before linux launch or to sync caches during
805 * relocation.
806 */
sync_n_cleanup_cache_all(void)807 void sync_n_cleanup_cache_all(void)
808 {
809 __dc_entire_op(OP_FLUSH_N_INV);
810
811 /*
812 * If SL$ is bypassed for data it is used only for instructions,
813 * and we shouldn't flush it. So invalidate it instead of flush_n_inv.
814 */
815 if (is_isa_arcv2()) {
816 if (slc_data_bypass())
817 __slc_entire_op(OP_INV);
818 else
819 __slc_entire_op(OP_FLUSH_N_INV);
820 }
821
822 __ic_entire_invalidate();
823 }
824
get_sp(void)825 static ulong get_sp(void)
826 {
827 ulong ret;
828
829 asm("mov %0, sp" : "=r"(ret) : );
830 return ret;
831 }
832
arch_lmb_reserve(struct lmb * lmb)833 void arch_lmb_reserve(struct lmb *lmb)
834 {
835 arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
836 }
837