1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2004 Texas Insturments
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * (C) Copyright 2002
10 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
11 */
12
13 /*
14 * CPU specific code
15 */
16
17 #include <common.h>
18 #include <command.h>
19 #include <cpu_func.h>
20 #include <irq_func.h>
21 #include <asm/cache.h>
22 #include <asm/system.h>
23
24 static void cache_flush(void);
25
cleanup_before_linux(void)26 int cleanup_before_linux (void)
27 {
28 /*
29 * this function is called just before we call linux
30 * it prepares the processor for linux
31 *
32 * we turn off caches etc ...
33 */
34
35 disable_interrupts();
36
37 /* turn off I/D-cache */
38 icache_disable();
39 dcache_disable();
40 /* flush I/D-cache */
41 cache_flush();
42
43 return 0;
44 }
45
cache_flush(void)46 static void cache_flush(void)
47 {
48 unsigned long i = 0;
49 /* clean entire data cache */
50 asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
51 /* invalidate both caches and flush btb */
52 asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
53 /* mem barrier to sync things */
54 asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
55 }
56
57 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
invalidate_dcache_all(void)58 void invalidate_dcache_all(void)
59 {
60 asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
61 }
62
flush_dcache_all(void)63 void flush_dcache_all(void)
64 {
65 asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
66 asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
67 }
68
invalidate_dcache_range(unsigned long start,unsigned long stop)69 void invalidate_dcache_range(unsigned long start, unsigned long stop)
70 {
71 if (!check_cache_range(start, stop))
72 return;
73
74 while (start < stop) {
75 asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
76 start += CONFIG_SYS_CACHELINE_SIZE;
77 }
78 }
79
flush_dcache_range(unsigned long start,unsigned long stop)80 void flush_dcache_range(unsigned long start, unsigned long stop)
81 {
82 if (!check_cache_range(start, stop))
83 return;
84
85 while (start < stop) {
86 asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
87 start += CONFIG_SYS_CACHELINE_SIZE;
88 }
89
90 asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
91 }
92
93 #else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
invalidate_dcache_all(void)94 void invalidate_dcache_all(void)
95 {
96 }
97
flush_dcache_all(void)98 void flush_dcache_all(void)
99 {
100 }
101 #endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
102
103 #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
enable_caches(void)104 void enable_caches(void)
105 {
106 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
107 icache_enable();
108 #endif
109 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
110 dcache_enable();
111 #endif
112 }
113 #endif
114