1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Freescale i.MX28 RAM init
4 *
5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6 * on behalf of DENX Software Engineering GmbH
7 */
8
9 #include <common.h>
10 #include <config.h>
11 #include <init.h>
12 #include <log.h>
13 #include <asm/io.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/sys_proto.h>
16 #include <linux/compiler.h>
17
18 #include "mxs_init.h"
19
20 __weak uint32_t mxs_dram_vals[] = {
21 /*
22 * i.MX28 DDR2 at 200MHz
23 */
24 #if defined(CONFIG_MX28)
25 0x00000000, 0x00000000, 0x00000000, 0x00000000,
26 0x00000000, 0x00000000, 0x00000000, 0x00000000,
27 0x00000000, 0x00000000, 0x00000000, 0x00000000,
28 0x00000000, 0x00000000, 0x00000000, 0x00000000,
29 0x00000000, 0x00000100, 0x00000000, 0x00000000,
30 0x00000000, 0x00000000, 0x00000000, 0x00000000,
31 0x00000000, 0x00000000, 0x00010101, 0x01010101,
32 0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101,
33 0x00000100, 0x00000100, 0x00000000, 0x00000002,
34 0x01010000, 0x07080403, 0x06005003, 0x0a0000c8,
35 0x02009c40, 0x0002030c, 0x0036a609, 0x031a0612,
36 0x02030202, 0x00c8001c, 0x00000000, 0x00000000,
37 0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
38 0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
39 0x00000003, 0x00000000, 0x00000000, 0x00000000,
40 0x00000000, 0x00000000, 0x00000000, 0x00000000,
41 0x00000000, 0x00000000, 0x00000612, 0x01000F02,
42 0x06120612, 0x00000200, 0x00020007, 0xf4004a27,
43 0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07000300,
44 0x07000300, 0x07400300, 0x07400300, 0x00000005,
45 0x00000000, 0x00000000, 0x01000000, 0x01020408,
46 0x08040201, 0x000f1133, 0x00000000, 0x00001f04,
47 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
48 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000,
49 0x00000000, 0x00000000, 0x00000000, 0x00000000,
50 0x00000000, 0x00000000, 0x00000000, 0x00000000,
51 0x00000000, 0x00000000, 0x00000000, 0x00000000,
52 0x00000000, 0x00000000, 0x00000000, 0x00000000,
53 0x00000000, 0x00000000, 0x00000000, 0x00000000,
54 0x00000000, 0x00000000, 0x00000000, 0x00000000,
55 0x00000000, 0x00000000, 0x00000000, 0x00000000,
56 0x00000000, 0x00000000, 0x00000000, 0x00000000,
57 0x00000000, 0x00000000, 0x00000000, 0x00000000,
58 0x00000000, 0x00000000, 0x00000000, 0x00000000,
59 0x00000000, 0x00000000, 0x00000000, 0x00000000,
60 0x00000000, 0x00000000, 0x00000000, 0x00000000,
61 0x00000000, 0x00000000, 0x00000000, 0x00000000,
62 0x00000000, 0x00000000, 0x00000000, 0x00000000,
63 0x00000000, 0x00000000, 0x00000000, 0x00000000,
64 0x00000000, 0x00000000, 0x00000000, 0x00000000,
65 0x00000000, 0x00000000, 0x00010000, 0x00030404,
66 0x00000003, 0x00000000, 0x00000000, 0x00000000,
67 0x00000000, 0x00000000, 0x00000000, 0x01010000,
68 0x01000000, 0x03030000, 0x00010303, 0x01020202,
69 0x00000000, 0x02040303, 0x21002103, 0x00061200,
70 0x06120612, 0x04420442, 0x04420442, 0x00040004,
71 0x00040004, 0x00000000, 0x00000000, 0x00000000,
72 0x00000000, 0xffffffff
73
74 /*
75 * i.MX23 DDR at 133MHz
76 */
77 #elif defined(CONFIG_MX23)
78 0x01010001, 0x00010100, 0x01000101, 0x00000001,
79 0x00000101, 0x00000000, 0x00010000, 0x01000001,
80 0x00000000, 0x00000001, 0x07000200, 0x00070202,
81 0x02020000, 0x04040a01, 0x00000201, 0x02040000,
82 0x02000000, 0x19000f08, 0x0d0d0000, 0x02021313,
83 0x02061521, 0x0000000a, 0x00080008, 0x00200020,
84 0x00200020, 0x00200020, 0x000003f7, 0x00000000,
85 0x00000000, 0x00000020, 0x00000020, 0x00c80000,
86 0x000a23cd, 0x000000c8, 0x00006665, 0x00000000,
87 0x00000101, 0x00040001, 0x00000000, 0x00000000,
88 0x00010000
89 #else
90 #error Unsupported memory initialization
91 #endif
92 };
93
mxs_adjust_memory_params(uint32_t * dram_vals)94 __weak void mxs_adjust_memory_params(uint32_t *dram_vals)
95 {
96 debug("SPL: Using default SDRAM parameters\n");
97 }
98
99 #ifdef CONFIG_MX28
initialize_dram_values(void)100 static void initialize_dram_values(void)
101 {
102 int i;
103
104 debug("SPL: Setting mx28 board specific SDRAM parameters\n");
105 mxs_adjust_memory_params(mxs_dram_vals);
106
107 debug("SPL: Applying SDRAM parameters\n");
108 for (i = 0; i < ARRAY_SIZE(mxs_dram_vals); i++)
109 writel(mxs_dram_vals[i], MXS_DRAM_BASE + (4 * i));
110 }
111 #else
initialize_dram_values(void)112 static void initialize_dram_values(void)
113 {
114 int i;
115
116 debug("SPL: Setting mx23 board specific SDRAM parameters\n");
117 mxs_adjust_memory_params(mxs_dram_vals);
118
119 /*
120 * HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as
121 * per FSL bootlets code.
122 *
123 * mx23 Reference Manual marks HW_DRAM_CTL27 and HW_DRAM_CTL28 as
124 * "reserved".
125 * HW_DRAM_CTL8 is setup as the last element.
126 * So skip the initialization of these HW_DRAM_CTL registers.
127 */
128 debug("SPL: Applying SDRAM parameters\n");
129 for (i = 0; i < ARRAY_SIZE(mxs_dram_vals); i++) {
130 if (i == 8 || i == 27 || i == 28 || i == 35)
131 continue;
132 writel(mxs_dram_vals[i], MXS_DRAM_BASE + (4 * i));
133 }
134
135 /*
136 * Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last
137 * element to be set
138 */
139 writel((1 << 24), MXS_DRAM_BASE + (4 * 8));
140 }
141 #endif
142
mxs_mem_init_clock(void)143 static void mxs_mem_init_clock(void)
144 {
145 struct mxs_clkctrl_regs *clkctrl_regs =
146 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
147 #if defined(CONFIG_MX23)
148 /* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */
149 const unsigned char divider = 33;
150 #elif defined(CONFIG_MX28)
151 /* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */
152 const unsigned char divider = 21;
153 #endif
154
155 debug("SPL: Initialising FRAC0\n");
156
157 /* Gate EMI clock */
158 writeb(CLKCTRL_FRAC_CLKGATE,
159 &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]);
160
161 /* Set fractional divider for ref_emi */
162 writeb(CLKCTRL_FRAC_CLKGATE | (divider & CLKCTRL_FRAC_FRAC_MASK),
163 &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);
164
165 /* Ungate EMI clock */
166 writeb(CLKCTRL_FRAC_CLKGATE,
167 &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]);
168
169 early_delay(11000);
170
171 /* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */
172 writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) |
173 (1 << CLKCTRL_EMI_DIV_XTAL_OFFSET),
174 &clkctrl_regs->hw_clkctrl_emi);
175
176 /* Unbypass EMI */
177 writel(CLKCTRL_CLKSEQ_BYPASS_EMI,
178 &clkctrl_regs->hw_clkctrl_clkseq_clr);
179
180 early_delay(10000);
181 debug("SPL: FRAC0 Initialised\n");
182 }
183
mxs_mem_setup_cpu_and_hbus(void)184 static void mxs_mem_setup_cpu_and_hbus(void)
185 {
186 struct mxs_clkctrl_regs *clkctrl_regs =
187 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
188
189 debug("SPL: Setting CPU and HBUS clock frequencies\n");
190
191 /* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz
192 * and ungate CPU clock */
193 writeb(19 & CLKCTRL_FRAC_FRAC_MASK,
194 (uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
195
196 /* Set CPU bypass */
197 writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
198 &clkctrl_regs->hw_clkctrl_clkseq_set);
199
200 /* HBUS = 151MHz */
201 writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set);
202 writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK,
203 &clkctrl_regs->hw_clkctrl_hbus_clr);
204
205 early_delay(10000);
206
207 /* CPU clock divider = 1 */
208 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu,
209 CLKCTRL_CPU_DIV_CPU_MASK, 1);
210
211 /* Disable CPU bypass */
212 writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
213 &clkctrl_regs->hw_clkctrl_clkseq_clr);
214
215 early_delay(15000);
216 }
217
mxs_mem_setup_vdda(void)218 static void mxs_mem_setup_vdda(void)
219 {
220 struct mxs_power_regs *power_regs =
221 (struct mxs_power_regs *)MXS_POWER_BASE;
222
223 debug("SPL: Configuring VDDA\n");
224
225 writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
226 (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
227 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW,
228 &power_regs->hw_power_vddactrl);
229 }
230
mxs_mem_get_size(void)231 uint32_t mxs_mem_get_size(void)
232 {
233 uint32_t sz, da;
234 uint32_t *vt = (uint32_t *)0x20;
235 /* The following is "subs pc, r14, #4", used as return from DABT. */
236 const uint32_t data_abort_memdetect_handler = 0xe25ef004;
237
238 /* Replace the DABT handler. */
239 da = vt[4];
240 vt[4] = data_abort_memdetect_handler;
241
242 sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
243
244 /* Restore the old DABT handler. */
245 vt[4] = da;
246
247 return sz;
248 }
249
250 #ifdef CONFIG_MX23
mx23_mem_setup_vddmem(void)251 static void mx23_mem_setup_vddmem(void)
252 {
253 struct mxs_power_regs *power_regs =
254 (struct mxs_power_regs *)MXS_POWER_BASE;
255
256 debug("SPL: Setting mx23 VDDMEM\n");
257
258 /* We must wait before and after disabling the current limiter! */
259 early_delay(10000);
260
261 clrbits_le32(&power_regs->hw_power_vddmemctrl,
262 POWER_VDDMEMCTRL_ENABLE_ILIMIT);
263
264 early_delay(10000);
265
266 }
267
mx23_mem_init(void)268 static void mx23_mem_init(void)
269 {
270 debug("SPL: Initialising mx23 SDRAM Controller\n");
271
272 /*
273 * Reset/ungate the EMI block. This is essential, otherwise the system
274 * suffers from memory instability. This thing is mx23 specific and is
275 * no longer present on mx28.
276 */
277 mxs_reset_block((struct mxs_register_32 *)MXS_EMI_BASE);
278
279 mx23_mem_setup_vddmem();
280
281 /*
282 * Configure the DRAM registers
283 */
284
285 /* Clear START and SREFRESH bit from DRAM_CTL8 */
286 clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8));
287
288 initialize_dram_values();
289
290 /* Set START bit in DRAM_CTL8 */
291 setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16);
292
293 clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);
294
295 /* Wait for EMI_STAT bit DRAM_HALTED */
296 for (;;) {
297 if (!(readl(MXS_EMI_BASE + 0x10) & (1 << 1)))
298 break;
299 early_delay(1000);
300 }
301
302 /* Adjust EMI port priority. */
303 clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);
304 early_delay(20000);
305
306 setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
307 setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
308 }
309 #endif
310
311 #ifdef CONFIG_MX28
mx28_mem_init(void)312 static void mx28_mem_init(void)
313 {
314 struct mxs_pinctrl_regs *pinctrl_regs =
315 (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
316
317 debug("SPL: Initialising mx28 SDRAM Controller\n");
318
319 /* Set DDR2 mode */
320 writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
321 &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
322
323 /*
324 * Configure the DRAM registers
325 */
326
327 /* Clear START bit from DRAM_CTL16 */
328 clrbits_le32(MXS_DRAM_BASE + 0x40, 1);
329
330 initialize_dram_values();
331
332 /* Clear SREFRESH bit from DRAM_CTL17 */
333 clrbits_le32(MXS_DRAM_BASE + 0x44, 1);
334
335 /* Set START bit in DRAM_CTL16 */
336 setbits_le32(MXS_DRAM_BASE + 0x40, 1);
337
338 /* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */
339 while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
340 ;
341 }
342 #endif
343
mxs_mem_init(void)344 void mxs_mem_init(void)
345 {
346 early_delay(11000);
347
348 mxs_mem_init_clock();
349
350 mxs_mem_setup_vdda();
351
352 #if defined(CONFIG_MX23)
353 mx23_mem_init();
354 #elif defined(CONFIG_MX28)
355 mx28_mem_init();
356 #endif
357
358 early_delay(10000);
359
360 mxs_mem_setup_cpu_and_hbus();
361 }
362