1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2013
4 * David Feng <fenghua@phytium.com.cn>
5 */
6
7#include <asm-offsets.h>
8#include <config.h>
9#include <linux/linkage.h>
10#include <asm/macro.h>
11#include <asm/armv8/mmu.h>
12
13/*************************************************************************
14 *
15 * Startup Code (reset vector)
16 *
17 *************************************************************************/
18
19.globl	_start
20_start:
21#if defined(CONFIG_LINUX_KERNEL_IMAGE_HEADER)
22#include <asm/boot0-linux-kernel-header.h>
23#elif defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK)
24/*
25 * Various SoCs need something special and SoC-specific up front in
26 * order to boot, allow them to set that in their boot0.h file and then
27 * use it here.
28 */
29#include <asm/arch/boot0.h>
30#else
31	b	reset
32#endif
33
34	.align 3
35
36.globl	_TEXT_BASE
37_TEXT_BASE:
38	.quad	CONFIG_SYS_TEXT_BASE
39
40/*
41 * These are defined in the linker script.
42 */
43.globl	_end_ofs
44_end_ofs:
45	.quad	_end - _start
46
47.globl	_bss_start_ofs
48_bss_start_ofs:
49	.quad	__bss_start - _start
50
51.globl	_bss_end_ofs
52_bss_end_ofs:
53	.quad	__bss_end - _start
54
55reset:
56	/* Allow the board to save important registers */
57	b	save_boot_params
58.globl	save_boot_params_ret
59save_boot_params_ret:
60
61#if CONFIG_POSITION_INDEPENDENT
62	/* Verify that we're 4K aligned.  */
63	adr	x0, _start
64	ands	x0, x0, #0xfff
65	b.eq	1f
660:
67	/*
68	 * FATAL, can't continue.
69	 * U-Boot needs to be loaded at a 4K aligned address.
70	 *
71	 * We use ADRP and ADD to load some symbol addresses during startup.
72	 * The ADD uses an absolute (non pc-relative) lo12 relocation
73	 * thus requiring 4K alignment.
74	 */
75	wfi
76	b	0b
771:
78
79	/*
80	 * Fix .rela.dyn relocations. This allows U-Boot to be loaded to and
81	 * executed at a different address than it was linked at.
82	 */
83pie_fixup:
84	adr	x0, _start		/* x0 <- Runtime value of _start */
85	ldr	x1, _TEXT_BASE		/* x1 <- Linked value of _start */
86	subs	x9, x0, x1		/* x9 <- Run-vs-link offset */
87	beq	pie_fixup_done
88	adrp    x2, __rel_dyn_start     /* x2 <- Runtime &__rel_dyn_start */
89	add     x2, x2, #:lo12:__rel_dyn_start
90	adrp    x3, __rel_dyn_end       /* x3 <- Runtime &__rel_dyn_end */
91	add     x3, x3, #:lo12:__rel_dyn_end
92pie_fix_loop:
93	ldp	x0, x1, [x2], #16	/* (x0, x1) <- (Link location, fixup) */
94	ldr	x4, [x2], #8		/* x4 <- addend */
95	cmp	w1, #1027		/* relative fixup? */
96	bne	pie_skip_reloc
97	/* relative fix: store addend plus offset at dest location */
98	add	x0, x0, x9
99	add	x4, x4, x9
100	str	x4, [x0]
101pie_skip_reloc:
102	cmp	x2, x3
103	b.lo	pie_fix_loop
104pie_fixup_done:
105#endif
106
107#ifdef CONFIG_SYS_RESET_SCTRL
108	bl reset_sctrl
109#endif
110
111#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
112.macro	set_vbar, regname, reg
113	msr	\regname, \reg
114.endm
115	adr	x0, vectors
116#else
117.macro	set_vbar, regname, reg
118.endm
119#endif
120	/*
121	 * Could be EL3/EL2/EL1, Initial State:
122	 * Little Endian, MMU Disabled, i/dCache Disabled
123	 */
124	switch_el x1, 3f, 2f, 1f
1253:	set_vbar vbar_el3, x0
126	mrs	x0, scr_el3
127	orr	x0, x0, #0xf			/* SCR_EL3.NS|IRQ|FIQ|EA */
128	msr	scr_el3, x0
129	msr	cptr_el3, xzr			/* Enable FP/SIMD */
130	b	0f
1312:	mrs	x1, hcr_el2
132	tbnz	x1, #34, 1f			/* HCR_EL2.E2H */
133	set_vbar vbar_el2, x0
134	mov	x0, #0x33ff
135	msr	cptr_el2, x0			/* Enable FP/SIMD */
136	b	0f
1371:	set_vbar vbar_el1, x0
138	mov	x0, #3 << 20
139	msr	cpacr_el1, x0			/* Enable FP/SIMD */
1400:
141
142#ifdef COUNTER_FREQUENCY
143	branch_if_not_highest_el x0, 4f
144	ldr	x0, =COUNTER_FREQUENCY
145	msr	cntfrq_el0, x0			/* Initialize CNTFRQ */
146#endif
147
1484:	isb
149
150	/*
151	 * Enable SMPEN bit for coherency.
152	 * This register is not architectural but at the moment
153	 * this bit should be set for A53/A57/A72.
154	 */
155#ifdef CONFIG_ARMV8_SET_SMPEN
156	switch_el x1, 3f, 1f, 1f
1573:
158	mrs     x0, S3_1_c15_c2_1               /* cpuectlr_el1 */
159	orr     x0, x0, #0x40
160	msr     S3_1_c15_c2_1, x0
161	isb
1621:
163#endif
164
165	/* Apply ARM core specific erratas */
166	bl	apply_core_errata
167
168	/*
169	 * Cache/BPB/TLB Invalidate
170	 * i-cache is invalidated before enabled in icache_enable()
171	 * tlb is invalidated before mmu is enabled in dcache_enable()
172	 * d-cache is invalidated before enabled in dcache_enable()
173	 */
174
175	/* Processor specific initialization */
176	bl	lowlevel_init
177
178#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD)
179	branch_if_master x0, x1, master_cpu
180	b	spin_table_secondary_jump
181	/* never return */
182#elif defined(CONFIG_ARMV8_MULTIENTRY)
183	branch_if_master x0, x1, master_cpu
184
185	/*
186	 * Slave CPUs
187	 */
188slave_cpu:
189	wfe
190	ldr	x1, =CPU_RELEASE_ADDR
191	ldr	x0, [x1]
192	cbz	x0, slave_cpu
193	br	x0			/* branch to the given address */
194#endif /* CONFIG_ARMV8_MULTIENTRY */
195master_cpu:
196	bl	_main
197
198#ifdef CONFIG_SYS_RESET_SCTRL
199reset_sctrl:
200	switch_el x1, 3f, 2f, 1f
2013:
202	mrs	x0, sctlr_el3
203	b	0f
2042:
205	mrs	x0, sctlr_el2
206	b	0f
2071:
208	mrs	x0, sctlr_el1
209
2100:
211	ldr	x1, =0xfdfffffa
212	and	x0, x0, x1
213
214	switch_el x1, 6f, 5f, 4f
2156:
216	msr	sctlr_el3, x0
217	b	7f
2185:
219	msr	sctlr_el2, x0
220	b	7f
2214:
222	msr	sctlr_el1, x0
223
2247:
225	dsb	sy
226	isb
227	b	__asm_invalidate_tlb_all
228	ret
229#endif
230
231/*-----------------------------------------------------------------------*/
232
233WEAK(apply_core_errata)
234
235	mov	x29, lr			/* Save LR */
236	/* For now, we support Cortex-A53, Cortex-A57 specific errata */
237
238	/* Check if we are running on a Cortex-A53 core */
239	branch_if_a53_core x0, apply_a53_core_errata
240
241	/* Check if we are running on a Cortex-A57 core */
242	branch_if_a57_core x0, apply_a57_core_errata
2430:
244	mov	lr, x29			/* Restore LR */
245	ret
246
247apply_a53_core_errata:
248
249#ifdef CONFIG_ARM_ERRATA_855873
250	mrs	x0, midr_el1
251	tst	x0, #(0xf << 20)
252	b.ne	0b
253
254	mrs	x0, midr_el1
255	and	x0, x0, #0xf
256	cmp	x0, #3
257	b.lt	0b
258
259	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
260	/* Enable data cache clean as data cache clean/invalidate */
261	orr	x0, x0, #1 << 44
262	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
263	isb
264#endif
265	b 0b
266
267apply_a57_core_errata:
268
269#ifdef CONFIG_ARM_ERRATA_828024
270	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
271	/* Disable non-allocate hint of w-b-n-a memory type */
272	orr	x0, x0, #1 << 49
273	/* Disable write streaming no L1-allocate threshold */
274	orr	x0, x0, #3 << 25
275	/* Disable write streaming no-allocate threshold */
276	orr	x0, x0, #3 << 27
277	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
278	isb
279#endif
280
281#ifdef CONFIG_ARM_ERRATA_826974
282	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
283	/* Disable speculative load execution ahead of a DMB */
284	orr	x0, x0, #1 << 59
285	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
286	isb
287#endif
288
289#ifdef CONFIG_ARM_ERRATA_833471
290	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
291	/* FPSCR write flush.
292	 * Note that in some cases where a flush is unnecessary this
293	    could impact performance. */
294	orr	x0, x0, #1 << 38
295	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
296	isb
297#endif
298
299#ifdef CONFIG_ARM_ERRATA_829520
300	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
301	/* Disable Indirect Predictor bit will prevent this erratum
302	    from occurring
303	 * Note that in some cases where a flush is unnecessary this
304	    could impact performance. */
305	orr	x0, x0, #1 << 4
306	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
307	isb
308#endif
309
310#ifdef CONFIG_ARM_ERRATA_833069
311	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
312	/* Disable Enable Invalidates of BTB bit */
313	and	x0, x0, #0xE
314	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
315	isb
316#endif
317	b 0b
318ENDPROC(apply_core_errata)
319
320/*-----------------------------------------------------------------------*/
321
322WEAK(lowlevel_init)
323	mov	x29, lr			/* Save LR */
324
325#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
326	branch_if_slave x0, 1f
327	ldr	x0, =GICD_BASE
328	bl	gic_init_secure
3291:
330#if defined(CONFIG_GICV3)
331	ldr	x0, =GICR_BASE
332	bl	gic_init_secure_percpu
333#elif defined(CONFIG_GICV2)
334	ldr	x0, =GICD_BASE
335	ldr	x1, =GICC_BASE
336	bl	gic_init_secure_percpu
337#endif
338#endif
339
340#ifdef CONFIG_ARMV8_MULTIENTRY
341	branch_if_master x0, x1, 2f
342
343	/*
344	 * Slave should wait for master clearing spin table.
345	 * This sync prevent salves observing incorrect
346	 * value of spin table and jumping to wrong place.
347	 */
348#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
349#ifdef CONFIG_GICV2
350	ldr	x0, =GICC_BASE
351#endif
352	bl	gic_wait_for_interrupt
353#endif
354
355	/*
356	 * All slaves will enter EL2 and optionally EL1.
357	 */
358	adr	x4, lowlevel_in_el2
359	ldr	x5, =ES_TO_AARCH64
360	bl	armv8_switch_to_el2
361
362lowlevel_in_el2:
363#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
364	adr	x4, lowlevel_in_el1
365	ldr	x5, =ES_TO_AARCH64
366	bl	armv8_switch_to_el1
367
368lowlevel_in_el1:
369#endif
370
371#endif /* CONFIG_ARMV8_MULTIENTRY */
372
3732:
374	mov	lr, x29			/* Restore LR */
375	ret
376ENDPROC(lowlevel_init)
377
378WEAK(smp_kick_all_cpus)
379	/* Kick secondary cpus up by SGI 0 interrupt */
380#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
381	ldr	x0, =GICD_BASE
382	b	gic_kick_secondary_cpus
383#endif
384	ret
385ENDPROC(smp_kick_all_cpus)
386
387/*-----------------------------------------------------------------------*/
388
389ENTRY(c_runtime_cpu_setup)
390#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
391	/* Relocate vBAR */
392	adr	x0, vectors
393	switch_el x1, 3f, 2f, 1f
3943:	msr	vbar_el3, x0
395	b	0f
3962:	msr	vbar_el2, x0
397	b	0f
3981:	msr	vbar_el1, x0
3990:
400#endif
401
402	ret
403ENDPROC(c_runtime_cpu_setup)
404
405WEAK(save_boot_params)
406	b	save_boot_params_ret	/* back to my caller */
407ENDPROC(save_boot_params)
408