1// SPDX-License-Identifier: GPL-2.0+ OR X11 2/* 3 * NXP ls1088a SOC common device tree source 4 * 5 * Copyright 2017, 2020-2021 NXP 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9/ { 10 compatible = "fsl,ls1088a"; 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 memory@80000000 { 16 device_type = "memory"; 17 reg = <0x00000000 0x80000000 0 0x80000000>; 18 /* DRAM space - 1, size : 2 GB DRAM */ 19 }; 20 21 gic: interrupt-controller@6000000 { 22 compatible = "arm,gic-v3"; 23 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 24 <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */ 25 #interrupt-cells = <3>; 26 interrupt-controller; 27 interrupts = <1 9 0x4>; 28 }; 29 30 timer { 31 compatible = "arm,armv8-timer"; 32 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ 33 <1 14 0x8>, /* Physical Non-Secure PPI, active-low */ 34 <1 11 0x8>, /* Virtual PPI, active-low */ 35 <1 10 0x8>; /* Hypervisor PPI, active-low */ 36 }; 37 38 i2c0: i2c@2000000 { 39 compatible = "fsl,vf610-i2c"; 40 #address-cells = <1>; 41 #size-cells = <0>; 42 reg = <0x0 0x2000000 0x0 0x10000>; 43 interrupts = <0 34 4>; 44 }; 45 46 i2c1: i2c@2010000 { 47 compatible = "fsl,vf610-i2c"; 48 #address-cells = <1>; 49 #size-cells = <0>; 50 reg = <0x0 0x2010000 0x0 0x10000>; 51 interrupts = <0 34 4>; 52 }; 53 54 i2c2: i2c@2020000 { 55 compatible = "fsl,vf610-i2c"; 56 #address-cells = <1>; 57 #size-cells = <0>; 58 reg = <0x0 0x2020000 0x0 0x10000>; 59 interrupts = <0 35 4>; 60 }; 61 62 i2c3: i2c@2030000 { 63 compatible = "fsl,vf610-i2c"; 64 #address-cells = <1>; 65 #size-cells = <0>; 66 reg = <0x0 0x2030000 0x0 0x10000>; 67 interrupts = <0 35 4>; 68 }; 69 70 serial0: serial@21c0500 { 71 device_type = "serial"; 72 compatible = "fsl,ns16550", "ns16550a"; 73 reg = <0x0 0x21c0500 0x0 0x100>; 74 clock-frequency = <0>; /* Updated by bootloader */ 75 interrupts = <0 32 0x1>; /* edge triggered */ 76 }; 77 78 serial1: serial@21c0600 { 79 device_type = "serial"; 80 compatible = "fsl,ns16550", "ns16550a"; 81 reg = <0x0 0x21c0600 0x0 0x100>; 82 clock-frequency = <0>; /* Updated by bootloader */ 83 interrupts = <0 32 0x1>; /* edge triggered */ 84 }; 85 86 dspi: dspi@2100000 { 87 compatible = "fsl,vf610-dspi"; 88 #address-cells = <1>; 89 #size-cells = <0>; 90 reg = <0x0 0x2100000 0x0 0x10000>; 91 interrupts = <0 26 0x4>; /* Level high type */ 92 num-cs = <6>; 93 }; 94 95 qspi: quadspi@1550000 { 96 compatible = "fsl,ls1088a-qspi"; 97 #address-cells = <1>; 98 #size-cells = <0>; 99 reg = <0x0 0x20c0000 0x0 0x10000>, 100 <0x0 0x20000000 0x0 0x10000000>; 101 reg-names = "QuadSPI", "QuadSPI-memory"; 102 num-cs = <4>; 103 }; 104 105 esdhc: esdhc@2140000 { 106 compatible = "fsl,esdhc"; 107 reg = <0x0 0x2140000 0x0 0x10000>; 108 interrupts = <0 28 0x4>; /* Level high type */ 109 little-endian; 110 bus-width = <4>; 111 }; 112 113 gpio0: gpio@2300000 { 114 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 115 reg = <0x0 0x2300000 0x0 0x10000>; 116 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 117 little-endian; 118 gpio-controller; 119 #gpio-cells = <2>; 120 interrupt-controller; 121 #interrupt-cells = <2>; 122 }; 123 124 gpio1: gpio@2310000 { 125 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 126 reg = <0x0 0x2310000 0x0 0x10000>; 127 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 128 little-endian; 129 gpio-controller; 130 #gpio-cells = <2>; 131 interrupt-controller; 132 #interrupt-cells = <2>; 133 }; 134 135 gpio2: gpio@2320000 { 136 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 137 reg = <0x0 0x2320000 0x0 0x10000>; 138 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 139 little-endian; 140 gpio-controller; 141 #gpio-cells = <2>; 142 interrupt-controller; 143 #interrupt-cells = <2>; 144 }; 145 146 gpio3: gpio@2330000 { 147 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 148 reg = <0x0 0x2330000 0x0 0x10000>; 149 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 150 little-endian; 151 gpio-controller; 152 #gpio-cells = <2>; 153 interrupt-controller; 154 #interrupt-cells = <2>; 155 }; 156 157 ifc: ifc@1530000 { 158 compatible = "fsl,ifc", "simple-bus"; 159 reg = <0x0 0x2240000 0x0 0x20000>; 160 interrupts = <0 21 0x4>; /* Level high type */ 161 }; 162 163 usb0: usb3@3100000 { 164 compatible = "fsl,layerscape-dwc3"; 165 reg = <0x0 0x3100000 0x0 0x10000>; 166 interrupts = <0 80 0x4>; /* Level high type */ 167 dr_mode = "host"; 168 }; 169 170 usb1: usb3@3110000 { 171 compatible = "fsl,layerscape-dwc3"; 172 reg = <0x0 0x3110000 0x0 0x10000>; 173 interrupts = <0 81 0x4>; /* Level high type */ 174 dr_mode = "host"; 175 }; 176 177 pcie1: pcie@3400000 { 178 compatible = "fsl,ls-pcie", "snps,dw-pcie"; 179 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ 180 0x00 0x03480000 0x0 0x80000 /* lut registers */ 181 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */ 182 0x20 0x00000000 0x0 0x20000>; /* configuration space */ 183 reg-names = "dbi", "lut", "ctrl", "config"; 184 #address-cells = <3>; 185 #size-cells = <2>; 186 device_type = "pci"; 187 num-lanes = <4>; 188 bus-range = <0x0 0xff>; 189 ranges = <0x81000000 0x0 0x00000000 0x20 0x00020000 0x0 0x00010000 /* downstream I/O */ 190 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 191 }; 192 193 pcie2: pcie@3500000 { 194 compatible = "fsl,ls-pcie", "snps,dw-pcie"; 195 reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */ 196 0x00 0x03580000 0x0 0x80000 /* lut registers */ 197 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */ 198 0x28 0x00000000 0x0 0x20000>; /* configuration space */ 199 reg-names = "dbi", "lut", "ctrl", "config"; 200 #address-cells = <3>; 201 #size-cells = <2>; 202 device_type = "pci"; 203 num-lanes = <4>; 204 bus-range = <0x0 0xff>; 205 ranges = <0x81000000 0x0 0x00000000 0x28 0x00020000 0x0 0x00010000 /* downstream I/O */ 206 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 207 }; 208 209 pcie3: pcie@3600000 { 210 compatible = "fsl,ls-pcie", "snps,dw-pcie"; 211 reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */ 212 0x00 0x03680000 0x0 0x80000 /* lut registers */ 213 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */ 214 0x30 0x00000000 0x0 0x20000>; /* configuration space */ 215 reg-names = "dbi", "lut", "ctrl", "config"; 216 #address-cells = <3>; 217 #size-cells = <2>; 218 device_type = "pci"; 219 num-lanes = <8>; 220 bus-range = <0x0 0xff>; 221 ranges = <0x81000000 0x0 0x00000000 0x30 0x00020000 0x0 0x00010000 /* downstream I/O */ 222 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 223 }; 224 225 sata: sata@3200000 { 226 compatible = "fsl,ls1088a-ahci"; 227 reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ 228 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/ 229 reg-names = "sata-base", "ecc-addr"; 230 interrupts = <0 133 4>; 231 status = "disabled"; 232 }; 233 234 psci { 235 compatible = "arm,psci-0.2"; 236 method = "smc"; 237 }; 238 239 fsl_mc: fsl-mc@80c000000 { 240 compatible = "fsl,qoriq-mc", "simple-mfd"; 241 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ 242 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ 243 #address-cells = <3>; 244 #size-cells = <1>; 245 246 /* 247 * Region type 0x0 - MC portals 248 * Region type 0x1 - QBMAN portals 249 */ 250 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 251 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 252 253 dpmacs { 254 compatible = "simple-mfd"; 255 #address-cells = <1>; 256 #size-cells = <0>; 257 258 dpmac1: dpmac@1 { 259 compatible = "fsl,qoriq-mc-dpmac"; 260 reg = <0x1>; 261 status = "disabled"; 262 }; 263 264 dpmac2: dpmac@2 { 265 compatible = "fsl,qoriq-mc-dpmac"; 266 reg = <0x2>; 267 status = "disabled"; 268 }; 269 270 dpmac3: dpmac@3 { 271 compatible = "fsl,qoriq-mc-dpmac"; 272 reg = <0x3>; 273 status = "disabled"; 274 }; 275 276 dpmac4: dpmac@4 { 277 compatible = "fsl,qoriq-mc-dpmac"; 278 reg = <0x4>; 279 status = "disabled"; 280 }; 281 282 dpmac5: dpmac@5 { 283 compatible = "fsl,qoriq-mc-dpmac"; 284 reg = <0x5>; 285 status = "disabled"; 286 }; 287 288 dpmac6: dpmac@6 { 289 compatible = "fsl,qoriq-mc-dpmac"; 290 reg = <0x6>; 291 status = "disabled"; 292 }; 293 294 dpmac7: dpmac@7 { 295 compatible = "fsl,qoriq-mc-dpmac"; 296 reg = <0x7>; 297 status = "disabled"; 298 }; 299 300 dpmac8: dpmac@8 { 301 compatible = "fsl,qoriq-mc-dpmac"; 302 reg = <0x8>; 303 status = "disabled"; 304 }; 305 306 dpmac9: dpmac@9 { 307 compatible = "fsl,qoriq-mc-dpmac"; 308 reg = <0x9>; 309 status = "disabled"; 310 }; 311 312 dpmac10: dpmac@a { 313 compatible = "fsl,qoriq-mc-dpmac"; 314 reg = <0xa>; 315 status = "disabled"; 316 }; 317 }; 318 }; 319 320 emdio1: mdio@8B96000 { 321 compatible = "fsl,ls-mdio"; 322 reg = <0x0 0x8B96000 0x0 0x1000>; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 status = "disabled"; 326 }; 327 328 emdio2: mdio@8B97000 { 329 compatible = "fsl,ls-mdio"; 330 reg = <0x0 0x8B97000 0x0 0x1000>; 331 #address-cells = <1>; 332 #size-cells = <0>; 333 status = "disabled"; 334 }; 335}; 336