1/* 2 * Copyright 2017 Gateworks Corporation 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public 20 * License along with this file; if not, write to the Free 21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 * 24 * Or, alternatively, 25 * 26 * b) Permission is hereby granted, free of charge, to any person 27 * obtaining a copy of this software and associated documentation 28 * files (the "Software"), to deal in the Software without 29 * restriction, including without limitation the rights to use, 30 * copy, modify, merge, publish, distribute, sublicense, and/or 31 * sell copies of the Software, and to permit persons to whom the 32 * Software is furnished to do so, subject to the following 33 * conditions: 34 * 35 * The above copyright notice and this permission notice shall be 36 * included in all copies or substantial portions of the Software. 37 * 38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 * OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48#include <dt-bindings/gpio/gpio.h> 49#include <dt-bindings/input/linux-event-codes.h> 50#include <dt-bindings/interrupt-controller/irq.h> 51 52/ { 53 /* these are used by bootloader for disabling nodes */ 54 aliases { 55 led0 = &led0; 56 led1 = &led1; 57 led2 = &led2; 58 mmc0 = &usdhc3; 59 usb0 = &usbotg; 60 usb1 = &usbh1; 61 }; 62 63 chosen { 64 stdout-path = &uart2; 65 }; 66 67 backlight { 68 compatible = "pwm-backlight"; 69 pwms = <&pwm4 0 5000000>; 70 brightness-levels = <0 4 8 16 32 64 128 255>; 71 default-brightness-level = <7>; 72 }; 73 74 gpio-keys { 75 compatible = "gpio-keys"; 76 #address-cells = <1>; 77 #size-cells = <0>; 78 79 user-pb { 80 label = "user_pb"; 81 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 82 linux,code = <BTN_0>; 83 }; 84 85 user-pb1x { 86 label = "user_pb1x"; 87 linux,code = <BTN_1>; 88 interrupt-parent = <&gsc>; 89 interrupts = <0>; 90 }; 91 92 key-erased { 93 label = "key-erased"; 94 linux,code = <BTN_2>; 95 interrupt-parent = <&gsc>; 96 interrupts = <1>; 97 }; 98 99 eeprom-wp { 100 label = "eeprom_wp"; 101 linux,code = <BTN_3>; 102 interrupt-parent = <&gsc>; 103 interrupts = <2>; 104 }; 105 106 tamper { 107 label = "tamper"; 108 linux,code = <BTN_4>; 109 interrupt-parent = <&gsc>; 110 interrupts = <5>; 111 }; 112 113 switch-hold { 114 label = "switch_hold"; 115 linux,code = <BTN_5>; 116 interrupt-parent = <&gsc>; 117 interrupts = <7>; 118 }; 119 }; 120 121 leds { 122 compatible = "gpio-leds"; 123 pinctrl-names = "default"; 124 pinctrl-0 = <&pinctrl_gpio_leds>; 125 126 led0: user1 { 127 label = "user1"; 128 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 129 default-state = "on"; 130 linux,default-trigger = "heartbeat"; 131 }; 132 133 led1: user2 { 134 label = "user2"; 135 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 136 default-state = "off"; 137 }; 138 139 led2: user3 { 140 label = "user3"; 141 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 142 default-state = "off"; 143 }; 144 }; 145 146 memory@10000000 { 147 device_type = "memory"; 148 reg = <0x10000000 0x40000000>; 149 }; 150 151 pps { 152 compatible = "pps-gpio"; 153 pinctrl-names = "default"; 154 pinctrl-0 = <&pinctrl_pps>; 155 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 156 }; 157 158 reg_1p0v: regulator-1p0v { 159 compatible = "regulator-fixed"; 160 regulator-name = "1P0V"; 161 regulator-min-microvolt = <1000000>; 162 regulator-max-microvolt = <1000000>; 163 regulator-always-on; 164 }; 165 166 reg_3p3v: regulator-3p3v { 167 compatible = "regulator-fixed"; 168 regulator-name = "3P3V"; 169 regulator-min-microvolt = <3300000>; 170 regulator-max-microvolt = <3300000>; 171 regulator-always-on; 172 }; 173 174 reg_usb_h1_vbus: regulator-usb-h1-vbus { 175 compatible = "regulator-fixed"; 176 regulator-name = "usb_h1_vbus"; 177 regulator-min-microvolt = <5000000>; 178 regulator-max-microvolt = <5000000>; 179 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 180 enable-active-high; 181 }; 182 183 reg_usb_otg_vbus: regulator-usb-otg-vbus { 184 compatible = "regulator-fixed"; 185 regulator-name = "usb_otg_vbus"; 186 regulator-min-microvolt = <5000000>; 187 regulator-max-microvolt = <5000000>; 188 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 189 enable-active-high; 190 }; 191}; 192 193&clks { 194 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 195 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 196 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 197 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 198}; 199 200&fec { 201 pinctrl-names = "default"; 202 pinctrl-0 = <&pinctrl_enet>; 203 phy-mode = "rgmii-id"; 204 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 205 phy-reset-duration = <10>; 206 phy-reset-post-delay = <100>; 207 status = "okay"; 208 209 fixed-link { 210 speed = <1000>; 211 full-duplex; 212 }; 213 214 mdio { 215 #address-cells = <1>; 216 #size-cells = <0>; 217 218 switch@0 { 219 compatible = "marvell,mv88e6085"; 220 reg = <0>; 221 222 ports { 223 #address-cells = <1>; 224 #size-cells = <0>; 225 226 port@0 { 227 reg = <0>; 228 label = "lan4"; 229 }; 230 231 port@1 { 232 reg = <1>; 233 label = "lan3"; 234 }; 235 236 port@2 { 237 reg = <2>; 238 label = "lan2"; 239 }; 240 241 port@3 { 242 reg = <3>; 243 label = "lan1"; 244 }; 245 246 port@5 { 247 reg = <5>; 248 label = "cpu"; 249 ethernet = <&fec>; 250 }; 251 }; 252 }; 253 }; 254}; 255 256&i2c1 { 257 clock-frequency = <100000>; 258 pinctrl-names = "default"; 259 pinctrl-0 = <&pinctrl_i2c1>; 260 status = "okay"; 261 262 gsc: gsc@20 { 263 compatible = "gw,gsc"; 264 reg = <0x20>; 265 interrupt-parent = <&gpio1>; 266 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 267 interrupt-controller; 268 #interrupt-cells = <1>; 269 #size-cells = <0>; 270 271 adc { 272 compatible = "gw,gsc-adc"; 273 #address-cells = <1>; 274 #size-cells = <0>; 275 276 channel@0 { 277 gw,mode = <0>; 278 reg = <0x00>; 279 label = "temp"; 280 }; 281 282 channel@2 { 283 gw,mode = <1>; 284 reg = <0x02>; 285 label = "vdd_vin"; 286 }; 287 288 channel@5 { 289 gw,mode = <1>; 290 reg = <0x05>; 291 label = "vdd_3p3"; 292 }; 293 294 channel@8 { 295 gw,mode = <1>; 296 reg = <0x08>; 297 label = "vdd_bat"; 298 }; 299 300 channel@b { 301 gw,mode = <1>; 302 reg = <0x0b>; 303 label = "vdd_5p0"; 304 }; 305 306 channel@e { 307 gw,mode = <1>; 308 reg = <0xe>; 309 label = "vdd_arm"; 310 }; 311 312 channel@11 { 313 gw,mode = <1>; 314 reg = <0x11>; 315 label = "vdd_soc"; 316 }; 317 318 channel@14 { 319 gw,mode = <1>; 320 reg = <0x14>; 321 label = "vdd_3p0"; 322 }; 323 324 channel@17 { 325 gw,mode = <1>; 326 reg = <0x17>; 327 label = "vdd_1p5"; 328 }; 329 330 channel@1d { 331 gw,mode = <1>; 332 reg = <0x1d>; 333 label = "vdd_1p8"; 334 }; 335 336 channel@20 { 337 gw,mode = <1>; 338 reg = <0x20>; 339 label = "vdd_an1"; 340 }; 341 342 channel@23 { 343 gw,mode = <1>; 344 reg = <0x23>; 345 label = "vdd_2p5"; 346 }; 347 }; 348 }; 349 350 gsc_gpio: gpio@23 { 351 compatible = "nxp,pca9555"; 352 reg = <0x23>; 353 gpio-controller; 354 #gpio-cells = <2>; 355 interrupt-parent = <&gsc>; 356 interrupts = <4>; 357 }; 358 359 eeprom1: eeprom@50 { 360 compatible = "atmel,24c02"; 361 reg = <0x50>; 362 pagesize = <16>; 363 }; 364 365 eeprom2: eeprom@51 { 366 compatible = "atmel,24c02"; 367 reg = <0x51>; 368 pagesize = <16>; 369 }; 370 371 eeprom3: eeprom@52 { 372 compatible = "atmel,24c02"; 373 reg = <0x52>; 374 pagesize = <16>; 375 }; 376 377 eeprom4: eeprom@53 { 378 compatible = "atmel,24c02"; 379 reg = <0x53>; 380 pagesize = <16>; 381 }; 382 383 dts1672: rtc@68 { 384 compatible = "dallas,ds1672"; 385 reg = <0x68>; 386 }; 387}; 388 389&i2c2 { 390 clock-frequency = <100000>; 391 pinctrl-names = "default"; 392 pinctrl-0 = <&pinctrl_i2c2>; 393 status = "okay"; 394 395 magn@1c { 396 compatible = "st,lsm9ds1-magn"; 397 reg = <0x1c>; 398 pinctrl-names = "default"; 399 pinctrl-0 = <&pinctrl_mag>; 400 interrupt-parent = <&gpio5>; 401 interrupts = <17 IRQ_TYPE_EDGE_RISING>; 402 }; 403 404 ltc3676: pmic@3c { 405 compatible = "lltc,ltc3676"; 406 reg = <0x3c>; 407 interrupt-parent = <&gpio1>; 408 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 409 410 regulators { 411 /* VDD_SOC (1+R1/R2 = 1.635) */ 412 reg_vdd_soc: sw1 { 413 regulator-name = "vddsoc"; 414 regulator-min-microvolt = <674400>; 415 regulator-max-microvolt = <1308000>; 416 lltc,fb-voltage-divider = <127000 200000>; 417 regulator-ramp-delay = <7000>; 418 regulator-boot-on; 419 regulator-always-on; 420 }; 421 422 /* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */ 423 reg_1p8v: sw2 { 424 regulator-name = "vdd1p8"; 425 regulator-min-microvolt = <1033310>; 426 regulator-max-microvolt = <2004000>; 427 lltc,fb-voltage-divider = <301000 200000>; 428 regulator-ramp-delay = <7000>; 429 regulator-boot-on; 430 regulator-always-on; 431 }; 432 433 /* VDD_ARM (1+R1/R2 = 1.635) */ 434 reg_vdd_arm: sw3 { 435 regulator-name = "vddarm"; 436 regulator-min-microvolt = <674400>; 437 regulator-max-microvolt = <1308000>; 438 lltc,fb-voltage-divider = <127000 200000>; 439 regulator-ramp-delay = <7000>; 440 regulator-boot-on; 441 regulator-always-on; 442 }; 443 444 /* VDD_DDR (1+R1/R2 = 2.105) */ 445 reg_vdd_ddr: sw4 { 446 regulator-name = "vddddr"; 447 regulator-min-microvolt = <868310>; 448 regulator-max-microvolt = <1684000>; 449 lltc,fb-voltage-divider = <221000 200000>; 450 regulator-ramp-delay = <7000>; 451 regulator-boot-on; 452 regulator-always-on; 453 }; 454 455 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ 456 reg_2p5v: ldo2 { 457 regulator-name = "vdd2p5"; 458 regulator-min-microvolt = <2490375>; 459 regulator-max-microvolt = <2490375>; 460 lltc,fb-voltage-divider = <487000 200000>; 461 regulator-boot-on; 462 regulator-always-on; 463 }; 464 465 /* VDD_HIGH (1+R1/R2 = 4.17) */ 466 reg_3p0v: ldo4 { 467 regulator-name = "vdd3p0"; 468 regulator-min-microvolt = <3023250>; 469 regulator-max-microvolt = <3023250>; 470 lltc,fb-voltage-divider = <634000 200000>; 471 regulator-boot-on; 472 regulator-always-on; 473 }; 474 }; 475 }; 476 477 imu@6a { 478 compatible = "st,lsm9ds1-imu"; 479 reg = <0x6a>; 480 st,drdy-int-pin = <1>; 481 pinctrl-names = "default"; 482 pinctrl-0 = <&pinctrl_imu>; 483 interrupt-parent = <&gpio4>; 484 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; 485 }; 486}; 487 488&i2c3 { 489 clock-frequency = <100000>; 490 pinctrl-names = "default"; 491 pinctrl-0 = <&pinctrl_i2c3>; 492 status = "okay"; 493 494 egalax_ts: touchscreen@4 { 495 compatible = "eeti,egalax_ts"; 496 reg = <0x04>; 497 interrupt-parent = <&gpio1>; 498 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 499 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 500 }; 501}; 502 503&ldb { 504 status = "okay"; 505 506 lvds-channel@0 { 507 fsl,data-mapping = "spwg"; 508 fsl,data-width = <18>; 509 status = "okay"; 510 511 display-timings { 512 native-mode = <&timing0>; 513 timing0: hsd100pxn1 { 514 clock-frequency = <65000000>; 515 hactive = <1024>; 516 vactive = <768>; 517 hback-porch = <220>; 518 hfront-porch = <40>; 519 vback-porch = <21>; 520 vfront-porch = <7>; 521 hsync-len = <60>; 522 vsync-len = <10>; 523 }; 524 }; 525 }; 526}; 527 528&pcie { 529 pinctrl-names = "default"; 530 pinctrl-0 = <&pinctrl_pcie>; 531 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; 532 status = "okay"; 533}; 534 535&pwm2 { 536 pinctrl-names = "default"; 537 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 538 status = "disabled"; 539}; 540 541&pwm3 { 542 pinctrl-names = "default"; 543 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 544 status = "disabled"; 545}; 546 547&pwm4 { 548 #pwm-cells = <2>; 549 pinctrl-names = "default"; 550 pinctrl-0 = <&pinctrl_pwm4>; 551 status = "okay"; 552}; 553 554&uart1 { 555 pinctrl-names = "default"; 556 pinctrl-0 = <&pinctrl_uart1>; 557 status = "okay"; 558}; 559 560&uart2 { 561 pinctrl-names = "default"; 562 pinctrl-0 = <&pinctrl_uart2>; 563 status = "okay"; 564}; 565 566&uart3 { 567 pinctrl-names = "default"; 568 pinctrl-0 = <&pinctrl_uart3>; 569 uart-has-rtscts; 570 status = "okay"; 571}; 572 573&uart4 { 574 pinctrl-names = "default"; 575 pinctrl-0 = <&pinctrl_uart4>; 576 uart-has-rtscts; 577 status = "okay"; 578}; 579 580&uart5 { 581 pinctrl-names = "default"; 582 pinctrl-0 = <&pinctrl_uart5>; 583 status = "okay"; 584}; 585 586&usbotg { 587 vbus-supply = <®_usb_otg_vbus>; 588 pinctrl-names = "default"; 589 pinctrl-0 = <&pinctrl_usbotg>; 590 disable-over-current; 591 dr_mode = "otg"; 592 status = "okay"; 593}; 594 595&usbh1 { 596 vbus-supply = <®_usb_h1_vbus>; 597 pinctrl-names = "default"; 598 pinctrl-0 = <&pinctrl_usbotg>; 599 status = "okay"; 600}; 601 602&usdhc3 { 603 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 604 pinctrl-0 = <&pinctrl_usdhc3>; 605 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 606 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 607 non-removable; 608 vmmc-supply = <®_3p3v>; 609 keep-power-in-suspend; 610 status = "okay"; 611}; 612 613&wdog1 { 614 pinctrl-names = "default"; 615 pinctrl-0 = <&pinctrl_wdog>; 616 fsl,ext-reset-output; 617}; 618 619&iomuxc { 620 pinctrl_enet: enetgrp { 621 fsl,pins = < 622 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 623 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 624 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 625 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 626 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 627 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 628 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 629 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 630 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 631 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 632 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 633 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 634 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 635 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 636 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 637 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 638 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ 639 >; 640 }; 641 642 pinctrl_gpio_leds: gpioledsgrp { 643 fsl,pins = < 644 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 645 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 646 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 647 >; 648 }; 649 650 pinctrl_i2c1: i2c1grp { 651 fsl,pins = < 652 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 653 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 654 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ 655 >; 656 }; 657 658 pinctrl_i2c2: i2c2grp { 659 fsl,pins = < 660 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 661 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 662 >; 663 }; 664 665 pinctrl_i2c3: i2c3grp { 666 fsl,pins = < 667 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 668 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 669 >; 670 }; 671 672 pinctrl_imu: imugrp { 673 fsl,pins = < 674 MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 675 >; 676 }; 677 678 pinctrl_mag: maggrp { 679 fsl,pins = < 680 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 681 >; 682 }; 683 684 pinctrl_pcie: pciegrp { 685 fsl,pins = < 686 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ 687 >; 688 }; 689 690 pinctrl_pmic: pmicgrp { 691 fsl,pins = < 692 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* PMIC_IRQ# */ 693 >; 694 }; 695 696 pinctrl_pps: ppsgrp { 697 fsl,pins = < 698 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 699 >; 700 }; 701 702 pinctrl_pwm2: pwm2grp { 703 fsl,pins = < 704 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 705 >; 706 }; 707 708 pinctrl_pwm3: pwm3grp { 709 fsl,pins = < 710 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 711 >; 712 }; 713 714 pinctrl_pwm4: pwm4grp { 715 fsl,pins = < 716 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 717 >; 718 }; 719 720 pinctrl_uart1: uart1grp { 721 fsl,pins = < 722 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 723 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 724 >; 725 }; 726 727 pinctrl_uart2: uart2grp { 728 fsl,pins = < 729 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 730 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 731 >; 732 }; 733 734 pinctrl_uart3: uart3grp { 735 fsl,pins = < 736 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 737 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 738 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 739 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 740 >; 741 }; 742 743 pinctrl_uart4: uart4grp { 744 fsl,pins = < 745 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 746 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 747 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 748 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 749 >; 750 }; 751 752 pinctrl_uart5: uart5grp { 753 fsl,pins = < 754 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 755 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 756 >; 757 }; 758 759 pinctrl_usbh1: usbh1grp { 760 fsl,pins = < 761 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 762 >; 763 }; 764 765 pinctrl_usbotg: usbotggrp { 766 fsl,pins = < 767 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 768 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ 769 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ 770 >; 771 }; 772 773 pinctrl_usdhc3: usdhc3grp { 774 fsl,pins = < 775 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 776 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 777 MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059 778 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 779 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 780 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 781 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 782 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 783 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 784 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 785 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 786 >; 787 }; 788 789 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 790 fsl,pins = < 791 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 792 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 793 MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9 794 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 795 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 796 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 797 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 798 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 799 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 800 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 801 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 802 >; 803 }; 804 805 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 806 fsl,pins = < 807 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 808 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 809 MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9 810 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 811 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 812 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 813 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 814 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 815 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 816 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 817 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 818 >; 819 }; 820 821 pinctrl_wdog: wdoggrp { 822 fsl,pins = < 823 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 824 >; 825 }; 826}; 827