1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Copyright 2020 Toradex 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/usb/pd.h> 9#include "imx8mm.dtsi" 10 11/ { 12 model = "Toradex Verdin iMX8M Mini Quad/DualLite"; 13 compatible = "toradex,verdin-imx8mm", "fsl,imx8mm"; 14 15 chosen { 16 stdout-path = &uart1; 17 }; 18 19 aliases { 20 eeprom0 = &eeprom_module; 21 eeprom1 = &eeprom_carrier_board; 22 eeprom2 = &eeprom_display_adapter; 23 }; 24 25 /* fixed clock dedicated to SPI CAN controller */ 26 clk20m: oscillator { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <20000000>; 30 }; 31 32 reg_ethphy: regulator-ethphy { 33 compatible = "regulator-fixed"; 34 enable-active-high; 35 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; 36 off-on-delay = <500000>; 37 pinctrl-names = "default"; 38 pinctrl-0 = <&pinctrl_reg_eth>; 39 regulator-boot-on; 40 regulator-max-microvolt = <3300000>; 41 regulator-min-microvolt = <3300000>; 42 regulator-name = "V3.3_ETH"; 43 startup-delay-us = <200000>; 44 }; 45 46 reg_usb_otg1_vbus: regulator-usb-otg1 { 47 compatible = "regulator-fixed"; 48 enable-active-high; 49 /* Verdin USB1_EN */ 50 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 51 pinctrl-names = "default"; 52 pinctrl-0 = <&pinctrl_reg_usb1_en>; 53 regulator-name = "usb_otg1_vbus"; 54 regulator-min-microvolt = <5000000>; 55 regulator-max-microvolt = <5000000>; 56 }; 57 58 reg_usb_otg2_vbus: regulator-usb-otg2 { 59 compatible = "regulator-fixed"; 60 enable-active-high; 61 /* Verdin USB2_EN */ 62 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; 63 pinctrl-names = "default"; 64 pinctrl-0 = <&pinctrl_reg_usb2_en>; 65 regulator-name = "usb_otg2_vbus"; 66 regulator-min-microvolt = <5000000>; 67 regulator-max-microvolt = <5000000>; 68 }; 69 70 reg_usdhc2_vmmc: regulator-usdhc2 { 71 compatible = "regulator-fixed"; 72 enable-active-high; 73 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; 74 pinctrl-names = "default"; 75 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; 76 regulator-name = "V3.3_SD"; 77 regulator-min-microvolt = <3300000>; 78 regulator-max-microvolt = <3300000>; 79 startup-delay-us = <2000>; 80 }; 81 82 reg_wifi_en: regulator-wifi-en { 83 compatible = "regulator-fixed"; 84 enable-active-high; 85 gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; 86 pinctrl-names = "default"; 87 pinctrl-0 = <&pinctrl_wifi_pwr_en>; 88 regulator-name = "V3.3_WI-FI"; 89 regulator-min-microvolt = <3300000>; 90 regulator-max-microvolt = <3300000>; 91 startup-delay-us = <2000>; 92 }; 93}; 94 95&A53_0 { 96 arm-supply = <&buck2_reg>; 97}; 98 99&clk { 100 assigned-clocks = <&clk IMX8MM_AUDIO_PLL1>, <&clk IMX8MM_AUDIO_PLL2>; 101 assigned-clock-rates = <786432000>, <722534400>; 102}; 103 104/* Verdin SPI_1 */ 105&ecspi2 { 106 #address-cells = <1>; 107 #size-cells = <0>; 108 pinctrl-names = "default"; 109 pinctrl-0 = <&pinctrl_ecspi2>; 110 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 111 status = "okay"; 112 113 spidev20: spidev@0 { 114 compatible = "toradex,evalspi"; 115 reg = <0>; 116 spi-max-frequency = <10000000>; 117 status = "okay"; 118 }; 119}; 120 121/* On-module CAN controller 1 & 2 */ 122&ecspi3 { 123 #address-cells = <1>; 124 #size-cells = <0>; 125 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>, 126 <&gpio1 5 GPIO_ACTIVE_LOW>; 127 /* This property is required, even if marked as obsolete in the doku */ 128 fsl,spi-num-chipselects = <2>; 129 pinctrl-names = "default"; 130 pinctrl-0 = <&pinctrl_ecspi3>; 131 status = "okay"; 132 133 can1: can@0 { 134 compatible = "microchip,mcp2517fd"; 135 clocks = <&clk20m>; 136 gpio-controller; 137 interrupt-parent = <&gpio1>; 138 interrupts = <6 IRQ_TYPE_EDGE_FALLING>; 139 microchip,clock-allways-on; 140 microchip,clock-out-div = <1>; 141 pinctrl-names = "default"; 142 pinctrl-0 = <&pinctrl_can1_int>; 143 reg = <0>; 144 spi-max-frequency = <2000000>; 145 }; 146 147 can2: can@1 { 148 compatible = "microchip,mcp2517fd"; 149 clocks = <&clk20m>; 150 gpio-controller; 151 interrupt-parent = <&gpio1>; 152 interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 153 pinctrl-names = "default"; 154 pinctrl-0 = <&pinctrl_can2_int>; 155 reg = <1>; 156 spi-max-frequency = <2000000>; 157 }; 158}; 159 160&fec1 { 161 fsl,magic-packet; 162 phy-handle = <ðphy0>; 163 phy-mode = "rgmii-id"; 164 phy-supply = <®_ethphy>; 165 pinctrl-names = "default", "sleep"; 166 pinctrl-0 = <&pinctrl_fec1>; 167 pinctrl-1 = <&pinctrl_fec1_sleep>; 168 status = "okay"; 169 170 mdio { 171 #address-cells = <1>; 172 #size-cells = <0>; 173 174 ethphy0: ethernet-phy@7 { 175 compatible = "ethernet-phy-ieee802.3-c22"; 176 interrupt-parent = <&gpio1>; 177 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 178 micrel,led-mode = <0>; 179 reg = <7>; 180 }; 181 }; 182}; 183 184&gpio4 { 185 /* 186 * The SE050 security element may be driven via I2C from user space. 187 * The element itself is enabled here as it has no kernel driver. 188 */ 189 se050_ena { 190 gpio-hog; 191 gpios = <19 GPIO_ACTIVE_HIGH>; 192 line-name = "SE050_ENABLE"; 193 output-high; 194 pinctrl-names = "default"; 195 pinctrl-0 = <&pinctrl_se050_ena>; 196 }; 197}; 198 199&gpio5 { 200 ctrl_sleep_moci { 201 gpio-hog; 202 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ 203 gpios = <1 GPIO_ACTIVE_HIGH>; 204 line-name = "CTRL_SLEEP_MOCI#"; 205 output-high; 206 pinctrl-names = "default"; 207 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; 208 }; 209}; 210 211/* On-module I2C */ 212&i2c1 { 213 clock-frequency = <400000>; 214 pinctrl-names = "default"; 215 pinctrl-0 = <&pinctrl_i2c1>; 216 status = "okay"; 217 218 /* Assembled on V1.1 HW and later */ 219 pmic { 220 reg = <0x25>; 221 u-boot,dm-spl; 222 compatible = "nxp,pca9450a"; 223 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ 224 pinctrl-0 = <&pinctrl_pmic>; 225 gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; 226 227 regulators { 228 u-boot,dm-spl; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 232 pca9450,pmic-buck2-uses-i2c-dvs; 233 /* Run/Standby voltage */ 234 pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; 235 236 buck1_reg: regulator@0 { 237 reg = <0>; 238 regulator-compatible = "buck1"; 239 regulator-min-microvolt = <600000>; 240 regulator-max-microvolt = <2187500>; 241 regulator-boot-on; 242 regulator-always-on; 243 regulator-ramp-delay = <3125>; 244 }; 245 246 buck2_reg: regulator@1 { 247 reg = <1>; 248 regulator-compatible = "buck2"; 249 regulator-min-microvolt = <600000>; 250 regulator-max-microvolt = <2187500>; 251 regulator-boot-on; 252 regulator-always-on; 253 regulator-ramp-delay = <3125>; 254 }; 255 256 buck3_reg: regulator@2 { 257 reg = <2>; 258 regulator-compatible = "buck3"; 259 regulator-min-microvolt = <600000>; 260 regulator-max-microvolt = <2187500>; 261 regulator-boot-on; 262 regulator-always-on; 263 }; 264 265 buck4_reg: regulator@3 { 266 reg = <3>; 267 regulator-compatible = "buck4"; 268 regulator-min-microvolt = <600000>; 269 regulator-max-microvolt = <3400000>; 270 regulator-boot-on; 271 regulator-always-on; 272 }; 273 274 buck5_reg: regulator@4 { 275 reg = <4>; 276 regulator-compatible = "buck5"; 277 regulator-min-microvolt = <600000>; 278 regulator-max-microvolt = <3400000>; 279 regulator-boot-on; 280 regulator-always-on; 281 }; 282 283 buck6_reg: regulator@5 { 284 reg = <5>; 285 regulator-compatible = "buck6"; 286 regulator-min-microvolt = <600000>; 287 regulator-max-microvolt = <3400000>; 288 regulator-boot-on; 289 regulator-always-on; 290 }; 291 292 ldo1_reg: regulator@6 { 293 reg = <6>; 294 regulator-compatible = "ldo1"; 295 regulator-min-microvolt = <1600000>; 296 regulator-max-microvolt = <3300000>; 297 regulator-boot-on; 298 regulator-always-on; 299 }; 300 301 ldo2_reg: regulator@7 { 302 reg = <7>; 303 regulator-compatible = "ldo2"; 304 regulator-min-microvolt = <800000>; 305 regulator-max-microvolt = <1150000>; 306 regulator-boot-on; 307 regulator-always-on; 308 }; 309 310 ldo3_reg: regulator@8 { 311 reg = <8>; 312 regulator-compatible = "ldo3"; 313 regulator-min-microvolt = <800000>; 314 regulator-max-microvolt = <3300000>; 315 regulator-boot-on; 316 regulator-always-on; 317 }; 318 319 ldo4_reg: regulator@9 { 320 reg = <9>; 321 regulator-compatible = "ldo4"; 322 regulator-min-microvolt = <800000>; 323 regulator-max-microvolt = <3300000>; 324 regulator-boot-on; 325 regulator-always-on; 326 }; 327 328 ldo5_reg: regulator@10 { 329 reg = <10>; 330 regulator-compatible = "ldo5"; 331 regulator-min-microvolt = <800000>; 332 regulator-max-microvolt = <3300000>; 333 }; 334 335 }; 336 }; 337 338 /* Epson RX8130 real time clock on carrier board */ 339 rtc@32 { 340 compatible = "epson,rx8130"; 341 reg = <0x32>; 342 }; 343 344 eeprom_module: eeprom@50 { 345 compatible = "st,24c02", "atmel,24c02", "i2c-eeprom"; 346 pagesize = <16>; 347 reg = <0x50>; 348 }; 349}; 350 351/* Verdin I2C_2_DSI */ 352&i2c2 { 353 clock-frequency = <10000>; 354 pinctrl-names = "default"; 355 pinctrl-0 = <&pinctrl_i2c2>; 356 status = "okay"; 357}; 358 359/* Verdin I2C_3_HDMI N/A */ 360 361/* Verdin I2C_4_CSI */ 362&i2c3 { 363 clock-frequency = <400000>; 364 pinctrl-names = "default"; 365 pinctrl-0 = <&pinctrl_i2c3>; 366 status = "okay"; 367}; 368 369/* Verdin I2C_1 */ 370&i2c4 { 371 clock-frequency = <400000>; 372 pinctrl-names = "default"; 373 pinctrl-0 = <&pinctrl_i2c4>; 374 status = "okay"; 375 376 /* Audio Codec */ 377 wm8904_1a: codec@1a { 378 compatible = "wlf,wm8904"; 379 #sound-dai-cells = <0>; 380 clocks = <&clk IMX8MM_CLK_SAI2_ROOT>; 381 clock-names = "mclk"; 382 reg = <0x1a>; 383 }; 384 385 gpio_expander_21: gpio-expander@21 { 386 compatible = "nxp,pcal6416"; 387 #gpio-cells = <2>; 388 gpio-controller; 389 reg = <0x21>; 390 }; 391 392 /* Current measurement into module VCC */ 393 hwmon@40 { 394 compatible = "ti,ina219"; 395 reg = <0x40>; 396 shunt-resistor = <10000>; 397 status = "okay"; 398 }; 399 400 /* EEPROM on display adapter (MIPI DSI Display Adapter) */ 401 eeprom_display_adapter: eeprom@50 { 402 compatible = "st,24c02", "atmel,24c02", "i2c-eeprom"; 403 pagesize = <16>; 404 reg = <0x50>; 405 }; 406 407 /* EEPROM on carrier board */ 408 eeprom_carrier_board: eeprom@57 { 409 compatible = "st,24c02", "atmel,24c02", "i2c-eeprom"; 410 pagesize = <16>; 411 reg = <0x57>; 412 }; 413}; 414 415/* Verdin PWM_3_DSI */ 416&pwm1 { 417 pinctrl-names = "default"; 418 pinctrl-0 = <&pinctrl_pwm_1>; 419 #pwm-cells = <3>; 420 status = "okay"; 421}; 422 423/* Verdin PWM_1 */ 424&pwm2 { 425 pinctrl-names = "default"; 426 pinctrl-0 = <&pinctrl_pwm_2>; 427 #pwm-cells = <3>; 428 status = "okay"; 429}; 430 431/* Verdin PWM_2 */ 432&pwm3 { 433 pinctrl-names = "default"; 434 pinctrl-0 = <&pinctrl_pwm_3>; 435 #pwm-cells = <3>; 436 status = "okay"; 437}; 438 439/* Verdin UART_3, Console/Debug UART */ 440&uart1 { 441 fsl,uart-has-rtscts; 442 pinctrl-names = "default"; 443 pinctrl-0 = <&pinctrl_uart1>; 444 status = "okay"; 445}; 446 447/* Verdin UART_1 */ 448&uart2 { 449 pinctrl-names = "default"; 450 pinctrl-0 = <&pinctrl_uart2>; 451 fsl,uart-has-rtscts; 452 status = "okay"; 453}; 454 455/* Verdin UART_2 */ 456&uart3 { 457 pinctrl-names = "default"; 458 pinctrl-0 = <&pinctrl_uart3>; 459 fsl,uart-has-rtscts; 460 status = "okay"; 461}; 462 463/* Verdin UART_4 */ 464/* 465 * resource allocated to M4 by default, must not be accessed from A-35 or you 466 * get an OOPS 467 */ 468&uart4 { 469 pinctrl-names = "default"; 470 pinctrl-0 = <&pinctrl_uart4>; 471 status = "disabled"; 472}; 473 474/* Verdin USB_1 */ 475&usbotg1 { 476 dr_mode = "otg"; 477 picophy,dc-vol-level-adjust = <7>; 478 picophy,pre-emp-curr-control = <3>; 479 vbus-supply = <®_usb_otg1_vbus>; 480 status = "okay"; 481}; 482 483/* Verdin USB_2 */ 484&usbotg2 { 485 dr_mode = "host"; 486 picophy,dc-vol-level-adjust = <7>; 487 picophy,pre-emp-curr-control = <3>; 488 vbus-supply = <®_usb_otg2_vbus>; 489 status = "okay"; 490}; 491 492/* On-module eMMC */ 493&usdhc1 { 494 bus-width = <8>; 495 keep-power-in-suspend; 496 non-removable; 497 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 498 pinctrl-0 = <&pinctrl_usdhc1>; 499 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 500 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 501 pm-ignore-notify; 502 status = "okay"; 503 /* TODO Strobe */ 504}; 505 506/* Verdin SD_1 */ 507&usdhc2 { 508 bus-width = <4>; 509 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 510 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 511 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; 512 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 513 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 514 vmmc-supply = <®_usdhc2_vmmc>; 515 status = "okay"; 516}; 517 518/* On-module Wi-Fi */ 519&usdhc3 { 520 bus-width = <4>; 521 non-removable; 522 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 523 pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>; 524 pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>; 525 pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>; 526 vmmc-supply = <®_wifi_en>; 527 status = "okay"; 528}; 529 530&wdog1 { 531 fsl,ext-reset-output; 532 pinctrl-names = "default"; 533 pinctrl-0 = <&pinctrl_wdog>; 534 status = "okay"; 535}; 536 537&iomuxc { 538 pinctrl-names = "default"; 539 pinctrl-0 = <&pinctrl_dsi_bkl_en>, <&pinctrl_gpio1>, <&pinctrl_gpio2>, 540 <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio5>, 541 <&pinctrl_gpio6>, <&pinctrl_gpio7>, <&pinctrl_gpio8>, 542 <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, 543 <&pinctrl_gpio_hog3>, <&pinctrl_gpio_hpd>; 544 545 pinctrl_can1_int: can1intgrp { 546 fsl,pins = < 547 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x1c4 548 >; 549 }; 550 551 pinctrl_can2_int: can2intgrp { 552 fsl,pins = < 553 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x1c4 554 >; 555 }; 556 557 pinctrl_ctrl_force_off_moci: ctrlforceoffgrp { 558 fsl,pins = < 559 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1c4 /* SODIMM 250 */ 560 >; 561 }; 562 563 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { 564 fsl,pins = < 565 MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1c4 /* SODIMM 256 */ 566 >; 567 }; 568 569 pinctrl_dsi_bkl_en: dsi_bkl_en { 570 fsl,pins = < 571 MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x1c4 /* SODIMM 21 */ 572 >; 573 }; 574 575 pinctrl_ecspi2: ecspi2grp { 576 fsl,pins = < 577 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x1c4 /* SODIMM 198 */ 578 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x4 /* SODIMM 200 */ 579 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x4 /* SODIMM 196 */ 580 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x1c4 /* SODIMM 202 */ 581 >; 582 }; 583 584 pinctrl_ecspi3: ecspi3grp { 585 fsl,pins = < 586 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x1c4 587 MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x4 588 MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x4 589 MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x1c4 590 MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x1c4 591 >; 592 }; 593 594 pinctrl_fec1: fec1grp { 595 fsl,pins = < 596 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 597 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 598 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 599 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 600 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 601 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 602 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 603 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 604 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 605 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 606 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 607 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 608 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 609 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 610 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x1c4 611 >; 612 }; 613 614 pinctrl_fec1_sleep: fec1-sleepgrp { 615 fsl,pins = < 616 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 617 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 618 MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f 619 MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f 620 MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f 621 MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f 622 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 623 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 624 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 625 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 626 MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f 627 MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f 628 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 629 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 630 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x184 631 >; 632 }; 633 634 pinctrl_flexspi0: flexspi0grp { 635 fsl,pins = < 636 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 /* SODIMM 52 */ 637 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 /* SODIMM 54 */ 638 MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x82 /* SODIMM 64 */ 639 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 /* SODIMM 56 */ 640 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 /* SODIMM 58 */ 641 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 /* SODIMM 60 */ 642 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 /* SODIMM 62 */ 643 MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x82 /* SODIMM 66 */ 644 >; 645 }; 646 647 /* (MEZ_)GPIO_1 shared with (MEZ_)DSI_1_INT# on Verdin Development Board */ 648 pinctrl_gpio1: gpio1grp { 649 fsl,pins = < 650 MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x184 /* SODIMM 206 */ 651 >; 652 }; 653 654 pinctrl_gpio2: gpio2grp { 655 fsl,pins = < 656 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x184 /* SODIMM 208 */ 657 >; 658 }; 659 660 pinctrl_gpio3: gpio3grp { 661 fsl,pins = < 662 MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x184 /* SODIMM 210 */ 663 >; 664 }; 665 666 pinctrl_gpio4: gpio4grp { 667 fsl,pins = < 668 MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x184 /* SODIMM 212 */ 669 >; 670 }; 671 672 pinctrl_gpio5: gpio5grp { 673 fsl,pins = < 674 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x184 /* SODIMM 216 */ 675 >; 676 }; 677 678 pinctrl_gpio6: gpio6grp { 679 fsl,pins = < 680 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x184 /* SODIMM 218 */ 681 >; 682 }; 683 684 pinctrl_gpio7: gpio7grp { 685 fsl,pins = < 686 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x184 /* SODIMM 220 */ 687 >; 688 }; 689 690 pinctrl_gpio8: gpio8grp { 691 fsl,pins = < 692 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184 /* SODIMM 222 */ 693 >; 694 }; 695 696 pinctrl_gpio_hog1: gpiohog1grp { 697 fsl,pins = < 698 MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4 /* SODIMM 88 */ 699 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4 /* SODIMM 90 */ 700 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4 /* SODIMM 92 */ 701 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4 /* SODIMM 94 */ 702 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4 /* SODIMM 96 */ 703 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4 /* SODIMM 100 */ 704 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4 /* SODIMM 102 */ 705 MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4 /* SODIMM 104 */ 706 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4 /* SODIMM 106 */ 707 MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4 /* SODIMM 108 */ 708 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4 /* SODIMM 112 */ 709 MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4 /* SODIMM 114 */ 710 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4 /* SODIMM 116 */ 711 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4 /* SODIMM 118 */ 712 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4 /* SODIMM 120 */ 713 >; 714 }; 715 716 pinctrl_gpio_hog2: gpiohog2grp { 717 fsl,pins = < 718 MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1c4 /* SODIMM 91 */ 719 >; 720 }; 721 722 pinctrl_gpio_hog3: gpiohog3grp { 723 fsl,pins = < 724 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x1c4 /* SODIMM 157 */ 725 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 /* SODIMM 187 */ 726 >; 727 }; 728 729 /* (MEZ_)DSI_1_INT# shared with (MEZ_)GPIO_1 on Verdin Development Board */ 730 pinctrl_gpio_hpd: gpiohpdgrp { 731 fsl,pins = < 732 MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x184 /* SODIMM 17 */ 733 >; 734 }; 735 736 /* On-module I2C */ 737 pinctrl_i2c1: i2c1grp { 738 fsl,pins = < 739 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c6 740 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c6 741 >; 742 }; 743 744 /* Verdin I2C_4_CSI */ 745 pinctrl_i2c2: i2c2grp { 746 fsl,pins = < 747 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c6 /* SODIMM 55 */ 748 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c6 /* SODIMM 53 */ 749 >; 750 }; 751 752 /* Verdin I2C_2_DSI */ 753 pinctrl_i2c3: i2c3grp { 754 fsl,pins = < 755 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c6 /* SODIMM 95 */ 756 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c6 /* SODIMM 93 */ 757 >; 758 }; 759 760 /* Verdin I2C_1 */ 761 pinctrl_i2c4: i2c4grp { 762 fsl,pins = < 763 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c6 /* SODIMM 14 */ 764 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c6 /* SODIMM 12 */ 765 >; 766 }; 767 768 pinctrl_pcie0: pcie0grp { 769 fsl,pins = < 770 MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6 /* SODIMM 244 */ 771 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6 /* PMIC_EN_PCIe_CLK */ 772 >; 773 }; 774 775 pinctrl_pmic: pmicirqgrp { 776 fsl,pins = < 777 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 778 >; 779 }; 780 781 pinctrl_pwm_1: pwm1grp { 782 fsl,pins = < 783 MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6 /* SODIMM 19 */ 784 >; 785 }; 786 787 pinctrl_pwm_2: pwm2grp { 788 fsl,pins = < 789 MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6 /* SODIMM 15 */ 790 >; 791 }; 792 793 pinctrl_pwm_3: pwm3grp { 794 fsl,pins = < 795 MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6 /* SODIMM 16 */ 796 >; 797 }; 798 799 pinctrl_reg_eth: regethgrp { 800 fsl,pins = < 801 MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x184 802 >; 803 }; 804 805 pinctrl_reg_usb1_en: regusb1engrp { 806 fsl,pins = < 807 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x184 /* SODIMM 155 */ 808 >; 809 }; 810 811 pinctrl_reg_usb2_en: regusb2engrp { 812 fsl,pins = < 813 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x184 /* SODIMM 185 */ 814 >; 815 }; 816 817 pinctrl_sai2: sai2grp { 818 fsl,pins = < 819 MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 /* SODIMM 38 */ 820 MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 /* SODIMM 36 */ 821 MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 /* SODIMM 30 */ 822 MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 /* SODIMM 34 */ 823 MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 /* SODIMM 32 */ 824 >; 825 }; 826 827 pinctrl_sai5: sai5grp { 828 fsl,pins = < 829 MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 /* SODIMM 48 */ 830 MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 /* SODIMM 44 */ 831 MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 /* SODIMM 42 */ 832 MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 /* SODIMM 46 */ 833 >; 834 }; 835 836 pinctrl_se050_ena: se050enagrp { 837 fsl,pins = < 838 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x184 839 >; 840 }; 841 842 pinctrl_uart1: uart1grp { 843 fsl,pins = < 844 MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1c4 /* SODIMM 147 */ 845 MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1c4 /* SODIMM 149 */ 846 >; 847 }; 848 849 pinctrl_uart2: uart2grp { 850 fsl,pins = < 851 MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1c4 /* SODIMM 133 */ 852 MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1c4 /* SODIMM 135 */ 853 MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1c4 /* SODIMM 131 */ 854 MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1c4 /* SODIMM 129 */ 855 >; 856 }; 857 858 pinctrl_uart3: uart3grp { 859 fsl,pins = < 860 MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1c4 /* SODIMM 141 */ 861 MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1c4 /* SODIMM 139 */ 862 MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1c4 /* SODIMM 137 */ 863 MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x1c4 /* SODIMM 143 */ 864 >; 865 }; 866 867 pinctrl_uart4: uart4grp { 868 fsl,pins = < 869 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x1c4 /* SODIMM 151 */ 870 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x1c4 /* SODIMM 153 */ 871 >; 872 }; 873 874 pinctrl_usdhc1: usdhc1grp { 875 fsl,pins = < 876 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 877 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 878 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 879 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 880 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 881 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 882 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 883 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 884 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 885 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 886 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190 887 >; 888 }; 889 890 pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 891 fsl,pins = < 892 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 893 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 894 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 895 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 896 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 897 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 898 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 899 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 900 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 901 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 902 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194 903 >; 904 }; 905 906 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 907 fsl,pins = < 908 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 909 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 910 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 911 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 912 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 913 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 914 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 915 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 916 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 917 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 918 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 919 >; 920 }; 921 922 pinctrl_usdhc2_cd: usdhc2cdgrp { 923 fsl,pins = < 924 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 /* SODIMM 84 */ 925 >; 926 }; 927 928 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { 929 fsl,pins = < 930 MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x184 /* SODIMM 76 */ 931 >; 932 }; 933 934 pinctrl_usdhc2: usdhc2grp { 935 fsl,pins = < 936 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 937 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 /* SODIMM 78 */ 938 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 /* SODIMM 74 */ 939 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 /* SODIMM 80 */ 940 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 /* SODIMM 82 */ 941 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 /* SODIMM 70 */ 942 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 /* SODIMM 72 */ 943 >; 944 }; 945 946 pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 947 fsl,pins = < 948 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 949 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 950 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 951 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 952 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 953 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 954 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 955 >; 956 }; 957 958 pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 959 fsl,pins = < 960 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 961 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 962 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 963 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 964 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 965 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 966 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 967 >; 968 }; 969 970 pinctrl_usdhc3: usdhc3grp { 971 fsl,pins = < 972 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 973 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 974 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 975 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 976 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 977 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 978 >; 979 }; 980 981 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 982 fsl,pins = < 983 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 984 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 985 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 986 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 987 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 988 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 989 >; 990 }; 991 992 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 993 fsl,pins = < 994 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 995 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 996 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 997 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 998 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 999 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 1000 >; 1001 }; 1002 1003 pinctrl_wdog: wdoggrp { 1004 fsl,pins = < 1005 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 1006 >; 1007 }; 1008 1009 pinctrl_wifi_ctrl: wifictrlgrp { 1010 fsl,pins = < 1011 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x1c4 /* WIFI_WKUP_BT */ 1012 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x1c4 /* WIFI_W_WKUP_HOST */ 1013 MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x1c4 /* WIFI_WKUP_WLAN */ 1014 >; 1015 }; 1016 1017 pinctrl_wifi_i2s: wifii2sgrp { 1018 fsl,pins = < 1019 MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0xd6 1020 MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0xd6 1021 MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0xd6 1022 MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0xd6 1023 >; 1024 }; 1025 1026 pinctrl_wifi_pwr_en: wifipwrengrp { 1027 fsl,pins = < 1028 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x184 /* PMIC_EN_WIFI */ 1029 >; 1030 }; 1031}; 1032