1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 NXP
4 */
5
6#include "imx8mp-u-boot.dtsi"
7
8/ {
9	wdt-reboot {
10		compatible = "wdt-reboot";
11		wdt = <&wdog1>;
12		u-boot,dm-spl;
13	};
14	firmware {
15		optee {
16			compatible = "linaro,optee-tz";
17			method = "smc";
18		};
19	};
20};
21
22&reg_usdhc2_vmmc {
23	u-boot,off-on-delay-us = <20000>;
24};
25
26&reg_usdhc2_vmmc {
27	u-boot,dm-spl;
28};
29
30&pinctrl_uart2 {
31	u-boot,dm-spl;
32};
33
34&pinctrl_usdhc2_gpio {
35	u-boot,dm-spl;
36};
37
38&pinctrl_usdhc2 {
39	u-boot,dm-spl;
40};
41
42&pinctrl_usdhc3 {
43	u-boot,dm-spl;
44};
45
46&gpio1 {
47	u-boot,dm-spl;
48};
49
50&gpio2 {
51	u-boot,dm-spl;
52};
53
54&gpio3 {
55	u-boot,dm-spl;
56};
57
58&gpio4 {
59	u-boot,dm-spl;
60};
61
62&gpio5 {
63	u-boot,dm-spl;
64};
65
66&uart2 {
67	u-boot,dm-spl;
68};
69
70&i2c1 {
71	u-boot,dm-spl;
72};
73
74&i2c2 {
75	u-boot,dm-spl;
76};
77
78&i2c3 {
79	u-boot,dm-spl;
80};
81
82&i2c4 {
83	u-boot,dm-spl;
84};
85
86&i2c5 {
87	u-boot,dm-spl;
88};
89
90&i2c6 {
91	u-boot,dm-spl;
92};
93
94&usdhc1 {
95	u-boot,dm-spl;
96};
97
98&usdhc2 {
99	u-boot,dm-spl;
100	sd-uhs-sdr104;
101	sd-uhs-ddr50;
102};
103
104&usdhc3 {
105	u-boot,dm-spl;
106	mmc-hs400-1_8v;
107	mmc-hs400-enhanced-strobe;
108};
109
110&wdog1 {
111	u-boot,dm-spl;
112};
113
114&eqos {
115	compatible = "fsl,imx-eqos";
116	/delete-property/ assigned-clocks;
117	/delete-property/ assigned-clock-parents;
118	/delete-property/ assigned-clock-rates;
119};
120
121&ethphy0 {
122	reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
123	reset-delay-us = <15000>;
124	reset-post-delay-us = <100000>;
125};
126
127&fec {
128	phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
129	phy-reset-duration = <15>;
130	phy-reset-post-delay = <100>;
131};
132
133
134