1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8mp.dtsi"
9
10/ {
11	model = "NXP i.MX8MPlus EVK board";
12	compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
13
14	chosen {
15		stdout-path = &uart2;
16	};
17
18	gpio-leds {
19		compatible = "gpio-leds";
20		pinctrl-names = "default";
21		pinctrl-0 = <&pinctrl_gpio_led>;
22
23		status {
24			label = "yellow:status";
25			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
26			default-state = "on";
27		};
28	};
29
30	memory@40000000 {
31		device_type = "memory";
32		reg = <0x0 0x40000000 0 0xc0000000>,
33		      <0x1 0x00000000 0 0xc0000000>;
34	};
35
36	reg_can1_stby: regulator-can1-stby {
37		compatible = "regulator-fixed";
38		regulator-name = "can1-stby";
39		pinctrl-names = "default";
40		pinctrl-0 = <&pinctrl_flexcan1_reg>;
41		regulator-min-microvolt = <3300000>;
42		regulator-max-microvolt = <3300000>;
43		gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
44		enable-active-high;
45	};
46
47	reg_can2_stby: regulator-can2-stby {
48		compatible = "regulator-fixed";
49		regulator-name = "can2-stby";
50		pinctrl-names = "default";
51		pinctrl-0 = <&pinctrl_flexcan2_reg>;
52		regulator-min-microvolt = <3300000>;
53		regulator-max-microvolt = <3300000>;
54		gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
55		enable-active-high;
56	};
57
58	reg_usdhc2_vmmc: regulator-usdhc2 {
59		compatible = "regulator-fixed";
60		pinctrl-names = "default";
61		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
62		regulator-name = "VSD_3V3";
63		regulator-min-microvolt = <3300000>;
64		regulator-max-microvolt = <3300000>;
65		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
66		enable-active-high;
67	};
68};
69
70&flexcan1 {
71	pinctrl-names = "default";
72	pinctrl-0 = <&pinctrl_flexcan1>;
73	xceiver-supply = <&reg_can1_stby>;
74	status = "okay";
75};
76
77&eqos {
78	pinctrl-names = "default";
79	pinctrl-0 = <&pinctrl_eqos>;
80	phy-mode = "rgmii-id";
81	phy-handle = <&ethphy0>;
82	status = "okay";
83
84	mdio {
85		compatible = "snps,dwmac-mdio";
86		#address-cells = <1>;
87		#size-cells = <0>;
88
89		ethphy0: ethernet-phy@1 {
90			compatible = "ethernet-phy-ieee802.3-c22";
91			reg = <1>;
92			eee-broken-1000t;
93		};
94	};
95};
96
97&flexcan2 {
98	pinctrl-names = "default";
99	pinctrl-0 = <&pinctrl_flexcan2>;
100	xceiver-supply = <&reg_can2_stby>;
101	status = "disabled";/* can2 pin conflict with pdm */
102};
103
104&fec {
105	pinctrl-names = "default";
106	pinctrl-0 = <&pinctrl_fec>;
107	phy-mode = "rgmii-id";
108	phy-handle = <&ethphy1>;
109	fsl,magic-packet;
110	status = "okay";
111
112	mdio {
113		#address-cells = <1>;
114		#size-cells = <0>;
115
116		ethphy1: ethernet-phy@1 {
117			compatible = "ethernet-phy-ieee802.3-c22";
118			reg = <1>;
119			eee-broken-1000t;
120			reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
121		};
122	};
123};
124
125&i2c3 {
126	clock-frequency = <400000>;
127	pinctrl-names = "default";
128	pinctrl-0 = <&pinctrl_i2c3>;
129	status = "okay";
130
131	pca6416: gpio@20 {
132		compatible = "ti,tca6416";
133		reg = <0x20>;
134		gpio-controller;
135		#gpio-cells = <2>;
136	};
137};
138
139&snvs_pwrkey {
140	status = "okay";
141};
142
143&uart2 {
144	/* console */
145	pinctrl-names = "default";
146	pinctrl-0 = <&pinctrl_uart2>;
147	status = "okay";
148};
149
150&usdhc2 {
151	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
152	assigned-clock-rates = <400000000>;
153	pinctrl-names = "default", "state_100mhz", "state_200mhz";
154	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
155	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
156	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
157	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
158	vmmc-supply = <&reg_usdhc2_vmmc>;
159	bus-width = <4>;
160	status = "okay";
161};
162
163&usdhc3 {
164	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
165	assigned-clock-rates = <400000000>;
166	pinctrl-names = "default", "state_100mhz", "state_200mhz";
167	pinctrl-0 = <&pinctrl_usdhc3>;
168	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
169	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
170	bus-width = <8>;
171	non-removable;
172	status = "okay";
173};
174
175&wdog1 {
176	pinctrl-names = "default";
177	pinctrl-0 = <&pinctrl_wdog>;
178	fsl,ext-reset-output;
179	status = "okay";
180};
181
182&iomuxc {
183	pinctrl_eqos: eqosgrp {
184		fsl,pins = <
185			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC	0x3
186			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO	0x3
187			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91
188			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91
189			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2	0x91
190			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3	0x91
191			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
192			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91
193			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x1f
194			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x1f
195			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x1f
196			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x1f
197			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f
198			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
199			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22		0x19
200		>;
201	};
202
203	pinctrl_fec: fecgrp {
204		fsl,pins = <
205			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
206			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
207			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
208			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
209			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
210			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
211			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
212			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
213			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
214			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
215			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
216			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
217			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
218			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
219			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x19
220		>;
221	};
222
223	pinctrl_flexcan1: flexcan1grp {
224		fsl,pins = <
225			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX          0x154
226			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX          0x154
227		>;
228	};
229
230	pinctrl_flexcan2: flexcan2grp {
231		fsl,pins = <
232			MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX         0x154
233			MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX         0x154
234		>;
235	};
236
237	pinctrl_flexcan1_reg: flexcan1reggrp {
238		fsl,pins = <
239			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05  0x154   /* CAN1_STBY */
240		>;
241	};
242
243	pinctrl_flexcan2_reg: flexcan2reggrp {
244		fsl,pins = <
245			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27      0x154   /* CAN2_STBY */
246		>;
247	};
248
249	pinctrl_gpio_led: gpioledgrp {
250		fsl,pins = <
251			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x19
252		>;
253	};
254
255	pinctrl_i2c3: i2c3grp {
256		fsl,pins = <
257			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c3
258			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c3
259		>;
260	};
261
262	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
263		fsl,pins = <
264			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x41
265		>;
266	};
267
268	pinctrl_uart2: uart2grp {
269		fsl,pins = <
270			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x49
271			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x49
272		>;
273	};
274
275	pinctrl_usdhc2: usdhc2grp {
276		fsl,pins = <
277			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
278			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0
279			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0
280			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0
281			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0
282			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0
283			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1
284		>;
285	};
286
287	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
288		fsl,pins = <
289			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194
290			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4
291			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4
292			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4
293			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4
294			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4
295			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
296		>;
297	};
298
299	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
300		fsl,pins = <
301			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196
302			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6
303			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6
304			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6
305			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6
306			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6
307			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
308		>;
309	};
310
311	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
312		fsl,pins = <
313			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x1c4
314		>;
315	};
316
317	pinctrl_usdhc3: usdhc3grp {
318		fsl,pins = <
319			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190
320			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0
321			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0
322			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0
323			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0
324			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0
325			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0
326			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0
327			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0
328			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0
329			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190
330		>;
331	};
332
333	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
334		fsl,pins = <
335			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194
336			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4
337			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4
338			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4
339			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4
340			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4
341			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4
342			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4
343			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4
344			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4
345			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194
346		>;
347	};
348
349	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
350		fsl,pins = <
351			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
352			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
353			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6
354			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6
355			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6
356			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6
357			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6
358			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6
359			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6
360			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6
361			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
362		>;
363	};
364
365	pinctrl_wdog: wdoggrp {
366		fsl,pins = <
367			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0x166
368		>;
369	};
370};
371