1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright 2021 NXP 4 */ 5 6/dts-v1/; 7 8#include "imx8ulp.dtsi" 9 10/ { 11 model = "FSL i.MX8ULP EVK"; 12 compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp"; 13 14 chosen { 15 stdout-path = &lpuart5; 16 bootargs = "console=ttyLP1,115200 earlycon"; 17 }; 18 19 usdhc2_pwrseq: usdhc2_pwrseq { 20 compatible = "mmc-pwrseq-simple"; 21 reset-gpios = <&pcal6408 2 GPIO_ACTIVE_LOW>; 22 }; 23}; 24 25&lpuart5 { 26 /* console */ 27 pinctrl-names = "default", "sleep"; 28 pinctrl-0 = <&pinctrl_lpuart5>; 29 pinctrl-1 = <&pinctrl_lpuart5>; 30 status = "okay"; 31}; 32 33&iomuxc1 { 34 pinctrl_lpuart5: lpuart5grp { 35 fsl,pins = < 36 MX8ULP_PAD_PTF14__LPUART5_TX 0x03 37 MX8ULP_PAD_PTF15__LPUART5_RX 0x03 38 >; 39 }; 40 41 pinctrl_lpi2c7: lpi2c7grp { 42 fsl,pins = < 43 MX8ULP_PAD_PTE12__LPI2C7_SCL 0x27 44 MX8ULP_PAD_PTE13__LPI2C7_SDA 0x27 45 >; 46 }; 47 48 pinctrl_usdhc0: usdhc0grp { 49 fsl,pins = < 50 MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x43 51 MX8ULP_PAD_PTD1__SDHC0_CMD 0x43 52 MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042 53 MX8ULP_PAD_PTD10__SDHC0_D0 0x43 54 MX8ULP_PAD_PTD9__SDHC0_D1 0x43 55 MX8ULP_PAD_PTD8__SDHC0_D2 0x43 56 MX8ULP_PAD_PTD7__SDHC0_D3 0x43 57 MX8ULP_PAD_PTD6__SDHC0_D4 0x43 58 MX8ULP_PAD_PTD5__SDHC0_D5 0x43 59 MX8ULP_PAD_PTD4__SDHC0_D6 0x43 60 MX8ULP_PAD_PTD3__SDHC0_D7 0x43 61 MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042 62 >; 63 }; 64 65 pinctrl_usdhc2_pte: usdhc2ptegrp { 66 fsl,pins = < 67 MX8ULP_PAD_PTE1__SDHC2_D0 0x43 68 MX8ULP_PAD_PTE0__SDHC2_D1 0x43 69 MX8ULP_PAD_PTE5__SDHC2_D2 0x43 70 MX8ULP_PAD_PTE4__SDHC2_D3 0x43 71 MX8ULP_PAD_PTE2__SDHC2_CLK 0x10042 72 MX8ULP_PAD_PTE3__SDHC2_CMD 0x43 73 MX8ULP_PAD_PTE7__PTE7 0x10003 74 >; 75 }; 76 77 pinctrl_fec: fecgrp { 78 fsl,pins = < 79 MX8ULP_PAD_PTE14__ENET0_MDIO 0x43 80 MX8ULP_PAD_PTE15__ENET0_MDC 0x43 81 MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43 82 MX8ULP_PAD_PTE17__ENET0_RXER 0x43 83 MX8ULP_PAD_PTF1__ENET0_RXD0 0x43 84 MX8ULP_PAD_PTE20__ENET0_RXD1 0x43 85 MX8ULP_PAD_PTE16__ENET0_TXEN 0x43 86 MX8ULP_PAD_PTE23__ENET0_TXD0 0x43 87 MX8ULP_PAD_PTE22__ENET0_TXD1 0x43 88 MX8ULP_PAD_PTE19__ENET0_REFCLK 0x10043 89 MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x10043 90 >; 91 }; 92 93 pinctrl_usbotg0_id: otg0idgrp { 94 fsl,pins = < 95 MX8ULP_PAD_PTF2__USB0_ID 0x10003 96 >; 97 }; 98 99 pinctrl_usbotg1_id: otg1idgrp { 100 fsl,pins = < 101 MX8ULP_PAD_PTD23__USB1_ID 0x10003 102 >; 103 }; 104}; 105 106&usdhc0 { 107 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 108 pinctrl-0 = <&pinctrl_usdhc0>; 109 pinctrl-1 = <&pinctrl_usdhc0>; 110 pinctrl-2 = <&pinctrl_usdhc0>; 111 bus-width = <8>; 112 non-removable; 113 status = "okay"; 114}; 115 116&usdhc2 { 117 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 118 pinctrl-0 = <&pinctrl_usdhc2_pte>; 119 pinctrl-1 = <&pinctrl_usdhc2_pte>; 120 pinctrl-2 = <&pinctrl_usdhc2_pte>; 121 pinctrl-3 = <&pinctrl_usdhc2_pte>; 122 mmc-pwrseq = <&usdhc2_pwrseq>; 123 max-frequency = <100000000>; 124 bus-width = <4>; 125 keep-power-in-suspend; 126 non-removable; 127 wakeup-source; 128 status = "okay"; 129 130 wifi_wake_host { 131 compatible = "nxp,wifi-wake-host"; 132 interrupt-parent = <&gpioe>; 133 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 134 interrupt-names = "host-wake"; 135 }; 136}; 137 138&lpi2c7 { 139 #address-cells = <1>; 140 #size-cells = <0>; 141 clock-frequency = <100000>; 142 pinctrl-names = "default"; 143 pinctrl-0 = <&pinctrl_lpi2c7>; 144 status = "okay"; 145 146 pcal6408: gpio@21 { 147 compatible = "ti,tca6408"; 148 reg = <0x21>; 149 gpio-controller; 150 #gpio-cells = <2>; 151 }; 152}; 153 154&flexspi0 { 155 status = "okay"; 156 157 flash0: atxp032@0 { 158 reg = <0>; 159 #address-cells = <1>; 160 #size-cells = <1>; 161 compatible = "jedec,spi-nor"; 162 spi-max-frequency = <66000000>; 163 }; 164}; 165 166&flexspi2 { 167 status = "okay"; 168 169 flash1: mt35xu512aba@0 { 170 reg = <0>; 171 #address-cells = <1>; 172 #size-cells = <1>; 173 compatible = "jedec,spi-nor"; 174 spi-max-frequency = <29000000>; 175 spi-nor,ddr-quad-read-dummy = <8>; 176 }; 177}; 178 179&fec { 180 pinctrl-names = "default"; 181 pinctrl-0 = <&pinctrl_fec>; 182 phy-mode = "rmii"; 183 phy-handle = <ðphy>; 184 status = "okay"; 185 186 phy-reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>; 187 188 mdio { 189 #address-cells = <1>; 190 #size-cells = <0>; 191 192 ethphy: ethernet-phy@1 { 193 reg = <1>; 194 micrel,led-mode = <1>; 195 }; 196 }; 197}; 198 199&usbotg0 { 200 pinctrl-names = "default"; 201 pinctrl-0 = <&pinctrl_usbotg0_id>; 202 srp-disable; 203 hnp-disable; 204 adp-disable; 205 status = "okay"; 206}; 207 208&usbphy0 { 209 fsl,tx-d-cal = <88>; 210}; 211 212&usbotg1 { 213 pinctrl-names = "default"; 214 pinctrl-0 = <&pinctrl_usbotg1_id>; 215 srp-disable; 216 hnp-disable; 217 adp-disable; 218 status = "okay"; 219}; 220 221&usbphy1 { 222 fsl,tx-d-cal = <88>; 223}; 224