1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/net/ti-dp83867.h>
10#include "imx8mm.dtsi"
11
12/ {
13	model = "PHYTEC phyCORE-i.MX8MM";
14	compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm";
15
16	chosen {
17		stdout-path = &uart3;
18	};
19
20	reg_usdhc2_vmmc: regulator-usdhc2 {
21		compatible = "regulator-fixed";
22		regulator-name = "VSD_3V3";
23		regulator-min-microvolt = <3300000>;
24		regulator-max-microvolt = <3300000>;
25		startup-delay-us = <100>;
26		off-on-delay-us = <12000>;
27	};
28};
29
30/* ethernet */
31&fec1 {
32	pinctrl-names = "default";
33	pinctrl-0 = <&pinctrl_fec1>;
34	phy-mode = "rgmii-id";
35	phy-handle = <&ethphy0>;
36	phy-reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
37	phy-reset-duration = <1>;
38	phy-reset-post-delay = <1>;
39	status = "okay";
40
41	mdio {
42		#address-cells = <1>;
43		#size-cells = <0>;
44
45		ethphy0: ethernet-phy@0 {
46			compatible = "ethernet-phy-ieee802.3-c22";
47			reg = <0x0>;
48			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
49			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
50			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
51			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
52			enet-phy-lane-no-swap;
53		};
54	};
55};
56
57/* SPI nor flash */
58&flexspi {
59	pinctrl-names = "default";
60	pinctrl-0 = <&pinctrl_flexspi0>;
61	status = "okay";
62
63	flash0: norflash@0 {
64		reg = <0>;
65		#address-cells = <1>;
66		#size-cells = <1>;
67		compatible = "jedec,spi-nor";
68		spi-max-frequency = <80000000>;
69		spi-tx-bus-width = <4>;
70		spi-rx-bus-width = <4>;
71	};
72};
73
74/* i2c eeprom */
75&i2c1 {
76	clock-frequency = <400000>;
77	pinctrl-names = "default", "gpio";
78	pinctrl-0 = <&pinctrl_i2c1>;
79	pinctrl-1 = <&pinctrl_i2c1_gpio>;
80	scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
81	sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
82	status = "okay";
83
84	/* M24C32-D */
85	i2c_eeprom: eeprom@51 {
86		compatible = "atmel,24c32";
87		reg = <0x51>;
88		u-boot,i2c-offset-len = <2>;
89	};
90
91	/* M24C32-D Identification page */
92	i2c_eeprom_id: eeprom@59 {
93		compatible = "atmel,24c32";
94		reg = <0x59>;
95		u-boot,i2c-offset-len = <2>;
96	};
97};
98
99/* debug console */
100&uart3 {
101	pinctrl-names = "default";
102	pinctrl-0 = <&pinctrl_uart3>;
103	status = "okay";
104};
105
106/* sd-card */
107&usdhc2 {
108	pinctrl-names = "default", "state_100mhz", "state_200mhz";
109	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
110	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
111	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
112	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
113	bus-width = <4>;
114	vmmc-supply = <&reg_usdhc2_vmmc>;
115	status = "okay";
116};
117
118/* eMMC */
119&usdhc3 {
120	pinctrl-names = "default", "state_100mhz", "state_200mhz";
121	pinctrl-0 = <&pinctrl_usdhc3>;
122	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
123	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
124	bus-width = <8>;
125	non-removable;
126	status = "okay";
127};
128
129/* watchdog */
130&wdog1 {
131	pinctrl-names = "default";
132	pinctrl-0 = <&pinctrl_wdog>;
133	fsl,ext-reset-output;
134	status = "okay";
135};
136
137&iomuxc {
138	pinctrl-names = "default";
139
140	pinctrl_fec1: fec1grp {
141		fsl,pins = <
142			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3
143			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO	0x3
144			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
145			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
146			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
147			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
148			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
149			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
150			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
151			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
152			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
153			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
154			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
155			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
156			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x19
157		>;
158	};
159
160	pinctrl_flexspi0: flexspi0grp {
161		fsl,pins = <
162			MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK		0x1c2
163			MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B		0x82
164			MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0		0x82
165			MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1		0x82
166			MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2		0x82
167			MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3		0x82
168		>;
169	};
170
171	pinctrl_i2c1: i2c1grp {
172		fsl,pins = <
173			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
174			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
175		>;
176	};
177
178	pinctrl_i2c1_gpio: i2c1grp-gpio {
179		fsl,pins = <
180			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14	0x1c3
181			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15	0x1c3
182		>;
183	};
184
185	pinctrl_uart3: uart3grp {
186		fsl,pins = <
187			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x49
188			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x49
189		>;
190	};
191
192	pinctrl_usdhc2_gpio: usdhc2grpgpio {
193		fsl,pins = <
194			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12        0x41
195		>;
196	};
197
198	pinctrl_usdhc2: usdhc2grp {
199		fsl,pins = <
200			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
201			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
202			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
203			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
204			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
205			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
206			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
207		>;
208	};
209
210	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
211		fsl,pins = <
212			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
213			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
214			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
215			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
216			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
217			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
218			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
219		>;
220	};
221
222	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
223		fsl,pins = <
224			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
225			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
226			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
227			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
228			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
229			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
230			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
231		>;
232	};
233
234	pinctrl_usdhc3: usdhc3grp {
235		fsl,pins = <
236			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000190
237			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
238			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
239			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
240			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
241			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
242			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
243			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
244			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
245			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
246			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190
247		>;
248	};
249
250	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
251		fsl,pins = <
252			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000194
253			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
254			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
255			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
256			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
257			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
258			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
259			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
260			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
261			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
262			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194
263		>;
264	};
265
266	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
267		fsl,pins = <
268			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000196
269			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
270			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
271			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
272			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
273			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
274			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
275			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
276			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
277			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
278			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196
279		>;
280	};
281
282	pinctrl_wdog: wdoggrp {
283		fsl,pins = <
284			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
285		>;
286	};
287};
288