1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2013 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include <dt-bindings/clock/rk3188-cru.h> 10#include <dt-bindings/power/rk3188-power.h> 11#include "rk3xxx.dtsi" 12#include "rk3xxx-u-boot.dtsi" 13 14/ { 15 compatible = "rockchip,rk3188"; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 enable-method = "rockchip,rk3066-smp"; 21 22 cpu0: cpu@0 { 23 device_type = "cpu"; 24 compatible = "arm,cortex-a9"; 25 next-level-cache = <&L2>; 26 reg = <0x0>; 27 clock-latency = <40000>; 28 clocks = <&cru ARMCLK>; 29 operating-points-v2 = <&cpu0_opp_table>; 30 resets = <&cru SRST_CORE0>; 31 }; 32 cpu1: cpu@1 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a9"; 35 next-level-cache = <&L2>; 36 reg = <0x1>; 37 operating-points-v2 = <&cpu0_opp_table>; 38 resets = <&cru SRST_CORE1>; 39 }; 40 cpu2: cpu@2 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a9"; 43 next-level-cache = <&L2>; 44 reg = <0x2>; 45 operating-points-v2 = <&cpu0_opp_table>; 46 resets = <&cru SRST_CORE2>; 47 }; 48 cpu3: cpu@3 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a9"; 51 next-level-cache = <&L2>; 52 reg = <0x3>; 53 operating-points-v2 = <&cpu0_opp_table>; 54 resets = <&cru SRST_CORE3>; 55 }; 56 }; 57 58 cpu0_opp_table: opp_table0 { 59 compatible = "operating-points-v2"; 60 opp-shared; 61 62 opp-312000000 { 63 opp-hz = /bits/ 64 <312000000>; 64 opp-microvolt = <875000>; 65 clock-latency-ns = <40000>; 66 }; 67 opp-504000000 { 68 opp-hz = /bits/ 64 <504000000>; 69 opp-microvolt = <925000>; 70 }; 71 opp-600000000 { 72 opp-hz = /bits/ 64 <600000000>; 73 opp-microvolt = <950000>; 74 opp-suspend; 75 }; 76 opp-816000000 { 77 opp-hz = /bits/ 64 <816000000>; 78 opp-microvolt = <975000>; 79 }; 80 opp-1008000000 { 81 opp-hz = /bits/ 64 <1008000000>; 82 opp-microvolt = <1075000>; 83 }; 84 opp-1200000000 { 85 opp-hz = /bits/ 64 <1200000000>; 86 opp-microvolt = <1150000>; 87 }; 88 opp-1416000000 { 89 opp-hz = /bits/ 64 <1416000000>; 90 opp-microvolt = <1250000>; 91 }; 92 opp-1608000000 { 93 opp-hz = /bits/ 64 <1608000000>; 94 opp-microvolt = <1350000>; 95 }; 96 }; 97 98 display-subsystem { 99 compatible = "rockchip,display-subsystem"; 100 ports = <&vop0_out>, <&vop1_out>; 101 }; 102 103 sram: sram@10080000 { 104 compatible = "mmio-sram"; 105 reg = <0x10080000 0x8000>; 106 #address-cells = <1>; 107 #size-cells = <1>; 108 ranges = <0 0x10080000 0x8000>; 109 110 smp-sram@0 { 111 compatible = "rockchip,rk3066-smp-sram"; 112 reg = <0x0 0x50>; 113 }; 114 }; 115 116 vop0: vop@1010c000 { 117 compatible = "rockchip,rk3188-vop"; 118 reg = <0x1010c000 0x1000>; 119 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 120 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>; 121 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 122 power-domains = <&power RK3188_PD_VIO>; 123 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; 124 reset-names = "axi", "ahb", "dclk"; 125 status = "disabled"; 126 127 vop0_out: port { 128 #address-cells = <1>; 129 #size-cells = <0>; 130 }; 131 }; 132 133 vop1: vop@1010e000 { 134 compatible = "rockchip,rk3188-vop"; 135 reg = <0x1010e000 0x1000>; 136 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 137 clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>; 138 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 139 power-domains = <&power RK3188_PD_VIO>; 140 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; 141 reset-names = "axi", "ahb", "dclk"; 142 status = "disabled"; 143 144 vop1_out: port { 145 #address-cells = <1>; 146 #size-cells = <0>; 147 }; 148 }; 149 150 timer3: timer@2000e000 { 151 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; 152 reg = <0x2000e000 0x20>; 153 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 154 clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>; 155 clock-names = "pclk", "timer"; 156 }; 157 158 timer6: timer@200380a0 { 159 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; 160 reg = <0x200380a0 0x20>; 161 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 162 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>; 163 clock-names = "pclk", "timer"; 164 }; 165 166 i2s0: i2s@1011a000 { 167 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; 168 reg = <0x1011a000 0x2000>; 169 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 170 pinctrl-names = "default"; 171 pinctrl-0 = <&i2s0_bus>; 172 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; 173 clock-names = "i2s_clk", "i2s_hclk"; 174 dmas = <&dmac1_s 6>, <&dmac1_s 7>; 175 dma-names = "tx", "rx"; 176 rockchip,playback-channels = <2>; 177 rockchip,capture-channels = <2>; 178 #sound-dai-cells = <0>; 179 status = "disabled"; 180 }; 181 182 spdif: sound@1011e000 { 183 compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif"; 184 reg = <0x1011e000 0x2000>; 185 #sound-dai-cells = <0>; 186 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>; 187 clock-names = "mclk", "hclk"; 188 dmas = <&dmac1_s 8>; 189 dma-names = "tx"; 190 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 191 pinctrl-names = "default"; 192 pinctrl-0 = <&spdif_tx>; 193 status = "disabled"; 194 }; 195 196 cru: clock-controller@20000000 { 197 compatible = "rockchip,rk3188-cru"; 198 reg = <0x20000000 0x1000>; 199 rockchip,grf = <&grf>; 200 201 #clock-cells = <1>; 202 #reset-cells = <1>; 203 }; 204 205 efuse: efuse@20010000 { 206 compatible = "rockchip,rk3188-efuse"; 207 reg = <0x20010000 0x4000>; 208 #address-cells = <1>; 209 #size-cells = <1>; 210 clocks = <&cru PCLK_EFUSE>; 211 clock-names = "pclk_efuse"; 212 213 cpu_leakage: cpu_leakage@17 { 214 reg = <0x17 0x1>; 215 }; 216 }; 217 218 pinctrl: pinctrl { 219 compatible = "rockchip,rk3188-pinctrl"; 220 rockchip,grf = <&grf>; 221 rockchip,pmu = <&pmu>; 222 223 #address-cells = <1>; 224 #size-cells = <1>; 225 ranges; 226 227 gpio0: gpio0@2000a000 { 228 compatible = "rockchip,rk3188-gpio-bank0"; 229 reg = <0x2000a000 0x100>; 230 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&cru PCLK_GPIO0>; 232 233 gpio-controller; 234 #gpio-cells = <2>; 235 236 interrupt-controller; 237 #interrupt-cells = <2>; 238 }; 239 240 gpio1: gpio1@2003c000 { 241 compatible = "rockchip,gpio-bank"; 242 reg = <0x2003c000 0x100>; 243 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&cru PCLK_GPIO1>; 245 246 gpio-controller; 247 #gpio-cells = <2>; 248 249 interrupt-controller; 250 #interrupt-cells = <2>; 251 }; 252 253 gpio2: gpio2@2003e000 { 254 compatible = "rockchip,gpio-bank"; 255 reg = <0x2003e000 0x100>; 256 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&cru PCLK_GPIO2>; 258 259 gpio-controller; 260 #gpio-cells = <2>; 261 262 interrupt-controller; 263 #interrupt-cells = <2>; 264 }; 265 266 gpio3: gpio3@20080000 { 267 compatible = "rockchip,gpio-bank"; 268 reg = <0x20080000 0x100>; 269 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&cru PCLK_GPIO3>; 271 272 gpio-controller; 273 #gpio-cells = <2>; 274 275 interrupt-controller; 276 #interrupt-cells = <2>; 277 }; 278 279 pcfg_pull_up: pcfg_pull_up { 280 bias-pull-up; 281 }; 282 283 pcfg_pull_down: pcfg_pull_down { 284 bias-pull-down; 285 }; 286 287 pcfg_pull_none: pcfg_pull_none { 288 bias-disable; 289 }; 290 291 emmc { 292 emmc_clk: emmc-clk { 293 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; 294 }; 295 296 emmc_cmd: emmc-cmd { 297 rockchip,pins = <0 RK_PD2 2 &pcfg_pull_up>; 298 }; 299 300 emmc_rst: emmc-rst { 301 rockchip,pins = <0 RK_PD3 2 &pcfg_pull_none>; 302 }; 303 304 /* 305 * The data pins are shared between nandc and emmc and 306 * not accessible through pinctrl. Also they should've 307 * been already set correctly by firmware, as 308 * flash/emmc is the boot-device. 309 */ 310 }; 311 312 emac { 313 emac_xfer: emac-xfer { 314 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>, /* tx_en */ 315 <3 RK_PC1 2 &pcfg_pull_none>, /* txd1 */ 316 <3 RK_PC2 2 &pcfg_pull_none>, /* txd0 */ 317 <3 RK_PC3 2 &pcfg_pull_none>, /* rxd0 */ 318 <3 RK_PC4 2 &pcfg_pull_none>, /* rxd1 */ 319 <3 RK_PC5 2 &pcfg_pull_none>, /* mac_clk */ 320 <3 RK_PC6 2 &pcfg_pull_none>, /* rx_err */ 321 <3 RK_PC7 2 &pcfg_pull_none>; /* crs_dvalid */ 322 }; 323 324 emac_mdio: emac-mdio { 325 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>, 326 <3 RK_PD1 2 &pcfg_pull_none>; 327 }; 328 }; 329 330 i2c0 { 331 i2c0_xfer: i2c0-xfer { 332 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 333 <1 RK_PD1 1 &pcfg_pull_none>; 334 }; 335 }; 336 337 i2c1 { 338 i2c1_xfer: i2c1-xfer { 339 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>, 340 <1 RK_PD3 1 &pcfg_pull_none>; 341 }; 342 }; 343 344 i2c2 { 345 i2c2_xfer: i2c2-xfer { 346 rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>, 347 <1 RK_PD5 1 &pcfg_pull_none>; 348 }; 349 }; 350 351 i2c3 { 352 i2c3_xfer: i2c3-xfer { 353 rockchip,pins = <3 RK_PB6 2 &pcfg_pull_none>, 354 <3 RK_PB7 2 &pcfg_pull_none>; 355 }; 356 }; 357 358 i2c4 { 359 i2c4_xfer: i2c4-xfer { 360 rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>, 361 <1 RK_PD7 1 &pcfg_pull_none>; 362 }; 363 }; 364 365 lcdc1 { 366 lcdc1_dclk: lcdc1-dclk { 367 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>; 368 }; 369 370 lcdc1_den: lcdc1-den { 371 rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>; 372 }; 373 374 lcdc1_hsync: lcdc1-hsync { 375 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>; 376 }; 377 378 lcdc1_vsync: lcdc1-vsync { 379 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>; 380 }; 381 382 lcdc1_rgb24: ldcd1-rgb24 { 383 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, 384 <2 RK_PA1 1 &pcfg_pull_none>, 385 <2 RK_PA2 1 &pcfg_pull_none>, 386 <2 RK_PA3 1 &pcfg_pull_none>, 387 <2 RK_PA4 1 &pcfg_pull_none>, 388 <2 RK_PA5 1 &pcfg_pull_none>, 389 <2 RK_PA6 1 &pcfg_pull_none>, 390 <2 RK_PA7 1 &pcfg_pull_none>, 391 <2 RK_PB0 1 &pcfg_pull_none>, 392 <2 RK_PB1 1 &pcfg_pull_none>, 393 <2 RK_PB2 1 &pcfg_pull_none>, 394 <2 RK_PB3 1 &pcfg_pull_none>, 395 <2 RK_PB4 1 &pcfg_pull_none>, 396 <2 RK_PB5 1 &pcfg_pull_none>, 397 <2 RK_PB6 1 &pcfg_pull_none>, 398 <2 RK_PB7 1 &pcfg_pull_none>, 399 <2 RK_PC0 1 &pcfg_pull_none>, 400 <2 RK_PC1 1 &pcfg_pull_none>, 401 <2 RK_PC2 1 &pcfg_pull_none>, 402 <2 RK_PC3 1 &pcfg_pull_none>, 403 <2 RK_PC4 1 &pcfg_pull_none>, 404 <2 RK_PC5 1 &pcfg_pull_none>, 405 <2 RK_PC6 1 &pcfg_pull_none>, 406 <2 RK_PC7 1 &pcfg_pull_none>; 407 }; 408 }; 409 410 pwm0 { 411 pwm0_out: pwm0-out { 412 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 413 }; 414 }; 415 416 pwm1 { 417 pwm1_out: pwm1-out { 418 rockchip,pins = <3 RK_PD4 1 &pcfg_pull_none>; 419 }; 420 }; 421 422 pwm2 { 423 pwm2_out: pwm2-out { 424 rockchip,pins = <3 RK_PD5 1 &pcfg_pull_none>; 425 }; 426 }; 427 428 pwm3 { 429 pwm3_out: pwm3-out { 430 rockchip,pins = <3 RK_PD6 1 &pcfg_pull_none>; 431 }; 432 }; 433 434 spi0 { 435 spi0_clk: spi0-clk { 436 rockchip,pins = <1 RK_PA6 2 &pcfg_pull_up>; 437 }; 438 spi0_cs0: spi0-cs0 { 439 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_up>; 440 }; 441 spi0_tx: spi0-tx { 442 rockchip,pins = <1 RK_PA5 2 &pcfg_pull_up>; 443 }; 444 spi0_rx: spi0-rx { 445 rockchip,pins = <1 RK_PA4 2 &pcfg_pull_up>; 446 }; 447 spi0_cs1: spi0-cs1 { 448 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_up>; 449 }; 450 }; 451 452 spi1 { 453 spi1_clk: spi1-clk { 454 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>; 455 }; 456 spi1_cs0: spi1-cs0 { 457 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_up>; 458 }; 459 spi1_rx: spi1-rx { 460 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_up>; 461 }; 462 spi1_tx: spi1-tx { 463 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_up>; 464 }; 465 spi1_cs1: spi1-cs1 { 466 rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>; 467 }; 468 }; 469 470 uart0 { 471 uart0_xfer: uart0-xfer { 472 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>, 473 <1 RK_PA1 1 &pcfg_pull_none>; 474 }; 475 476 uart0_cts: uart0-cts { 477 rockchip,pins = <1 RK_PA2 1 &pcfg_pull_none>; 478 }; 479 480 uart0_rts: uart0-rts { 481 rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>; 482 }; 483 }; 484 485 uart1 { 486 uart1_xfer: uart1-xfer { 487 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>, 488 <1 RK_PA5 1 &pcfg_pull_none>; 489 }; 490 491 uart1_cts: uart1-cts { 492 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; 493 }; 494 495 uart1_rts: uart1-rts { 496 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_none>; 497 }; 498 }; 499 500 uart2 { 501 uart2_xfer: uart2-xfer { 502 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>, 503 <1 RK_PB1 1 &pcfg_pull_none>; 504 }; 505 /* no rts / cts for uart2 */ 506 }; 507 508 uart3 { 509 uart3_xfer: uart3-xfer { 510 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>, 511 <1 RK_PB3 1 &pcfg_pull_none>; 512 }; 513 514 uart3_cts: uart3-cts { 515 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none>; 516 }; 517 518 uart3_rts: uart3-rts { 519 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_none>; 520 }; 521 }; 522 523 sd0 { 524 sd0_clk: sd0-clk { 525 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>; 526 }; 527 528 sd0_cmd: sd0-cmd { 529 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>; 530 }; 531 532 sd0_cd: sd0-cd { 533 rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>; 534 }; 535 536 sd0_wp: sd0-wp { 537 rockchip,pins = <3 RK_PB1 1 &pcfg_pull_none>; 538 }; 539 540 sd0_pwr: sd0-pwr { 541 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>; 542 }; 543 544 sd0_bus1: sd0-bus-width1 { 545 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>; 546 }; 547 548 sd0_bus4: sd0-bus-width4 { 549 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, 550 <3 RK_PA5 1 &pcfg_pull_none>, 551 <3 RK_PA6 1 &pcfg_pull_none>, 552 <3 RK_PA7 1 &pcfg_pull_none>; 553 }; 554 }; 555 556 sd1 { 557 sd1_clk: sd1-clk { 558 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; 559 }; 560 561 sd1_cmd: sd1-cmd { 562 rockchip,pins = <3 RK_PC0 1 &pcfg_pull_none>; 563 }; 564 565 sd1_cd: sd1-cd { 566 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>; 567 }; 568 569 sd1_wp: sd1-wp { 570 rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>; 571 }; 572 573 sd1_bus1: sd1-bus-width1 { 574 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>; 575 }; 576 577 sd1_bus4: sd1-bus-width4 { 578 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>, 579 <3 RK_PC2 1 &pcfg_pull_none>, 580 <3 RK_PC3 1 &pcfg_pull_none>, 581 <3 RK_PC4 1 &pcfg_pull_none>; 582 }; 583 }; 584 585 i2s0 { 586 i2s0_bus: i2s0-bus { 587 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>, 588 <1 RK_PC1 1 &pcfg_pull_none>, 589 <1 RK_PC2 1 &pcfg_pull_none>, 590 <1 RK_PC3 1 &pcfg_pull_none>, 591 <1 RK_PC4 1 &pcfg_pull_none>, 592 <1 RK_PC5 1 &pcfg_pull_none>; 593 }; 594 }; 595 596 spdif { 597 spdif_tx: spdif-tx { 598 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_none>; 599 }; 600 }; 601 }; 602}; 603 604&emac { 605 compatible = "rockchip,rk3188-emac"; 606}; 607 608&global_timer { 609 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 610 status = "disabled"; 611}; 612 613&local_timer { 614 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 615}; 616 617&gpu { 618 compatible = "rockchip,rk3188-mali", "arm,mali-400"; 619 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 629 interrupt-names = "gp", 630 "gpmmu", 631 "pp0", 632 "ppmmu0", 633 "pp1", 634 "ppmmu1", 635 "pp2", 636 "ppmmu2", 637 "pp3", 638 "ppmmu3"; 639 power-domains = <&power RK3188_PD_GPU>; 640}; 641 642&grf { 643 compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd"; 644 645 usbphy: usbphy { 646 compatible = "rockchip,rk3188-usb-phy", 647 "rockchip,rk3288-usb-phy"; 648 #address-cells = <1>; 649 #size-cells = <0>; 650 status = "disabled"; 651 652 usbphy0: usb-phy@10c { 653 reg = <0x10c>; 654 clocks = <&cru SCLK_OTGPHY0>; 655 clock-names = "phyclk"; 656 #clock-cells = <0>; 657 #phy-cells = <0>; 658 }; 659 660 usbphy1: usb-phy@11c { 661 reg = <0x11c>; 662 clocks = <&cru SCLK_OTGPHY1>; 663 clock-names = "phyclk"; 664 #clock-cells = <0>; 665 #phy-cells = <0>; 666 }; 667 }; 668}; 669 670&i2c0 { 671 compatible = "rockchip,rk3188-i2c"; 672 pinctrl-names = "default"; 673 pinctrl-0 = <&i2c0_xfer>; 674}; 675 676&i2c1 { 677 compatible = "rockchip,rk3188-i2c"; 678 pinctrl-names = "default"; 679 pinctrl-0 = <&i2c1_xfer>; 680}; 681 682&i2c2 { 683 compatible = "rockchip,rk3188-i2c"; 684 pinctrl-names = "default"; 685 pinctrl-0 = <&i2c2_xfer>; 686}; 687 688&i2c3 { 689 compatible = "rockchip,rk3188-i2c"; 690 pinctrl-names = "default"; 691 pinctrl-0 = <&i2c3_xfer>; 692}; 693 694&i2c4 { 695 compatible = "rockchip,rk3188-i2c"; 696 pinctrl-names = "default"; 697 pinctrl-0 = <&i2c4_xfer>; 698}; 699 700&pmu { 701 power: power-controller { 702 compatible = "rockchip,rk3188-power-controller"; 703 #power-domain-cells = <1>; 704 #address-cells = <1>; 705 #size-cells = <0>; 706 707 power-domain@RK3188_PD_VIO { 708 reg = <RK3188_PD_VIO>; 709 clocks = <&cru ACLK_LCDC0>, 710 <&cru ACLK_LCDC1>, 711 <&cru DCLK_LCDC0>, 712 <&cru DCLK_LCDC1>, 713 <&cru HCLK_LCDC0>, 714 <&cru HCLK_LCDC1>, 715 <&cru SCLK_CIF0>, 716 <&cru ACLK_CIF0>, 717 <&cru HCLK_CIF0>, 718 <&cru ACLK_IPP>, 719 <&cru HCLK_IPP>, 720 <&cru ACLK_RGA>, 721 <&cru HCLK_RGA>; 722 pm_qos = <&qos_lcdc0>, 723 <&qos_lcdc1>, 724 <&qos_cif0>, 725 <&qos_ipp>, 726 <&qos_rga>; 727 #power-domain-cells = <0>; 728 }; 729 730 power-domain@RK3188_PD_VIDEO { 731 reg = <RK3188_PD_VIDEO>; 732 clocks = <&cru ACLK_VDPU>, 733 <&cru ACLK_VEPU>, 734 <&cru HCLK_VDPU>, 735 <&cru HCLK_VEPU>; 736 pm_qos = <&qos_vpu>; 737 #power-domain-cells = <0>; 738 }; 739 740 power-domain@RK3188_PD_GPU { 741 reg = <RK3188_PD_GPU>; 742 clocks = <&cru ACLK_GPU>; 743 pm_qos = <&qos_gpu>; 744 #power-domain-cells = <0>; 745 }; 746 }; 747}; 748 749&pwm0 { 750 pinctrl-names = "default"; 751 pinctrl-0 = <&pwm0_out>; 752}; 753 754&pwm1 { 755 pinctrl-names = "default"; 756 pinctrl-0 = <&pwm1_out>; 757}; 758 759&pwm2 { 760 pinctrl-names = "default"; 761 pinctrl-0 = <&pwm2_out>; 762}; 763 764&pwm3 { 765 pinctrl-names = "default"; 766 pinctrl-0 = <&pwm3_out>; 767}; 768 769&spi0 { 770 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; 771 pinctrl-names = "default"; 772 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 773}; 774 775&spi1 { 776 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; 777 pinctrl-names = "default"; 778 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 779}; 780 781&uart0 { 782 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; 783 pinctrl-names = "default"; 784 pinctrl-0 = <&uart0_xfer>; 785}; 786 787&uart1 { 788 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; 789 pinctrl-names = "default"; 790 pinctrl-0 = <&uart1_xfer>; 791}; 792 793&uart2 { 794 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; 795 pinctrl-names = "default"; 796 pinctrl-0 = <&uart2_xfer>; 797}; 798 799&uart3 { 800 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; 801 pinctrl-names = "default"; 802 pinctrl-0 = <&uart3_xfer>; 803}; 804 805&vpu { 806 compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu"; 807 power-domains = <&power RK3188_PD_VIDEO>; 808}; 809 810&wdt { 811 compatible = "rockchip,rk3188-wdt", "snps,dw-wdt"; 812}; 813