1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sam9x60.dtsi - Device Tree Include file for SAM9X60 SoC. 4 * 5 * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries 6 * 7 * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com> 8 */ 9 10#include "skeleton.dtsi" 11#include <dt-bindings/dma/at91.h> 12#include <dt-bindings/pinctrl/at91.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/clk/at91.h> 16 17/{ 18 model = "Microchip SAM9X60 SoC"; 19 compatible = "microchip,sam9x60"; 20 21 aliases { 22 serial0 = &dbgu; 23 gpio0 = &pioA; 24 gpio1 = &pioB; 25 gpio3 = &pioD; 26 spi0 = &qspi; 27 }; 28 29 clocks { 30 slow_rc_osc: slow_rc_osc { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <18500>; 34 }; 35 36 main_rc: main_rc { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <12000000>; 40 }; 41 42 slow_xtal: slow_xtal { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 }; 46 47 main_xtal: main_xtal { 48 compatible = "fixed-clock"; 49 #clock-cells = <0>; 50 }; 51 }; 52 53 cpus { 54 #address-cells = <1>; 55 #size-cells = <0>; 56 57 ARM9260_0: cpu@0 { 58 device_type = "cpu"; 59 compatible = "arm,arm926ej-s"; 60 clocks = <&pmc PMC_TYPE_CORE 19>, <&pmc PMC_TYPE_CORE 11>, <&main_xtal>; 61 clock-names = "cpu", "master", "xtal"; 62 }; 63 }; 64 65 ahb { 66 compatible = "simple-bus"; 67 #address-cells = <1>; 68 #size-cells = <1>; 69 ranges; 70 71 sdhci0: sdhci-host@80000000 { 72 compatible = "microchip,sam9x60-sdhci"; 73 reg = <0x80000000 0x300>; 74 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>; 75 clock-names = "hclock", "multclk"; 76 assigned-clocks = <&pmc PMC_TYPE_GCK 12>; 77 assigned-clock-rates = <100000000>; 78 assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */ 79 bus-width = <4>; 80 pinctrl-names = "default"; 81 pinctrl-0 = <&pinctrl_sdhci0>; 82 }; 83 84 apb { 85 compatible = "simple-bus"; 86 #address-cells = <1>; 87 #size-cells = <1>; 88 ranges; 89 90 qspi: spi@f0014000 { 91 compatible = "microchip,sam9x60-qspi"; 92 reg = <0xf0014000 0x100>, <0x70000000 0x10000000>; 93 reg-names = "qspi_base", "qspi_mmap"; 94 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 18>; /* ID_QSPI */ 95 clock-names = "pclk", "qspick"; 96 #address-cells = <1>; 97 #size-cells = <0>; 98 status = "disabled"; 99 }; 100 101 flx0: flexcom@f801c600 { 102 compatible = "atmel,sama5d2-flexcom"; 103 reg = <0xf801c000 0x200>; 104 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 105 #address-cells = <1>; 106 #size-cells = <1>; 107 ranges = <0x0 0xf801c000 0x800>; 108 status = "disabled"; 109 }; 110 111 macb0: ethernet@f802c000 { 112 compatible = "cdns,sam9x60-macb", "cdns,macb"; 113 reg = <0xf802c000 0x100>; 114 pinctrl-names = "default"; 115 pinctrl-0 = <&pinctrl_macb0_rmii>; 116 clock-names = "hclk", "pclk"; 117 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>; 118 status = "disabled"; 119 }; 120 121 dbgu: serial@fffff200 { 122 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 123 reg = <0xfffff200 0x200>; 124 pinctrl-names = "default"; 125 pinctrl-0 = <&pinctrl_dbgu>; 126 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 127 clock-names = "usart"; 128 }; 129 130 pinctrl { 131 #address-cells = <1>; 132 #size-cells = <1>; 133 compatible = "microchip,sam9x60-pinctrl", "simple-bus"; 134 ranges = <0xfffff400 0xfffff400 0x800>; 135 reg = <0xfffff400 0x200 /* pioA */ 136 0xfffff600 0x200 /* pioB */ 137 0xfffff800 0x200 /* pioC */ 138 0xfffffa00 0x200>; /* pioD */ 139 140 /* shared pinctrl settings */ 141 dbgu { 142 pinctrl_dbgu: dbgu-0 { 143 atmel,pins = 144 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP 145 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; 146 }; 147 }; 148 149 macb0 { 150 pinctrl_macb0_rmii: macb0_rmii-0 { 151 atmel,pins = 152 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */ 153 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */ 154 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */ 155 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */ 156 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ 157 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */ 158 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ 159 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ 160 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ 161 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */ 162 }; 163 }; 164 165 sdhci0 { 166 pinctrl_sdhci0: sdhci0 { 167 atmel,pins = 168 <AT91_PIOA 17 AT91_PERIPH_A 169 (AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA17 CK periph A with pullup */ 170 AT91_PIOA 16 AT91_PERIPH_A 171 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA16 CMD periph A with pullup */ 172 AT91_PIOA 15 AT91_PERIPH_A 173 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA15 DAT0 periph A */ 174 AT91_PIOA 18 AT91_PERIPH_A 175 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA18 DAT1 periph A with pullup */ 176 AT91_PIOA 19 AT91_PERIPH_A 177 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA19 DAT2 periph A with pullup */ 178 AT91_PIOA 20 AT91_PERIPH_A 179 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>; /* PA20 DAT3 periph A with pullup */ 180 }; 181 }; 182 }; 183 184 pioA: gpio@fffff400 { 185 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 186 reg = <0xfffff400 0x200>; 187 #gpio-cells = <2>; 188 gpio-controller; 189 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; 190 }; 191 192 pioB: gpio@fffff600 { 193 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 194 reg = <0xfffff600 0x200>; 195 #gpio-cells = <2>; 196 gpio-controller; 197 clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; 198 }; 199 200 pioD: gpio@fffffa00 { 201 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 202 reg = <0xfffffa00 0x200>; 203 #gpio-cells = <2>; 204 gpio-controller; 205 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; 206 }; 207 208 pmc: pmc@fffffc00 { 209 compatible = "microchip,sam9x60-pmc"; 210 reg = <0xfffffc00 0x200>; 211 #clock-cells = <2>; 212 clocks = <&clk32 1>, <&clk32 0>, <&main_xtal>, <&main_rc>; 213 clock-names = "td_slck", "md_slck", "main_xtal", "main_rc"; 214 status = "okay"; 215 }; 216 217 pit: timer@fffffe40 { 218 compatible = "atmel,at91sam9260-pit"; 219 reg = <0xfffffe40 0x10>; 220 clocks = <&pmc PMC_TYPE_CORE 11>; /* ID_MCK. */ 221 }; 222 223 clk32: sckc@fffffe50 { 224 compatible = "microchip,sam9x60-sckc"; 225 reg = <0xfffffe50 0x4>; 226 clocks = <&slow_rc_osc>, <&slow_xtal>; 227 #clock-cells = <1>; 228 }; 229 }; 230 }; 231 232 onewire_tm: onewire { 233 compatible = "w1-gpio"; 234 status = "disabled"; 235 }; 236}; 237